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Parts of a SOM (Self-Organizing Map) based quantizer can be performed in parallel; i.e. distance calculation between an input pixel and a group of codewords or processing elements (PEs), and updating weight of PEs. To search for the best matching unit (BMU) whose distance is the minimum, all distances are inevitably required to compare with each other. Conventionally, the minimum distance searching unit is constructed from a group of comparators which are connected in a multistage manner in order to come up with the final single minimum distance and its index. In this way, the overall latency of the unit is linearly proportional to the number of stage of comparators log 2 ( C ) where C is the number of distances. In this paper, we propose a novel hardware centric algorithm with the objective to reduce the latency for the minimum distance searching unit. In a simple form, the algorithm relies on using a memory of K addresses of 1-bit word size where K is equal to the maximum value of distance. During operation, all distances are used to refer to the memory addresses in order to change their states from ‘unoccupied’ to ‘occupied’. To efficiently search for the first address whose state is ‘occupied’, which is equivalent to the minimum distance, the look up table is employed. The algorithm is also adapted to make it more feasible to realize on an FPGA platform. The synthesis results compared with the conventional minimum distance searching indicate that the FPGA resource requirements of the algorithm are twice in terms of slices and LUT usages. In term of latency reduction, the implementation takes only 0.62 times of the conventional one for a PE size of 256. After integrating the unit to the SOM based quantizer, it has found that the obtained frame rate is 1.50 times of the conventional one for a PE size of 256, the image size of 512 × 512 and the clock speed of 66.67 MHz. The latency reduction can be further improved if the FPGA supports combining all the ‘occupied’ states in a single stage in contrast to use a group of internal limited input size LUTs. [ABSTRACT FROM AUTHOR]

In this paper, a new dynamic logic style is proposed to reduce the power consumption and delay of wide fan-in gates used in tag comparators. In the proposed dynamic circuit, a large pull-down network (PDN) is partitioned into smaller networks to decrease the parasitic capacitance on the dynamic node. As a result, a weak keeper transistor is sufficient to achieve the desired robustness, and hence the contention current between the keeper transistor and pull-down networks is reduced. Lower contention causes lower delay and power consumption in the proposed dynamic circuit. Simulation of wide fan-in OR gates and 40-bit tag comparators are performed using HSPICE simulator in a 90 nm CMOS technology model. Simulation results indicate 38% and 42% reduction in power and delay, respectively, at the same noise immunity compared to the conventional dynamic circuit for 64-bit OR gates. In addition, simulation results exhibit 34% and 21% reduction in the power consumption and delay of the proposed tag comparator, respectively, compared to the conventional design at the same noise immunity. [ABSTRACT FROM AUTHOR]

Majority, minority gates and inverters are the natural logic element of several beyond-CMOS emerging nanotechnologies. Magnitude comparators are components used in computer systems to compare if two binary numbers are equal or if one number is greater or less than the other. Therefore, efficient majority logic implementation of magnitude comparators is highly desirable. The proposed majority logic magnitude comparators have lower circuit and delay complexity compared against the already published majority logic magnitude comparator designs. [ABSTRACT FROM AUTHOR]

The DC-DC converter is used for different applications which needs higher voltages when compared to the input source. The boost converter is one of the most efficient methods to choose DC-DC Converter in different ways. The purpose of the proposed method is to reduce the area of VLSI design logic and power consumption. Boost converter topology is difficult because it has a large component. The proposed work of four transistor comparator based PWM (Pulse width Modulator) that can be used in DC-DC boost converter, which reduces the area, and power consumption of the entire system. This proposed work calculates the parameters of boost converter and the simulation performed using different duty cycle and parameters. Simulation results shows different duty cycles with different resistance and inductance parameters using boost converter. In addition to this the result carries out four transistor comparator output which is used to reduce the boost converter circuit design. PWM is based on the proposed four transistor comparator, which is used in the Cadence Virtuoso software using conventional CMOS technology. [ABSTRACT FROM AUTHOR]

Reversible or information lossless gates have applications in nano-technology, digital signal processing (DSP), communication, computer graphics and cryptography. Gate-diffusion input (GDI) technique can provide the possibility of designing fundamental gates in ultra-low power and layout chip area with low number of transistors. A reversible logic-based single-bit magnitude comparator (RMC) circuit is presented by using the modified-GDI (m-GDI) method-based reversible gates for designing RMC in any arbitrary number of bit levels for processing at nano-scales. In this paper, several figure of merits (FOMs) like: energy consumption-propagation delay product (EDP) and worst delay-power consumption-chip area product (DPA) are evaluated and compared with other designs. The simulation results show the improvement of the evaluation parameters of the proposed RMC in compare with the other similar basic GDI-based comparators. Also, according to the simulation results, presented comparator is capable to work at extensive frequency ranges with higher maximum operating frequency (f max.). The effects of different process, voltage and the temperature (PVT) variations are extensively evaluated by Monte-Carlo simulation. According to the results, the proposed circuit is robust against PVT variations and also noise-tolerable parameter. Moreover, the proposed RMC architecture is used in images applications. The results show that output images of the proposed inexact RMC have a very high quality and resemblance to the images generated by exact RMC, thus excellent values for the peak signal-to-noise ratio (PSNR) and mean structural similarity index metric (MSSIM) indicate that the proposed inexact RMC circuit has a proper accuracy for applications such as: comparative analysis in medical images, motion detector, edge detection and segmentation in nano-technology. Therefore, using the proposed scheme can be improved in comparator circuit in chips for future generation of VLSI and ULSI blocks, like: nano-processors performance. [ABSTRACT FROM AUTHOR]

• A novel sorting technique called Vasanth sorting is proposed using 25 comparisons to sort 9 numbers in increasing order. • A novel parallel VLSI architecture for Vasanth sorting was also formulated. • The parallel VLSI architecture was targetted for Virtex and Virtex 7 devices and results were tabulated in terms of area, speed, power. • The proposed parallel VLSI architecture for Vasanth sorting was compared with standard sorting techniques and found to be area efficient and works at high speed when compared to existing sorting algorithms. An efficient VLSI architecture for minimized sorting network (Vasanth sorting) in rank ordering application to remove salt and pepper noise is proposed. The basic operation in salt and pepper noise removal is rank ordering. In this work, a novel 2D sorting technique referred to as Vasanth sorting is proposed for a fixed 3 × 3 window. Vasanth sorting requires only 25 comparators to sort 9 elements of the window. A parallel architecture is developed for Vasanth sorting with 25 comparators. The processing element of the parallel architecture is an 8-bit data comparator (Two cell comparator). The performance of the proposed sorting technique is compared with the different sorting technique which is targeted for XCV1000-5bg560 on XILINX 7.1i and xc7v2000t-2flg1925 Xilinx 14.7 project manager respectively with Modelsim 10.4a for simulation and XST compiler tool for synthesis using VHDL. It was found that the parallel architecture developed for Vasanth sorting requires the only ¼ of the area in FPGA when compared to existing sorting techniques. The combinational delay of the proposed architecture was also twice as less like their counterparts. The power consumption of the logic was 7mw. Hence the above performances make Vasanth sorting a better choice compared to existing techniques for rank ordering. [ABSTRACT FROM AUTHOR]