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Abstract: With the growth of the embedded devices consumer market, power efficient hardware is needed. Therefore power-aware architectural exploration is one of the most crucial design steps. For such an exploration procedure, it is important to accurately model the power consumption of all main components of the embedded system. Registers and register files are one of the highest power consumers of any programmable processor, but there is a lack of accurate and publicly available models. This paper provides such a power model for standard cell based register files for 130 and 90nm technologies. The proposed model provides dynamic power, leakage power, area and timing information for register files in terms of key parameters like width, depth, activity, ports, and capacitive loading. It is shown that current models capture neither correct absolute nor relative trends present in register files. It is shown that some key, but often neglected parameters like switching activity, load have a larger influence in some particular sizes of the register files than others. Therefore, using the Empire model, accurate architectural exploration is possible. [Copyright &y& Elsevier]

Abstract: In deeply scaled CMOS technologies, Bias Temperature Instability (BTI) is one of the most critical degradation mechanisms impacting the device reliability. This study presents the BTI evaluation of gates covering both the PMOS and NMOS degradation in a workload dependent, atomistic trap-based, stochastic BTI model. The gate propagation delay depends on the gate intrinsic delay, the input signal characteristics, and the output load. In this paper, the impact of (1) duty factor, (2) periodic clock-based and non-periodic random input sequences, (3) gate, and (4) drive strength to the BTI degradation are investigated. Statistical studies show a mean degradation of 3% and a worst-case of 27%. Moreover, the near-critical paths with lower drive strength cells are 3.7× more susceptible to BTI degradation than the critical paths with higher drive strength cells. Next, the relative degradations of the propagation delays for the well-known gates (i.e. INV, NAND, NOR, AOI) are presented. Under the same stress stimuli, degradations of the gate propagation delays differ by 4.5×. [Copyright &y& Elsevier]

Negative Bias Temperature Instability (NBTI) is one of the major time-dependent degradation mechanisms that impact the reliability of advanced deeply scaled CMOS technologies. NBTI can cause workload-dependent shifts on a transistor’s threshold voltage ( V TH ), and performance during its lifetime. This study presents a comparison of the NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes. The first part of the study focuses on the NBTI-induced performance degradation of 32-bit adders (one of the most fundamental block of a processor’s arithmetic logic unit) from the points of architectural topology and workload dependency in the planar technologies (i.e. commercial 28 , 45 , 65 nm nodes), while the second part investigates the energy-delay product degradation of ring oscillators beyond the planar nodes (i.e. research-grade 14 , 10 , 7 nm FinFET technology nodes for several FET channel materials, e.g. Si, SiGe, Ge, InGaAs). Results show the tight coupling between the NBTI aging and the architectural topology, run-time workload, and technology choice. [ABSTRACT FROM AUTHOR]