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Processor vendors have been expanding Single Instruction Multiple Data (SIMD) extensions to exploit data-level-parallelism in their General Purpose Processors (GPPs). Each SIMD technology such as Streaming SIMD Extensions (SSE) and Advanced Vector eXtensions (AVX) has its own Instruction Set Architecture (ISA) which equipped with Special Purpose Instructions (SPIs). In order to exploit these features, many programming approaches have been developed. Intrinsic Programming Model (IPM) is a low-level concept for explicit SIMDization. Besides, Compiler’s Automatic Vectorization (CAV) has been embedded in modern compilers such as Intel C++ compiler (ICC), GNU Compiler Collections (GCC) and LLVM for implicit vectorization. Each SIMDization shows different improvements because of different SIMD ISAs, vector register width, and programming approaches. Our goal in this paper is to evaluate the performance of explicit and implicit vectorization. Our experimental results show that the behavior of explicit vectorization on different compilers is almost the same compared to implicit vectorization. IPM improves the performance more than CAVs. In general, ICC and GCC compilers can more efficiently vectorize kernels and use SPI compared to LLVM. In addition, AVX2 technology is more useful for small matrices and compute-intensive kernels compared to large matrices and data-intensive kernels because of memory bottlenecks. Furthermore, CAVs fail to vectorize kernels which have overlapping and non-consecutive memory access patterns. The way of implementation of a kernel impacts the vectorization. In order to understand what kind of scalar implementations of an algorithm is suitable for vectorization, an approach based on code modification technique is proposed. Our experimental results show that scalar implementations that have either loop collapsing, loop unrolling, software pipelining, or loop exchange techniques can be efficiently vectorized compared to straightforward implementations.

Data processing on a continuously growing volume of data and the increasing power restrictions have become an ubiquitous challenge in our world today. Besides parallel computing, a promising approach to improve the energy efficiency of current systems is to integrate specialized hardware. This paper presents two application-specific architectures to accelerate basic database operators frequently used in modern database systems: an extended instruction set based on a given Cadence Tensilica processor(ASIP) and a comparable application-specific integrated circuit(ASIC). The ASIP is implemented in a system-on-chip and manufactured in a 28nm CMOS technology to realize measurements of performance and power consumption. Furthermore, the comparison with the ASIC blocks allows to quantify the results with the ASIP approach in terms of throughput, area, and energy efficiency as well as to discuss the capabilities and limitations when accelerating selected database operators.

In this paper, we have proposed an efficient method for integrating longer pipeline coprocessors with SPARCv8 compliant processor implementations that requires minimum changes in the existing processor pipeline. The proposed integration method is independent of the length of the coprocessor pipeline. We have used COordinate Rotation DIgital Computer (CORDIC) core as the coprocessor that has been integrated with SPARCv8 based LEON3 processor. Only a subset of the coprocessor instructions defined in the Instruction Set Architecture (ISA) are required in our proposed method. The required synchronisation of data and control signals between the coprocessor and LEON3 pipeline has been presented in detail. The performance of the resulting closely-coupled design is compared with bus-based integration in terms of speed, power and area in the System-on-Chip (SoC) design, and both FPGA and ASIC results are reported. Our proposed integration method shows significant improvements over bus-based method for applications that require consecutive coprocessor operations in terms of CPI metric along with substantial reduction in number of cycles. Similar strategy can be employed for integration with coprocessors having different pipeline lengths.

Although technology advancement can pack more and more physical registers in processors, the numbers of architectural registers defined by the instruction set architectures (ISAs) remain relatively small on most modern processors. Exposing more architectural registers to compilers and programmers can improve the effectiveness of compiler optimization and the quality of code. However, increasing the number of architectural registers by simply adding extra bits to the register fields of instructions will expand the code size. Therefore, a better way of exposing more ISA registers without significantly expanding the code size is needed. This paper presents a new ISA called Floating Accumulator Architecture (FAA) that can expand the number of ISA registers without increasing the instruction length. Unlike the accumulator architecture whose accumulator is a fixed, special register, FAA dynamically chooses a register from the general-purpose register file as the accumulator. In other words, the accumulator in FAA is an alias to some register in the register file at any instruction, and the alias relation can be dynamically updated by FAA at any program points. Since the accumulator implicitly stores the result, the destination register field can be omitted from FAA instructions, resulting in a saving of 3 to 5 bits for each instruction. This new free instruction bit space can be utilized in two possible ways: doubling the number of ISA registers of modern 32-bit RISC processors or maintaining the number of ISA registers for 16-bit instructions on embedded processors. This paper presents the result of utilizing the free bit space to double the number of ISA registers from 16 to 32 on ARM processors, and experimental results show that performance can be improved by 7.6% on average for MediaBench benchmarks.

In the high-speed free-form surface machining, the real-time motion planning and interpolation is a challenging task. This paper presents the design and implementation of a dedicated processor for the interpolation task in computerized numerical control (CNC) machine tools. The jerk-limited look-ahead motion planning and interpolation algorithm has been integrated in the interpolation processor to achieve smooth motion in the high-speed machining. The processor features a compactly designed floating-point parallel computing architecture, which employs a 3-stage pipelined reduced instruction set computer (RISC) core and a very long instruction word (VLIW) floating-point arithmetic unit. A new asynchronous execution mechanism has been employed in the processor to allow multi-cycle instructions to be performed in parallel. The proposed processor has been verified on a low-cost field programmable gate array (FPGA) chip in a prototype controller. Experimental result has demonstrated the significant improvement of the computing performance with the interpolation processor in the free-form surface machining.

Side-channel attacks are currently among the most serious threats for embedded systems. Popular countermeasures to mitigate the impact of such attacks are masking schemes, where secret intermediate values are split in two or more values by virtue of secret sharing. Processing the secret happens on separate execution paths, which are executed on the same central processing unit (CPU). In case of unwanted correlations between different registers inside the CPU the shared secret may leak out through a side-channel. This problem is particularly evident on low cost embedded systems, such as nodes for the Internet of Things (IoT), where cryptographic algorithms are often implemented in pure software on a reduced instruction set computer (RISC). On such an architecture, all data manipulation operations are carried out on the contents of the CPU's register file. This means that all intermediate values of the cryptographic algorithm at some stage pass through the register file. Towards avoiding unwanted correlations and leakages thereof, special care has to be taken in the mapping of the registers to intermediate values of the algorithm. In this work, we describe an empirical study that reveals effects of unintended unmasking of masked intermediate values and thus leaking secret values. The observed phenomena are related to the leakage of masked hardware implementations caused by glitches in the combinatorial path of the circuit but the effects are abstracted to the level of the instruction set architecture on a RISC CPU. Furthermore, we discuss countermeasures to have the compiler thwart such leakages.

The paper discusses the design process of a programmable logic controller implemented by means of an FPGA device. The PLC implements on the machine language level a subset of the instruction set defined in the EN 61131-3 norm. Different aspects of instruction list and hardware architecture design are presented, however two aspects are the most important: Central Processing Unit (CPU) and the Arithmetic and Logic Unit (ALU). The ALU can execute 34 operations, which include the basic logic operations, comparators, and the four basic arithmetic operations. The operations can be performed for fixed-point and floating-point numbers. All the operations are implemented fully in hardware, so the solution is fast. The developed PLC is implemented using an FPGA device; however, the HDL models used for synthesis can be easily ported to an ASIC.

Contemporary embedded systems require low-power solutions while still keeping a minimum performance level, and this is even more acute in the Internet of Things (IoT) domain, with its vast design space. This work proposes a configurable RISC processor associated to a design flow that includes a hardware synthesis flow and a software toolchain. This design flow is useful to explore design space and trade-offs of processor cores for IoT applications, by enabling multiple hardware configurations with variable degrees of complexity, while maintaining compatibility with the chosen instruction set architecture, which is itself configurable. Results rely on example designs targeting a 65 nm technology and post-mapped hardware simulations of two benchmarks sets, the CoreMark and Malardalen suites. These results indicate that substantial power savings can be obtained by tailoring the architecture to a given application class, while reducing hardware complexity and maintaining performance figures. Findings show that the proposed processor provides an interesting resource to target low-end and middle-sized IoT applications, while demonstrating that reducing hardware complexity usually leads to the best trade-off between performance and power.

Scaling new-silicons to nano-scale era has brought more integration, high performance and low power consumption while the reliability becomes a serious challenge for integrated circuits technology. Therefore, reliability awareness has become essential in early stages of integrated circuit design. Since many of modern chips scrimmage with the limited power budget and traditional techniques such as N-Modular Redundancy (NMR) is not efficient for non-uniform fault tolerance, accurate analyzing of the reliability of different hardware components or application parts is necessary. Transient and soft errors which are resulted from cosmic rays strike and Process Voltage and Temperature (PVT) variation are known as main sources of unreliability. Recently, Architectural Vulnerability Factor (AVF) is widely used for analyzing the reliability of a processors. In this paper, we have introduced a new metric named as Instruction Vulnerability Factor (IVF) which is used for fast, accurate, and recurring AVF estimation. Special scenarios have been developed which enable us to utilize exhaustive fault injection for precise IVF calculation for a given processor instruction set. IVFs of a special instruction considers the vulnerability of pipeline stages while executing the instruction. Finally, a simple equation has been derived for AVF estimation based on running instructions. Our experimental results which are extracted by our Configurable Reliability Analysis Framework (CRAF) confirm the accuracy of presented AVF estimation method. Moreover, IVF can be employed by reliability aware compilation or online AVF estimation techniques.

With continuous scaling down of the semiconductor technology, the soft errors induced by energetic particles have become an increasing challenge in designing current and next-generation reliable microprocessors. Due to their large share of the transistor budget and die area, cache memories suffer from an increasing vulnerability against soft errors. Previous work based on the vulnerability factor (VF) analysis proposed analytical models to evaluate the reliability of on-chip data and instruction caches. However, we have no possession of a system-level study on the vulnerability of instruction caches. In this paper, we propose a new analytical model to estimate the system-level vulnerability factor for on-chip instruction caches in embedded processors. In our model, the error masking/detection effects in instructions based on the Instruction Set Architecture (ISA) are studied. Our experimental results show that the self-error-masking/detection in instructions will reduce the VF of the instruction caches compared to the previous study. We also exemplify our design methodology by proposing several optimizing schemes to improve the reliability. Benchmarking is carried out to demonstrate the effectiveness of our vulnerability model and optimization approach, which can provide an insightful guidance for the future reliable instruction cache and ISA design.

Matrix computing based on software, particularly floating point matrix computing, is slow and often becomes a problem in overall embedded systems. A matrix computing coprocessor (MCC) is developed in this study to improve the performance of matrix computing. The proposed MCC, which is an application-specific instruction set processor for the construction of a high-performance embedded system, can independently implement the entire algorithm, including floating point matrix computing. A good definition matrix operation instruction set is also presented. A single floating-point MCC and an embedded system with the MCC are implemented. Experimental results show that the proposed MCC exhibits high performance and has excellent flexibility and good application prospect.

Display Omitted Provide a VHDL simulation model of a hybrid quantum/classical processor.Provide a processor capable of executing classical and quantum programs.Provide an assembler to interpret both classical and quantum assembly instructions.Provide C++ libraries to develop quantum algorithms within classical programs.Test the whole framework to show it can implement quantum algorithms correctly. The objective of this paper is to model a hybrid quantum processor capable of executing both classical and quantum instructions. The processor is modeled and simulated using VHDL. It consists of a MIPS R2000 processor with a quantum processing module embedded within it. Additionally, an assembler has been developed capable of interpreting assembly programs modeling quantum algorithms or circuits, containing instructions from both the standard MIPS instruction set as well as the Quantum Assembly (QASM) instruction set. Furthermore, a quantum C++ library has been developed, with methods and classes to encapsulate the QASM instructions so that a programmer may use it to develop a C++ program implementing a quantum algorithm containing both classical and quantum parts.

With the increasing importance of Application Domain Specific Processor (ADSP) design, a significant challenge is to identify special-purpose operations for implementation as a customized instruction. While many methodologies have been proposed for this purpose, they all work for a single algorithm chosen from the target application domain. Such algorithm-specific approaches are not suitable for designing instruction sets applicable to a whole family of related algorithms. For an entire range of related algorithms, this paper develops a methodology for identifying compound operations, as a basis for designing “domain-specific” Instruction Set Architectures (ISAs) that can efficiently run most of the algorithms in a given domain. Our methodology combines three different static analysis techniques to identify instruction sequences common to several related algorithms: identification of (non-branching) instruction sequences that occur commonly across the algorithms; identification of instruction sequences nested within iterative constructs that are thus executed frequently; and identification of commonly-occurring instruction sequences that span basic blocks. Choosing different combinations of these results enables us to design domain-specific special operations with different desired characteristics, such as performance or suitability as a library function. To demonstrate our approach, case studies are carried out for a family of thirteen string matching algorithms. Finally, the validity of our static analysis results is confirmed through independent dynamic analysis experiments and performance improvement measurements.

Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-) configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the researchers and practitioners, a very important problem of hardware reuse in ASIP and accelerator synthesis is clearly underestimated and does not get enough attention in the published research. This paper is an effect of an industry and academic collaborative research. It analyses the problem of hardware sharing, shows its high practical relevance, as well as a big influence of hardware sharing on the major circuit and system parameters, and its importance for the multi-objective optimization and tradeoff exploitation. It also demonstrates that the state-of-the-art synthesis tools do not sufficiently address this problem and gives several guidelines related to enhancement of the hardware reuse.

This contribution documents the development, implementation, and verification of a RISC microprocessor using the functional hardware description language Lava. Basic methods to describe hardware in Lava are introduced and extended towards implementation of instruction set architecture and pipeline structure and control. FPGA synthesis results are presented and compared against a traditional VHDL-based design flow. An implementation of a coprocessor interface used to accelerate application-specific code is discussed supported by the case study of fast Fourier transform. To authors' best knowledge it is the first attempt to describe, simulate, verify, synthesize and test-run a complete von Neumann machine in Lava. Project experiences are summarized followed by a sketch of possible directions for further improvement of Lava in particular and functional hardware description languages in general.

In this article, we present the Beefarm infrastructure for FPGA-based multiprocessor emulation, a popular research topic of the last few years both in FPGA and computer architecture communities. We explain how we modify and extend a MIPS-based open-source soft core, we discuss various design tradeoffs to make efficient use of the bounded resources available on chip and we demonstrate superior scalability compared to traditional software instruction set simulators through experimental results running Software Transactional Memory (STM) benchmarks. Based on our experience, we comment on the pros and cons and the future trends of using hardware-based emulation for multicore research.

The increasing complexity of applications with a decreasing time-to-market requirement has created a strong interest in both high-performance and flexible embedded processors with a strong consideration for battery life. Low-power optimizations are therefore often applied toward the development of Application-Specific Instruction-Set Processors (ASIPs). In this paper ASIP accelerators for a typical DSP task are developed and synthesis results from six different cell-based and FPGA architectures are shown. By carefully analyzing algorithms and implementing appropriate accelerators with logic, it is shown that an increase in design performance is achieved while still reducing energy consumption due to the reduced latency of the task. In addition, we show cases when classic synthesis options can outperform new power optimization features in Xilinx ISE 11.1.

Software defined radios provide programmable solutions for implementing the physical layer processing of multiple communication standards. Mobile devices implementing these standards require high-performance processors to perform high-bandwidth physical layer processing in real time. In this paper, we present instruction set extensions for several important communication algorithms including cyclic redundancy checking, convolutional encoding, Viterbi decoding, turbo decoding, and Reed-Solomon encoding and decoding. We also present hardware designs for implementing these extensions, along with estimates of their area, critical path delay, and power consumption. The performance benefits of these extensions are evaluated using a supercomputer-class vectorizing compiler and the Sandblaster low-power multithreaded processor for software defined radio. The proposed instruction set extensions provide significant performance improvements at relatively low cost, while maintaining a high degree of programmability.

This paper introduces the mapping of MPEG video decoders on ADRES, IMEC's new coarse-grain reconfigurable and fully C-programmable array processor that targets nomadic devices. ADRES is a flexible template that allows the instantiation of many different processor versions. An XML-based architecture description language allows a designer to easily generate different processor instances with full compiler support by specifying different values for the communication topology, the number and size of local register files and functional units and supported instruction set. ADRES supports a VLIW-like programming model with a pure VLIW mode for legacy code, and a (coarse-grain reconfigurable) array mode with very high parallelism for the processing of compute intensive loops. We demonstrate the mapping of two video decoders MPEG-2 and AVC, and discuss the performance trade-offs for two critical kernels: IDCT and integer transform. As a result, an ADRES based system can perform AVC decoding in CIF resolution with less then 50MHz on a 4x4 array processor.

In this paper, a new programmable RISC processor architecture named VGP-I is proposed, aiming to the acceleration of genetic algorithms in embedded systems. Compared to other GA engines, the VGP-I specification defines a compact instruction set supporting multiple operator types, with scalable instruction encodings, programmer-visible and auxiliary registers and optional extensions. Apart from the programmable accelerator approach, VGP-I instructions have been tightly integrated to the Nios II soft-core processor as well. For performance assessment, a cycle-accurate reference VGP-I model has been developed while VGP-I subsets have been realized on a prototype microarchitecture and as Nios II custom instructions, both verified on programmable logic. Performance improvements on the execution of genetic operators are typically at the level of two orders of magnitude with application kernels written in ANSI C being accelerated by about 20x due to the usage of GA instruction set extensions.

Custom instruction generation is fast becoming popular as it provides an alternative means to realize application specific processors. In this paper, we propose an efficient methodology for rapid instruction set customization on RISPs (Reconfigurable Instruction Set Processors) using predefined sets of dataflow structures that are based on templates and reusable structures. A novel template selection strategy was employed to reduce the number of templates required for matching by up to 50%, while providing comparable performance with known approaches. It has been shown that custom instructions could be realized through instantiation of a reduced set of pre-designed reusable structures. Experimental results show that a small number of reusable structures can sufficiently cater to custom instruction generation to notably reduce the time required to realize them on configurable hardware. Moreover, based on our evaluations using MiBench benchmark suites, the reusable structures constitute to only 2% of all the custom instruction instances. The custom instructions generated with reusable structures were implemented in FPGA and it is evident that up to 14% area savings with comparable performance can be achieved when compared with conventional implementation approaches.

Application-specific instruction set extensions on reconfigurable hardware open up new opportunities for the embedded system designer. Although the flexibility offered by unrestricted instruction set extensions seems strongly attractive in first place, insufficient retargetable compiler support may hamper the benefits. It is therefore useful to reduce the design space of these instruction extensions to widely accepted tools supported instruction formats in order to capitalize on the existing resources. SIMD extensions have been proposed and implemented in the general-purpose processor domain but never brought to the embedded world due to the complexity, area, and energy consumption of SIMD model of computation. In this paper, we propose an application-specific AltiVec compatible customized SIMD synthesis flow well adapted to FPGA platforms which solve both compatibility and customization issues.

The abstract vector processing unit (VPU) is a virtual VPU that represents a set of real VPUs. It has an idealised instruction set and constraints common to the VPUs that it represents. Together, the idealised instruction set and common constraints allow programs to be portable and to perform efficiently on the real VPUs being represented. The abstract VPU is suitable for programmers who want the performance advantages of using the VPU directly, without being restricted to a particular VPU. An abstract VPU implementation, Vector Virtual Machine (VVM), is presented in this paper. VVM is designed to represent desktop VPUs, such as AltiVec, and to support the creation of a generic, vectorised, machine-vision library. Constraints common to desktop VPUs that VVM are short vectors, fixed vector sizes, and fast access to aligned memory addresses only. To support the creation of a generic, vectorised, machine-vision library, VVM has traits, templated vectors, constant scalar count vectors, and uses consistent functions for scalars and vectors where possible. Because VVM has constant scalar count, each VVM vector can consist of more than one scalar or VPU vector. Since the cost of type conversions is large for VPU programs, VVM only supports explicit type conversions. Ideally, an abstract VPU should have no overheads; that is be zero-cost. Function overloading and expression templates were tested to investigate the possibility of creating a zero-cost implementation of VVM using only Standard C++ and Apple's GCC 3.1 20021003 compiler. Results show that in this environment, zero-cost can be achieved only when processing VVM vectors that contain a single scalar or VPU vector. For expressions involving one to five additions, function overloading was at worst 3.6% slower than hand-coded programs when processing VVM vectors with one scalar or VPU vector. Unfortunately, for VVM vectors with four VPU vectors, function overloading was at worst 23.0% slower. For the same kind of expressions, the expression templates implementation was up to 888.3% slower. It was comparable to hand-coded programs only for expressions involving only one addition between VVM vectors that contain four VPU vectors. When a VPU is available, only char VVM vectors will consist of one VPU vector. In scalar mode, all VVM vectors will consist of one scalar. Thus, with Apple GCC 3.1 20031003, a VVM implementation based on function overloading has minimal overheads only for applications where most operations involve char types. This implementation's performance is adequate for creating a generic, vectorised, machine-vision library because most image processing operations operate on char types.

Application-specific instruction set processor (ASIP) design is a promising approach for meeting the performance and cost goals of embedded systems. We have developed a new microarchitecture, called a wide counterflow pipeline (WCFP), for automatically constructing ASIPs. Our ASIP synthesis technique uses software pipelining and design-space exploration to generate a custom WCFP and instruction set for an embedded application. This paper describes an innovative methodology and framework for WCFP synthesis and the lessons learned from designing and building the infrastructure. These lessons can be applied to other automated design tools for application-specific processors. The framework includes a user-supplied design database, intermediate representations for pipeline organization and custom instruction set architecture, and a reconfigurable simulator and performance analysis tool. The paper describes how the requirements and needs of automatic architectural design for WCFPs influenced the synthesis methodology and framework. To demonstrate the framework, we show its usefulness in refining the organization of custom WCFPs to better match the execution behavior of an application.

Microprocessor architectures are diversifying to support niche market requirements, with growing emphasis for performance delivery on the architectural design rather than the silicon implementation. This paper outlines the architectural design, programmer's model and instruction set of a microprocessor, which adopts a novel approach to network data. In particular, Asynchronous Transfer Mode (ATM) cells are delivered to a special FIFO cache memory, located at the heart of the processor. Cell input and output is conducted at wire speed using dedicated streaming input and output hardware. Special read and write instructions then allow the cell payloads to be accessed directly, and transferred from/to the register file. Multimedia applications have previously been identified as an important market for such a network centric architecture. Therefore the paper ends with a demonstration of the power of some key instructions. A motion estimation kernel from the MPEG standard is used to exercise the architecture and instruction set. Execution speed is shown to be comparable to today's processors, using only a 400 MHz clock for a full search. The minimally resourced design is therefore suited to embedded network applications from both economic and performance standpoints.

This article describes the construction of a Forth cross-compiler whose main characteristic is the resources use optimisation, based on the knowledge of the user's application. This optimisation consists in the elimination of portions of the language not required for the functioning of the developed application. The number of Forth words available for elimination by the post-optimiser was notoriously increased due to the change introduced in the execution model as a consequence of the migration from an interpreter-compiler to a cross-compiler.

Java was designed for network programming. This imposes certain requirements on its virtual machine instruction set architecture and on designs that intend to support Java. The purpose of this study is to carry out a behavioral analysis of the different aspects of Java instruction set architecture. Performance metrics were collected through benchmarking a bytecode interpreter. In this second part of our two-part paper, we study the instruction set utilization, instruction execution time, method invocation behavior, and the effect of object-orientation.

Java was designed for network programming. This imposes certain requirements on its virtual machine instruction set architecture and on designs that support Java. The purpose of this study is to carry out a behavioral analysis of the different aspects of Java instruction set architecture. This will help in establishing the hardware requirements for executing Java bytecodes. First, the bytecode interpreter was instrumented to include performance counters and statistics collectors. Then performance metrics were collected through benchmarking. Analyzing these data helps to identify performance-critical aspects that are candidates for hardware support, while less critical aspects can be left for software implementations. In this first part of our two-part paper, we study access patterns for data types, addressing modes, and instruction encoding. Recommendations for architectural requirements for Java processors will be made throughout this study.

This paper presents an environment for developing customized hardware–software solutions for intelligent embedded applications. They are based on the use of custom-configurable machines generated around a flexible instruction execution unit, called Flexible Instruction Execution Unit, or FLIX. The FLIX customization environment contains the FLIX processor core, which can be customized with a small effort to solve the software part of the solution, the standard interface, and the application specific functional units that represent hardware part of the solution. The FLIX environment allows easy modification of the FLIX instruction set, with the necessary changes of its control unit, as well as the software development support in a form of self-generating assembler. Field-Programmable Logic Devices (FPLDs) are used as the implementation technology.

Undergraduate programs in computer science are taught in many universities throughout the world. Most of these courses include a unit on computer architecture. Since computer architecture is concerned with instruction set construction and interpretation, the teacher has to decide whether to base the course on one or more real architectures or whether to use a hypothetical architecture. Although some choose a hypothetical processor, many prefer to use a real, commercially available device as a vehicle for introducing the basic principles of this subject. This article discusses some of the issues involved in selecting a suitable processor for use in teaching and describes two specific microprocessors. One, the 68K family, is a mainstream CISC device and one, the ARM family, a modern RISC processor. Both these processors have particular advantages when they are used to teach computer architecture.

The following article is a tutorial on CPU design aspects like instruction set design, etc. It covers in detail the design process which led to the NICE-processor (NICE is charmingly elegant), developed in 1997 (B. Ulmann, Computer Architecture News, October 1997). This architecture is very well suited for educational purposes in computer architecture since it employs a simple but very powerful orthogonal instruction set in conjunction with a true general purpose register set and versatile addressing modes. These features simplify the programming of NICE as well as its possible implementation in hardware.

In this paper, a filter-debugger and a memory-trace generator software tool (DGT) are considered. DGT analyses executable files under the DOS operating system for the instruction set architecture based on the Intel 80×86 microprocessor family. The methodology used for creating this tool is given. Also, a practical result for illustrating some characteristics of the developed tool is presented.

Commercial workloads, such as transaction processing, stress the memory hierarchies of current computers. TPC-B is a transaction processing benchmark that generates significant operating system and database activity, and a TPC-B instruction trace is analyzed for the Motorola 88110 microprocessor. Instruction set usage reveals one branch in every four to five instructions, and instruction cache performance indicates that this branching behavior causes a large number of words to be brought in by cache refills but never used. Code reorganization optimizations to reduce unused words and avoid cache misses are simulated and found to reduce misses in the on-chip instruction cache by almost one fifth.

This paper illustrates certain design techniques and tradeoffs for application-specific processors by considering the design of fully integrated speed and torque controllers for electric motors. We begin with the algorithmic requirements of two controller ASICs leading to a top-level partitioning of each system. Critical partitions are then allocated to dedicated processors with customised instruction sets and architectures. The implementation of the ALU and the control unit of each processor is described and we conclude by reviewing the performance and design costs of the resulting systems. Our approach is suitable for embedded control applications where software requirements are not very extensive (e.g. several Kbytes of code and data) and significant cost and performance advantages can be obtained from integrating all the functions and software in a single chip. The use of application-specific processors simplifies the design and gives a performance advantage of about two to three times over a standard microcontroller or digital signal processor.

A special purpose RISC (reduced instruction set computer) microprocessor for programmable logic controllers (PLC), named PLCRISC, is proposed. To develop an optimal PLCRISC, we analysed existing PLC programs currently used in factories, with special attention to the instruction execution characteristics and features required for a high performance PLC processor. Based on this analysis, an optimal RISC-style instruction set and an architecture suitable for the required features are suggested. In particular, the instruction format, the instruction pipeline, and the detailed internal architecture are the significant characteristics of the proposed PLCRISC. The performance enhancement achieved with a PLCRISC is seen from a straightforward evaluation. ASIC implementation with VHDL is also discussed. The PLCRISC is under fabrication in a 0.8 μm CMOS technology.

The goal of designing a special-purpose computer is to offer a highly efficient computer-aided environment for circuit simulation using hardware description languages. The suggestion is to have a machine that supports bitstring operations. A bitstring comprises a sequence of bits and must have at least one bit, and is found to be the predominant operation in hardware description languages, yet not a common operation in Pascal-like languages. A special-purpose machine is proposed and its hardware architecture reflects the characteristics of a hardware description language. The main part of this paper deals with the design concepts of the hardware machine, which is derived directly from the run-time requirements of hardware description programs. We start by examining examples of these programs and their operators, then identifying areas which can be improved through the use of hardware. Next, we present the architecture of the machine and bitstring operators that are supported. The instruction format is also presented and some comparisons are made to the reduced instruction set computers. Finally, we study the related works that have been conducted elsewhere.

This paper presents an investigation into the performance evaluation of advanced complex instruction set computer (CISC) processors, reduced instruction set computer (RISC) processors and digital signal processing (DSP) devices in the real-time implementation of signal processing and control algorithms. The algorithms considered are of varying degree of regularity relative to one another. These include a fast Fourier transform algorithm, a second-order correlation algorithm, two adaptive filtering algorithms, a simulation algorithm of a flexible manipulator system and simulation, identification and active vibration control algorithms of a flexible beam system. The algorithms are implemented on an 80486DX2 CISC processor, an 80386DX CISC processor, a SPARC TMS390S10 RISC processor, a T805 RISC processor, an 80i860 RISC processor and a TMS320C40 DSP device. The hardware and software resources and capabilities of the processors and the characteristics of the algorithms are discussed to provide a matching between the algorithms and the architectures. Finally, a comparison of the results of the implementations, on the basis of real-time computation performance, is made and discussed.

This paper presents MASCOT (MicroArchitecture Synthesis of ConTrol paths). This synthesis system constructs the optimal microarchitecture for a control path of an instruction set processor. Input to the system is the behavioural specification of a control path. This specification is in finite state machine form which is mapped initially onto a single programmed logic array (PLA) microarchitecture. The synthesis strategy then applies a sequence of decompositions on this initial microarchitecture. This strategy follows a decision scheme until all design objectives are met. It transforms the initial microarchitecture into a complex microarchitecture of several PLAs and ROMs. Where it is impossible to meet the design objectives, the system constructs a microarchitecture which comes as close as possible to given design objectives. Design objectives are allowed on floorplan dimensions and delay. Our strategy integrates a number of known optimization methods for specific microarchitectures. Therefore this synthesis method explores a larger part of the design space than do other control path synthesis methods. Other methods are mostly bound to one microarchitecture which they optimize. Our system is not only very flexible in microarchitecture construction but also open for extension by other optimizations.

The primary concern in the construction of a computational system is to produce a design which satisfies the requirements specification of the system. Induced faults on the hardware may lead to changes in expected program flow. A program which is executing when an unexpected event takes place which corrupts part of the software will have unexpected behaviour. Clearly, the exact location and extent of the corruption determines the subsequent program flow. This paper is concerned with the effects which occur when hardware malfunctions lead to the corruption of software. Intuitively, many faults will have severe effects. The purpose of this paper is to determine how severe these faults are. An analysis of the structure of the instruction set of the 1414 transputer is given. A database has been generated for examining the effects of faults induced by such malfunctions. This database can be used to determine the types of behaviour which must be captured by fault tolerance mechanisms. Some suggestions are made in an attempt to increase the reliability of commonly used programming structures.

Superscalar and VLIW processors can both execute multiple instructions each cycle. Each employs a different instruction scheduling method to achieve multiple instruction execution. Superscalar processors schedule instructions dynamically, and VLIW processors execute statically scheduled instructions. This paper quantitatively compares various superscalar processor architectures with a very long instruction word (VLIW) architecture developed at the University of California, Irvine. An architectural overview and performance analysis of the superscalar processor models and VIPER, a VLIW processor designed to take advantage of the parallelizing capabilities of percolation scheduling, are presented. The motivation for this comparison is to study the capability of a dynamically scheduled processor to obtain the same performance achieved by a statically scheduled processor, and examine the hardware resources required by each.

The design and verification of microcode for a processor with a complex instruction set can be a complicated task. In this paper it is shown how a standard relational database can be used at various stages to simplify such a design process, as automatic microcode generation is not always suitable for this process. Using the example of a coprocessor for list manipulation, it is demonstrated how the database can be used to enter the microprogram, check various aspects of consistency, generate simulation patterns for the datapath and finally to generate the optimized microcode.

This is an applications tutorial oriented towards the practical use of the discrete Fourier transform (DFT) implemented via the fast Fourier transform (FFT) algorithm. The DFT plays an important role in many areas of digital signal processing, including linear filtering, convolution and spectral analysis. The first part of the article is a practical industrial example and takes the reader through the thought process an engineer might take as DFT familiarity is gained. If standard software packages did not provide the necessary performance, the engineer would need to port the application to specialized hardware. The second part of the tutorial discusses the theoretical concepts behind the FFT algorithm and a processor architecture suitable for high speed FFT handling. Rather than examining the standard digital signal processors (DSP) in this situation, the final section looks at how the reduced instruction set (RISC) processors perform. The Advanced Micro Devices scalar Am29050 and the super-scalar Intel i860 processors are detailed, Comparison of the DSP and RISC processors is given showing that the more generalized RISC chips do well, although changes in certain aspects of the RISC architecture would provide for considerable improvements in performance.

Decoupled computer architectures provide high scalar performance by exploiting the fine-grained parallelism existing between the access and execute functions in a computer program. These architectures employ an access processor to fetch execute processor data ahead of demand. Some of the decoupled architectures employ identical access and execute processors, but special processors that efficiently access data structures have also been proposed. In this paper, we present the design of an access processor targeted for VLSI implementation. The processor hardware elements, instruction set and instruction formats are presented in sufficient detail to define the system architecture. The various trade-offs involved in the design are explained. Finally, a detailed implementation of a scaled down version of the processor is presented.

The authors have developed an architecture simulation toolkit from which a RISC simulator has been built by employing object-oriented software development techniques. Object-oriented design makes it easy to extend the simulated RISC architecture. Equally, more or even different functionality can be incorporated by uniformly extending the framework of the simulator. The basic framework is explained by simulating a subset of the Acorn ARM RISC's instruction set. This instruction set is then extended to provide further functionality by the addition of a multiply with accumulate instruction. The reader is expected to be reasonably conversant with the C++ programming language and with the basic concepts of object-oriented programming.

This application note from Motorola provides a tutorial on the use of the stack in an embedded microcomputer. A thorough understanding of the stack and its role in the creation and manipulation of local variables is essential to the real-time programmer. The topics covered by this application note are: the operation of the M68HC11's stack and the instructions that manipulate it; the use of local and global variables; subroutine parameter passing and the stack; the use of the MC68HC11's instruction set to support local variables and parameter passing.

Two collaborative projects, the European ESPRIT BRA ProCoS project and the UK IED safemos project, are currently investigating methods to prove software and hardware systems correct at a number of different levels of abstraction. Both projects intend to concentrate on subsets of Occam, and the transputer instruction set. The projects will aim to use the same machine language so that results obtained on both projects will be compatible. The initial selection of the projects (a simple subset of the transputer) is presented using the specification language Z. The role of the specification in the two projects is explained and the benefits and drawbacks of such a specification are discussed.

The Motorola MC88000 RISC architecture has been designed to take advantage of the three fundamental techniques of improving processor performance: increasing clock speeds, improving the instruction sets and executing multiple instructions per clock cycle. The basic techniques are described with the associated problems encountered in their implementation, and the paper shows how the architecture overcomes them.

The 801 minicomputer 1 project at IBM Research in Yorktown Heights, NY, USA, in 1975 pioneered many of architectural concepts used in RISC including IBM's RT System. The paper describes a second-generation RISC architecture, the POWER architecture, which is based on subsequent research by the original 801 team and is used in the recently announced RISC System/6000. The architecture was designed to support superscalar implementations which can execute multiple instructions every cycle. It provides compound-function instructions which allow application path lengths to be less than would be required on many complex instruction set computers. The architecture also exploits advances in optimizing compiler and operating system technology. An extension to the original 801 virtual memory architecture for hardware support of database storage is also described.

The paper describes the design and analysis of an instruction set which is applicable to a RISC processor operating as a geometry engine for computer image generation. A prototype LSI implementation of a fixedpoint pipelined RISC is described. It provides a novel technique with DMA channels direct to the register file, a high-performance multiplier and a high-performance divider. The extension of this approach to a VLSI ASIC version using macrocells from a standard cell library is outlined together with a discussion of the testability issues. Results from an LSI implementation and an ASIC simulation are presented.

Microprocessor manufacturers usually produce a programming card for each of their microprocessors. This card gives details of opcodes, mnemonics, addressing modes, registers etc. However, there is no standard way of laying out this information and each manufacturer has its own ad hoc approach. The paper presents a series of programming cards which were developed for a wide selection of microprocessors but which are set out in a standard format. This enables users to swap between processors and programming cards with greater ease once the format has been assimilated.