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A coupling mechanism between flicker noise and hot carrier degradation (HCD) is revealed in this work. Predicting the flicker noise properties of fresh and aged devices is becoming essential for circuit designs, requiring an understanding of the fundamental noise behaviors. While certain models for fresh devices have been proposed, those for aged devices have not been reported yet because of the lack of a clear mechanism. The flicker noise of aged FinFETs is characterized based on the measure-stress-measure (MSM) method and analyzed from the device physics. It is found that both the mean and deviations of the noise power spectral density increase compared with the fresh counterparts. A coupling mechanism is proposed to explain the trap time constants, leading to the trap characterizations in their energy profiles. The amplitude and number of contributing traps are also changing and are dependent on the mode of HCD and determined by the position of the induced traps. A microscopic picture is developed from the perspective of trap coupling, reproducing well the measured noise of advanced nanoscale FinFETs. The finding is important for accurate flicker noise calculations and aging-aware circuit designs.

In this article, an experimental study on the gate-induced drain leakage (GIDL) current repairing worst hot carrier degradation (HCD) in Si p-FinFETs is investigated with the aid of an ultra-fast measurement (UFM) technique (~30 μs). It is found that increasing GIDL bias from 3 V to 4 V achieves a 114.7% VT recovery ratio from HCD. This over-repair phenomenon of HCD by UFM GIDL is deeply discussed through oxide trap behaviors. When the applied gate-to-drain GIDL bias reaches 4 V, a significant electron trapping and interface trap generation of the fresh device with GIDL repair is observed, which greatly contributes to the approximate 114.7% over-repair VT ratio of the device under worst HCD stress (−2.0 V, 200 s). Based on the TCAD simulation results, the increase in the vertical electric field on the surface of the channel oxide layer is the direct cause of an extraordinary electron trapping effect accompanied by the over-repair phenomenon. Under a high positive electric field, a part of channel electrons is captured by oxide traps in the gate dielectric, leading to further VT recovery. Through the discharge-based multi-pulse (DMP) technique, the energy distribution of oxide traps after GIDL recovery is obtained. It is found that over-repair results in a 34% increment in oxide traps around the conduction energy band (Ec) of silicon, which corresponds to a higher stabilized VT shift under multi-cycle HCD-GIDL tests. The results provide a trap-based understanding of the transistor repairing technique, which could provide guidance for the reliable long-term operation of ICs.