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In this study, we perform reconfigurable n- and p-channel operations of a tri-top-gate field-effect transistor (FET) made of a p+-i-n+ silicon nanowire (SiNW). In the reconfigurable FET (RFET), two polarity gates and one control gate induce virtual electrostatic doping in the SiNW channel. The polarity gates are electrically connected to each other and program the channel type, while the control gate modulates the flow of charge carriers in the SiNW channel. The SiNW RFET features simple device design, symmetrical electrical characteristics in the n- and p-channel operation modes using p+-i-n+ diode characteristics, and both operation modes exhibit high ON/OFF ratios (∼106) and high ON currents (∼1 μA μm−1). The proposed device is demonstrated experimentally using a fully CMOS-compatible top-down processes.

In this paper, we propose inverting logic-in-memory (LIM) cells comprising silicon nanowire feedback field-effect transistors with steep switching and holding characteristics. The timing diagrams of the proposed inverting LIM cells under dynamic and static conditions are investigated via mixed-mode technology computer-aided design simulation to verify the performance. The inverting LIM cells have an operating speed of the order of nanoseconds, an ultra-high voltage gain, and a longer retention time than that of conventional dynamic random access memory. The disturbance characteristics of half-selected cells within an inverting LIM array confirm the appropriate functioning of the random access memory array.

In this paper, we describe the feedback and tunneling operations of a dual top gate field-effect transistor (FET) with a p

In this study, we demonstrate the substantial enhancement of the thermoelectric power factors of silicon nanowires (SiNWs) on plastic substrates achievable by field-effect modulation. The Seebeck coefficient and electrical conductivity are adjusted by varying the charge carrier concentration via electrical modulation with a gate voltage in the 0 to ±5 range, thus enhancing the power factors from 2.08 to 935 μW K−2 m−1) for n-type SiNWs, and from 453 to 944 μW K−2 m−1) for p-type SiNWs. The electrically modulated thermoelectric characteristics of SiNWs are analyzed and discussed.

In this paper, we describe the feedback and tunneling operations of a dual top gate field-effect transistor (FET) with a p +-i-n + doped silicon nanowire channel. The transistor functions selectively in either a feedback FET (FBFET) or a tunneling FET mode by modulating the source-to-drain voltage, and it features an outstanding subthreshold swing characteristic of 6.15 mV dec-1 with an on/off current ratio (I on/I off) of approximately 106 in the feedback operating mode and of 41.3 mV dec-1 with I on/I off of ∼107 in the tunneling operating mode. Moreover, our device in the FBFET operation mode has memory characteristics with a retention time of 104 s and a program/erase endurance up to 103 cycles owing to the positive feedback loop in the channel region. This study demonstrates the promising potential of our devices in the development of multifunctional electronics.

In this study, we propose newly designed feedback field-effect transistors that utilize the positive feedback of charge carriers in single-gated silicon channels to achieve steep switching behaviors. The band diagram, I–V characteristics, subthreshold swing, and on/off current ratio are analyzed using a commercial device simulator. Our proposed feedback field-effect transistors exhibit subthreshold swings of less than 0.1 mV dec−1, an on/off current ratio of approximately 1011, and an on-current of approximately 10−4 A at room temperature, demonstrating that the switching characteristics are superior to those of other silicon-based devices. In addition, the device parameters that affect the device performance, hysteresis characteristics, and temperature-dependent device characteristics are discussed in detail.

We report on the thermoelectric characteristics of p-type silicon nanowires (NWs) on plastics in the relatively low temperature regime below 47 °C, and for temperature differences of less than 10 K in ambient air. Thermal profile images are utilized to directly determine the temperature difference in the NWs generated by Joule heating in air. The Seebeck coefficient of the NWs increases from 294 to 414 μV K(-1) as the NW length varies from 40 to 280 μm. For a temperature difference of 7 K, the maximal Seebeck voltage can be estimated to be 2.7 mV for NWs with a length of 280 μm. In contrast, the output power is maximized for NWs length of 240 μm. The maximized output power obtained experimentally in this study is 2.1 pW at a temperature difference of 6 K. The thermoelectric characteristics are analyzed and discussed.

We construct a flexible pn heterostructured photodiode using a CdTe nanoparticle thin film and a single ZnO nanowire (NW) on a plastic substrate. The photocurrent characteristics of the flexible photodiode are examined under illumination with 325 nm wavelength light and the photocurrent efficiencies at bias voltages of ± 2.5 V are estimated to be 8.0 and 2.1 µA W(-1) under forward and reverse bias conditions, respectively. The photocurrent generation of the pn heterostructured photodiode is dominantly associated with the transport of the photogenerated charge carriers in the single ZnO NW. Furthermore, the operations of our flexible photodiode are investigated in the upwardly and downwardly bent states, as well as in the flat state.

The memory characteristics of ZnO nanowire-based nano-floating gate memory (NFGM) with Pt nanocrystals acting as the floating gate nodes were investigated in this work. Pt nanocrystals were embedded between Al(2)O(3) tunneling and control oxide layers deposited on ZnO nanowire channels. For a representative ZnO nanowire-based NFGM with embedded Pt nanocrystals, a threshold voltage shift of 3.8 V was observed in its drain current versus gate voltage (I(DS)-V(GS)) measurements for a double sweep of the gate voltage, revealing that the deep effective potential wells built into the nanocrystals provide our NFGM with a large charge storage capacity. Details of the charge storage effect observed in this memory device are discussed in this paper.

Electrical characteristics of NOT and NAND logic circuits fabricated using top-gate ZnO nanowire field-effect transistors (FETs) with high-k Al(2)O(3) gate layers were investigated in this study. To form a NOT logic circuit, two identical FETs whose I(on)/I(off) ratios were as high as ∼10(8) were connected in series in a single ZnO nanowire channel, sharing a common source electrode. Its voltage transfer characteristics exhibited an inverting operation and its logic swing was 98%. In addition, the characteristics of a NAND logic circuit composed of three top-gate FETs connected in series in a single nanowire channel are discussed in this paper.

Transparent and flexible thin film transistors (TFTs) with channel layers composed of sintered HgTe nanocrystals were fabricated on top of UV/ozone treated plastic substrates and their electrical properties were characterized. A representative TFT with a channel layer composed of sintered HgTe nanocrystals revealed typical p-type characteristics, an on/off current ratio of ∼10(3) and a field-effect mobility of 4.1 cm(2) V(-1) s(-1). When the substrate was bent until the bending radius of the substrate reached 2.4 cm, which corresponded to a strain of 0.83% that the HgTe thin film experienced, the TFT exhibited an on/off current ratio of ∼10(3) and a field-effect mobility of 4.0 cm(2) V(-1) s(-1).

We construct fully transparent nano-floating gate memory devices on a glass substrate. These memory thin-film transistors consist of channel layers of ZnO films, electrodes of Al/ITO, and floating gate nodes of Al nanoparticles, exhibiting a transmittance of approximately 71% in the visible region. Their electron mobility, on/off ratio, and threshold voltage shift are estimated to be 0.92 cm(2) V( - 1) s( - 1), about 10(4), and 3.1 V, respectively. Moreover, their programming/erasing, endurance and retention are characterized in this study. Our study suggests that our memory devices have great potential for realizing transparent systems-on-glass.

Complementary NAND and NOR gates composed of p-channel HgTe-nanocrystal (NC) films and n-channel HgSe-NC films were constructed on back-gate patterned plastic substrates. The NAND gate was made of two HgTe-p-channel thin film transistors (TFTs) in parallel and two HgSe-n-channel TFTs in series. The NOR gate was built up with both two HgSe-n-channel TFTs in parallel and two HgTe-p-channel TFTs in series. The mobility and on/off ratio for the p-channel TFTs were estimated to be 0.9 cm(2) V(-1) s(-1) and 10, respectively, and those for the n-channel TFTs were measured to be 1.8 cm(2) V(-1) s(-1) and 10(2), respectively. The NAND and NOR gates were operated with gains of 1.45 and 1.63 and transition widths of 7.8 and 6.2 V, respectively, at room temperature in air. In addition, the operations of the NAND and NOR logics are reproducible for up to 1000 strain cycles.

The transfer of charge carriers, photogenerated in nanoparticles (NPs), into a single nanowire (NW) is demonstrated in this study by conducting a careful comparison of the optoelectronic characteristics of a ZnO NW with ZnO NPs attached to its surface, a bare ZnO NW and a film of close-packed ZnO NPs. Under the illumination of an above-gap light, the photocurrent taken from the NW with the NPs is remarkably higher in magnitude than that obtained from the bare NW, although the photocurrent is substantially lower for the close-packed NPs. The presence of the absorption band of the NPs in the photoresponse spectrum taken from the NW with the NPs reveals that the transfer of the charge carriers photogenerated in the NPs into the NW dramatically enhances the magnitude of the photocurrent flowing in this NW. Nevertheless, during the transfer, the charge carriers experience trapping and detrapping at the interfaces of the NPs and the NW.

High performance NOT, NAND and NOR logic gates composed of GaAs-nanowire (NW)-based metal‐semiconductor field-effect transistors (MESFETs) were constructed on flexible plastics through a noble top-down route. The representative GaAs-NW-based MESFETs exhibited superior electrical characteristics such as a high mobility (∼3300 cm 2 V −1 s −1 ), large Ion/Ioff ratio (∼10 8 ) and small subthreshold swing (∼70 mV/dec). The NOT, NAND and NOR logic gates showed a maximum voltage gain of 108 and logic swings of 97‐99%. All of the logic gates successfully retained their electrical characteristics during 2000 bending cycles. Furthermore, the logic gates were well operated by square-wave signals of up to 100 MHz under various strain conditions. The high performances demonstrated in this study open the way to the realization of high speed flexible logic devices. (Some figures may appear in colour only in the online journal)

Flexible electronic devices which are lightweight, thin and bendable have attracted increasing attention in recent years. In particular, solution processes have been spotlighted in the field of flexible electronics, since they provide the opportunity to fabricate flexible electronics using low-temperature processes at low-cost with high throughput. However, there are few reports which describe the characteristics of electronic devices on flexible substrates. In this study, we fabricated flexible thin-film transistors (TFTs) on plastic substrates with channel layers formed by the spin-coating of ZnO nanoparticles and investigated their electrical properties in the flat and bent states. To the best of our knowledge, this study is the first attempt to fabricate fully functional ZnO TFTs on flexible substrates through the solution process. The ZnO TFTs showed n-channel device characteristics and operated in enhancement mode. In the flat state, a representative ZnO TFT presented a very low field-effect mobility of 1.2 x 10(-5) cm(2) V(-1) s(-1), while its on/off ratio was as high as 1.5 x 10(3). When the TFT was in the bent state, some of the device parameters changed. The changes of the device parameters and the possible reasons for these changes will be described. The recovery characteristics of the TFTs after being subjected to cyclic bending will be discussed as well.

A technique to implement silicon nanowire (SiNW)-based tunneling field-effect transistors (TFETs) on flexible plastic substrates is developed for the first time. The p-i-n configured Si NWs are obtained from an Si wafer using a conventional top-down CMOS-compatible technology, and they are then transferred onto the plastic substrate. Based on gate-controlled band-to-band tunneling (BTBT) as their working principle, the SiNW-based TFETs show normal p-channel switching behavior with a threshold voltage of -1.86 V and a subthreshold swing of 827 mV/dec. In addition, ambipolar conduction is observed due to the presence of the BTBT between the heavily doped p+ drain and n+ channel regions, indicating that our TFETs can operate in the n-channel mode as well. Furthermore, the BTBT generation rates for both the p-channel and n-channel operating modes are nearly independent of the bending state (strain = 0.8%) of the plastic substrate.