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We experimentally evaluated the effect of crosstalk between crossing microstrip lines (MSLs) on our MSL receiver. The measurement circuit consisted of two crossing MSLs, referred to as the upper MSL and lower MSL. At the crossing area, the upper MSL and lower MSL were separated by a 400-nm thickness of SiO2 thin film. The parasitic capacitance between them was estimated to be about 0.1 pF. We measured bias margin of the receiver connected to the lower MSL under two conditions: with a pulse train running through the upper MSL, i.e., with crosstalk noise, and without a pulse train in the upper MSL, i.e., without crosstalk noise. Our measurements showed that (i) crosstalk mainly reduced the lower limit of the receiver’s bias margin, and (ii) this reduction of bias margin was enhanced by resonance when the repetition frequency of pulses in the upper ring satisfied resonance condition. [Copyright &y& Elsevier]

To expand designable circuit scale, we have developed a new cell-based circuit design for single flux quantum (SFQ) circuit. We call it CONNECT cell library. The CONNECT cell library has over 100 cells at present. Each CONNECT cell consists of a Verilog digital behavior model, circuit information, and a physical layout. All circuit parameter values have been optimized for obtaining the widest margins and minimizing interactions between cells. At the layout level, we have defined a minimum standard cell size and made cell height and width a multiple of the size. Using this cell library, we can easily expand circuit scale without the time-consuming dynamic simulations of whole circuits. For estimation of the reliability of the library, we designed and fabricated test circuits using CONNECT cells. We demonstrated experimentally correct operations, which means the CONNECT cell library is sufficiently reliable. [Copyright &y& Elsevier]

Abstract: Fabricating high quality Josephson junction is essential in superconducting qubit circuits. In this letter, high quality tunnel junctions with a low critical current density of ∼32A/cm2 were fabricated. The 1/f noise parameter η was obtained from junctions’ low frequency voltage noise power spectral density . Our findings showed that the noise spectrum is junction linear dimension dependent, indicating the junction’s side leakage current induced by defects in the amorphous oxide insulator dominates the origin of the 1/f noise in our epitaxial NbN/AlN/NbN tunnel junctions. [Copyright &y& Elsevier]

Abstract: We have observed vortex penetration into Nb thin films with square arrays of square holes with variable sizes and lattice constants. We find that when the lattice spacing is large and the width of superconducting line is narrow, vortices penetrate diagonally rather than parallel to the nearest neighbor direction. This phenomenon is also confirmed in NbTiN samples with the same geometry. We also confirm that the direction of edge relative to that of hole array is not relevant. Possible origin of such a preferential penetration is proposed. [ABSTRACT FROM AUTHOR]

Abstract: We measured the delay times of several components of the rapid single-flux-quantum (RSFQ) circuit using ring oscillators so as to improve the precision in the timing design. The delay time deviates from the designed value because of wafer-to-wafer and on-wafer parameter spreads. In addition, three-dimensional structures of the actual circuits generate unpredictable parasitic inductances, which occasionally lead to the large timing deviation from the design. The 1-σ local spread of the delay time originating from the fabrication was found to be 5.2% for a Josephson transmission line (JTL) composed of two junctions. This result provides a quantitative indication of timing margins required between SFQ pluses. However, the delay times tended to be smaller than those in numerical simulation by approximately 20%. We think that this is because the timing parameters were extracted without any considerations of the parasitic inductance of shunt resistors in the simulation. To examine the influence of the parasitic inductance, we designed four JTLs having additional inductances in series with shunt resistors, and measured each delay time. The decreasing ratio of delay time to the parasitic inductance was found to be 0.32ps per 1 pH. We estimated that the parasitic inductance connected in series with a shunt resistor was 1.6 pH for the JTL. This timing consideration is applicable to all the cells because the junctions used in the actual circuits have roughly the same geometry as that of the JTL. [Copyright &y& Elsevier]

Abstract: We have designed, fabricated and tested a time-to-digital converter (TDC) using SFQ logic circuits. The proposed TDC consists of two sets of ring oscillators and binary counters, and a coincidence detector (CD), which detects the coincidence of the arrival of two SFQ pulses from two ring oscillators. The advantage of the proposed TDC is its simple circuit structure with wide measurement range in addition to the high resolution and the high sensitivity of the SFQ TDC compared to semiconductor TDCs. The time resolution of the proposed TDC is limited by the resolution of the CD. In order to improve the resolution, we have developed a dynamic AND (DAND) gate, which can detect two simultaneous SFQ signal inputs with high accuracy. It was demonstrated that the time resolution of the TDC using the DAND gate is improved to be ±4ps. [Copyright &y& Elsevier]

Abstract: We propose an integer multiplier with systolic array structure for single-flux-quantum (SFQ) technology. Since SFQ logic circuits work by pulse logic, suitable circuit structure for SFQ logic circuits is different from one for semiconductor logic circuits. The systolic array is a circuit structure for VLSIs and consists of regularly arranged simple processing elements. All signals of the proposed systolic multiplier flow from input to output unidirectionally. This feature matches concurrent-flow clocking well. For evaluating the proposed systolic multiplier, we have designed a 4-bit systolic multiplier, as well as a 4-bit array multiplier which is one of the most typical parallel multipliers, and have compared them with each other. From the results of the design and the digital simulation, the number of Josephson junctions (JJs) of the 4-bit systolic multiplier is almost the half of that of the 4-bit array multiplier, and the latency of the former is about 1.5 times longer than that of the latter. Our estimation of the performance of larger-scale multipliers shows that the proposed systolic multiplier achieves comparable latency to the array multiplier, using extremely smaller number of JJs when the bit-width of input becomes large. We have fabricated a 1-bit cell of the systolic multiplier using NEC standard Nb process and have successfully tested it at low speed. The proposed systolic integer multiplier is attractive for SFQ technology. [Copyright &y& Elsevier]

Abstract: We designed a single-flux-quantum (SFQ) scheduler for a 4×4 network switch. It receives requests serially and arbitrates them. Fair scheduling is achieved by using a round-robin priority pointer at each output port. The pointer is updated so that the input port that was granted permission has the lowest priority in the next scheduling cycle. We divided the scheduler into sub-blocks, which were separately designed. The sub-blocks, which have asynchronous interfaces, were then connected with passive transmission lines. Ladder-type on-chip clock generators were included in the circuit for high-speed operation. Using logic simulation, we verified the scheduler test circuit. The scheduler test circuit was composed of about 3000 Josephson junctions. We tested the scheduler circuit at high speed and confirmed correct operations at over 40GHz. [Copyright &y& Elsevier]

Abstract: We have demonstrated the components of datapath toward single-flux-quantum microprocessors based on our new architecture called the forwarding architecture. In the forwarding architecture, we improve the performance by utilizing multiple ALUs to conceal the inefficiency of bit-serial processing. The key components of the datapath are a register file and cascaded ALUs. We have designed the register file to hold four bit-serial data with two read ports and one write port. In each ALU, we have implemented six functionalities: addition, subtraction, logical AND, OR and Exclusive OR operations, and comparison with zero. We have tested the register file and the ALU using high-speed on-chip testing, and confirmed the correct operations up to 18GHz and 23GHz, respectively. [Copyright &y& Elsevier]

Abstract: We have designed, fabricated and tested a time-to-digital converter (TDC) using SFQ logic circuits. The proposed TDC consists of two sets of ring oscillators and binary counters, and a coincidence detector (CD), which detects the coincidence of the arrival of two SFQ pulses from two ring oscillators. The advantage of the proposed TDC is its simple circuit structure with wide measurement range. The time resolution of the proposed TDC is limited by the resolution of the CD, which is about 10ps because it is made by an NDRO cell in this study. The circuits are implemented using NEC 2.5kA/cm2 Nb standard process and the CONNECT cell library. We have demonstrated the measurement of the propagation delay of a Josephson transmission line by the TDC with the time resolution of about 10ps. [Copyright &y& Elsevier]

Abstract: We have calculated a bit-error-rate (BER) of Josephson latching drivers using the Monte-Carlo simulations taking into account the thermal noise at the Josephson junctions. The latching driver under investigation is composed of parallel 8-junction stacks and a SQUID input gate. We have optimized the structure of the SQUID input gate based on the BER simulation to get larger bias margins with acceptable BER. We have shown that the bias margins of the latching driver with a 3-junction SQUID input gate are better than that using a 2-junction SQUID input gate. The high-speed measurement of the Josephson latching driver confirms the validity of the BER based optimization. We have obtained the BER lower than 10−12 at 5GHz and 10−5 at 10GHz in the Josephson latching driver with the 3-junction SQUID input gate by the high-speed test. [Copyright &y& Elsevier]

Abstract: In this paper we have considered how to perform logic synthesis of the single-flux-quantum (SFQ) logic circuits by using logic synthesis tools for semiconductor logic circuits. Fundamental difference of the SFQ logic gates from the semiconductor logic gates in terms of logic synthesis is that typical SFQ gates are clocked gate, where gates have to be clocked by SFQ pulses. In our approach, we divided the procedure into two steps; logic synthesis and clock distribution. In the logic synthesis step, the logic function is optimized using a logic synthesis tool without considering the clock network. The Design Analyzer provided from Synopsys is used in this study. We have developed an SFQ cell library for the logic synthesis. In the clock distribution step, clock networks for every clocked SFQ gates are designed taking account of timing. We used a clock-followed-data clocking scheme in this study. We have classified every clocked gate into stages, where the clocked gates in the same stage are clocked simultaneously. To demonstrate the validity of our approach, we have designed a controller of an 8-bit SFQ microprocessor. [Copyright &y& Elsevier]

We have been developing an SFQ shift register memory, which is one candidate to realize high-throughput and high-density superconductive memories. We have modified our memory architecture in order to adapt it to our SFQ microprocessor, CORE1. The new version of the shift register memory is composed of shift registers with non-destructive readout operation, which have an internal feedback. We have also studied the availability of passive transmission line (PTL) wiring in the memory system at high speed. The tested circuit is a 4-byte shift register file, where four kinds of wiring circuits are used between a decoder and shift registers. We have measured the dependences of the DC bias margin on the operating frequency for all wiring methods, and obtained almost the same dependences, which shows the availability of the PTL wiring in the memory system. We have used the NEC 2.5 kA/cm2 Nb standard process and the CONNECT cell library. [Copyright &y& Elsevier]

We have designed and implemented an SFQ programmable clock generator (PCG), which can generate the variable number of SFQ pulses according to its internal state. The PCG is composed of an SFQ ring oscillator, a control circuit which counts up the number of SFQ pulses and stops the operation of the ring oscillator, and a decoder which defines the initial state of the control circuit. The PCG can generate the variable number of SFQ pulses ranging from 2 to 2N, where N is the number of T flip-flops in the control circuit. The oscillation frequency of the PCG is designed to be ranging from 6.2 to 18.8 GHz. In this study, we have implemented a PCG generating SFQ pulses ranging from 2 to 24 using a cell-based design methodology and confirmed its correct functionality. [Copyright &y& Elsevier]

Internet traffic is still growing rapidly. Link capacity is easily increased by bundling optical fibers, but the packet switching capacity at a node is limited by the performance of a semiconductor switch facing problems of packaging density, operation speed, and power consumption. Photonic technology is therefore emerging from the link technology into the packet switch technology. A photonic packet switch can analyze the packet label optically and control optical switches, but packet scheduling must be done in the non-optical domain because photonic technology lacks arithmetic characteristics. Increases in the line speed and the number of ports will make this scheduling a bottleneck. Because single flux quantum (SFQ) circuits can operate at several tens of gigahertz, a speed comparable to optical link speed, they will be able to eliminate this bottleneck. To improve the performance of the nodes in the photonic network, we propose an SFQ-circuit-controlled optical packet switch core. Here we describe and discuss two photonic packet switch architectures using SFQ-circuit-controlled photonic switches. [Copyright &y& Elsevier]

We have developed essential components for most of microarchitectures based on the single-flux-quantum (SFQ) logic. The circuit under test is composed of two registers, an ALU and a control unit, and made up of about 540 cells, 1600 Josephson junctions on 1.5 × 2.4 mm area. We have obtained the correct results by a sequence of several instructions, in which two integers are written into the registers with the LOAD and COPY operations, and then execute the ADD operation. Some of their functions were tested at both low and high frequencies. As a result, we found that the designed components could work at 15 GHz for the designed bias current and up to 18 GHz for higher bias currents. [Copyright &y& Elsevier]

The performance of high-end routers will soon reach the limits of conventional technology. Single flux quantum (SFQ) digital technology is a key technology for achieving a breakthrough. We have already proposed a high-end router using SFQ technology. In this paper, we report on the latest innovation of SFQ router technology. First we describe a design methodology development. We have developed a new SFQ logic cell library for cell-based top-down circuit design. To expand the circuit scale further, a novel pseudo-automatic Josephson transmission line (JTL) routing technique has also been developed. And then, we discuss issues of passive interconnection, and show the operation of a passive transmission line interconnected circuit up to 40-Gbps throughput. Second we describe a packet switch circuit demonstration. We designed a 2 × 2 crossbar packet switch circuit, which is a key element in the packet switch. We successfully tested the circuit up to a clock frequency of 35 GHz. Finally we discuss an SFQ circuit application in the optical router as an alternative application strategy. [Copyright &y& Elsevier]

Abstract: We have observed vortex motion in superconducting networks with relatively large holes. Vortices penetrate the network along the diagonal direction more easily than the parallel direction. This phenomenon is also confirmed in NbTiN networks as well as Nb networks. The mechanism for the diagonal vortex penetration is discussed on the basis of the enhancement of flux density near the vertices of square holes. [ABSTRACT FROM AUTHOR]