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In this paper we demonstrate the feasibility of Negative Tone Development (NTD) process to pattern 22nm node contact holes leveraging freeform source and model based assist features. We demonstrate this combined technology with detailed simulation and wafer results. Analysis also includes further improvement achievable using a freeform source compared to a conventional standard source while keeping the mask optimization approaches the same. Similar studies are performed using the Positive Tone Development (PTD) process to demonstrate the benefits of the NTD process.

In the very low k1regime in optical lithography, aggressive RET such as strong off-axis illumination causes significant forbidden pitches and lithography hotspots for aggressive designs. Various lithography retargeting techniques have been introduced to mitigate these process window failures. This paper proposes to bring the lithography target optimization into the Source-Mask Optimization (SMO) flow to achieve better SMO solutions at an earlier process development stage. Through this tight integration of lithography target optimization and source mask optimization, lithography target, source, and mask can be tuned together to provide the best overall process window for the newly defined targets. This improvement is demonstrated using a simple SMO test case for the 20-nm metal layer. Then at the later development stage, retargeting rules can be extracted from these optimized lithography targets, and they can be applied in the normal mask optimization process. This lithography target optimization flow can provide a faster tuning process for the lithography target rules at an early process development stage, and can provide optimized retarget rules for mask optimization process too. New challenges for retargeting in double patterning lithography are also discussed.

Double patterning technology (DPT) provides the extension to immersion lithography before EUV lithography or other alternative lithography technologies are ready for manufacturing. Besides the additional cost due to DPT processes over traditional single patterning process, DPT design restrictions are of concerns for potential additional design costs. This paper analyzes design restrictions introduced by DPT in the form of DPT restricted design rules, which are the interface between design and technology. Both double patterning approaches, Litho-Etch-Litho-Etch (LELE) and Self-Aligned Double Patterning with spacer lithography (SADP), are studied. DPT design rules are summarized based on drawn design layers instead of decomposed layers. It is shown that designs can be made DPT compliant designs if DPT design rules are enforced and DPT coloring check finds no odd cycles. This paper also analyzes DPT design rules in the design rule optimization flow with examples. It is essential to consider DPT design rules in the integrated optimization flow. Only joint optimization in design rules between design, decomposition and process constraints can achieve the best scaled designs for manufacturing. This paper also discusses DPT enablement in the design flow where DPT aware design tools are needed so that final designs can meet all DPT restricted design rules.

The 20nm generation for logic will be challenging for optical lithography, with a contacted gate pitch of ~82nm and a minimum metal pitch of ~64nm. A gridded design approach with lines and cuts has previously been shown to allow optimizing illuminator conditions for critical layers in logic designs.[1] The approach has shown good pattern fidelity and is expected to be scalable to the 7nm logic node. [2,3,4] A regular pattern for logic makes the optimization problem straightforward if only standard cells are used in a chip. However, modern SOC's include large amounts of SRAM memory as well. The proposed approach truly optimizes both, instead of the conventional approach of sacrificing the SRAM because of logic layouts with bends and multiple pitches. We consider a design with the logic and SRAMs unified from the beginning. In this case, critical layer orientations as well as pitches are matched and each of the layers optimized for both functional sets of patterns. The layout for a typical standard cell using Gridded Design rules is shown in Figure 1a. The Gate electrodes are oriented in the vertical direction, with Active regions running horizontally. Figure 1b shows a group of SRAM bit cells designed to be compatible with the logic cell. The Gate orientation and pitch are the same. Optimization results will be presented for the co-optimization of critical layers for the cells. The Source-Mask Optimization (SMO) method used can optimize the illumination source [5] and mask for multiple patterns to improve the 2-D image fidelity and process window while controlling the mask sensitivity. It can incorporate the design intentions that are implied by Gridded Design rules. SMO will be done to balance complexity of the source and the complexity of the mask (OPC & MBSRAFs). A flexible approach to the optimization will be introduced.

We present a comprehensive study of applicability of a fast 3D mask model in the context of source-mask optimization to advanced nodes. We compare the results of source optimization (SO) and source-mask optimization (SMO) with and without incorporating a fast 3D mask model to the rigorous 3D mask simulations and wafer data at 22 nm technology node. We do this comparison in terms of process metrics such as depth of focus (DOF), exposure latitude (EL), and mask error enhancement factor (MEEF). We try to answer the question of how much the illumination shape changes with the introduction of mask topography effect. We also investigate if the illumination change introduces any mask complexity and at which level. Correlation between MEEF and any mask complexity due to source variation is also explored. We validate our simulation predictions with experimental data.