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Line width roughness (LWR) is one of the most critical performance indexes for low k1 ArF immersion Lithography. Several factors are impacting LWR performance during Lithography process, such as structures, anti-reflective coating (ARC), photoresist, baking condition, illumination condition and track process. However, the structures and ARCs are strongly related to integration and Etch processes. The illumination conditions, including mask bias, are decided by simulation software but the track condition usually follows the pervious node at initial step normally. Therefore, it sometimes shows poor results because of the difference of the under-layer condition. For example, it has been uncovered that LWR and local CD uniformity (LCDU) became worse while structure changed to Carbon-DARC-Resist (CDR) from Multi-Layer Resist (MLR). Generally, photoresist evaluation with baking condition optimization is a typical way to improve LWR performance. The photoresist formulation contains photosensitive polymers, photoacid generators (PAGs), quenchers, additives, and solvents. Based on photoresist's point of view, the first two are the most important factors of LWR performance control. Several designs of experiments (DOEs) were planned with polymers, PAGs, and PEB conditions. The target is to achieve LWR of CDR under the result of MLR. In this paper, Polymer DOE1 and its statistical analyses have finished. Compared to de-composition efficiency of each unit, small protection unit and PEB effect are the most important factors, and bulky protection unit shows less influence for LWR improvement. Small protection unit is more important than bulky protection unit, and high Ea monomers of both are good for LWR. Based on previous experiences, we have chosen the acid diffusion length / amount of PAG and PEB temperature for PAG DOE2 plan. Higher PEB is the most effective to LWR. Shorter diffusion length PAG with fewer loading amounts is better for MEEF and EL by DOE2 result. The final DOE3 is combined by optimized polymers by DOE1 and optimized PAG by DOE2. The polymer is used DOE1 Tr2, DOE1 Tr4, and estimated new polymer by DOE1 result, and the PAG is chosen shorter diffusion PAG-O with the split of loading amount and PEB temperature. Based on the statistical analyses of DOE3 result, higher PEB temperature is still the most effective to LWR, and new polymer and DOE1 Tr2 polymer are better for LWR reduction. However, higher PEB temperature would suffer a little bit of DOF, EL, and MEEF. In order to achieve the lower LWR, it needs to use DOE1 Tr2 polymer with higher PEB, but insufficient DOE and MEEF would get at the same time. New polymer by DOE1 combined fewer PAG-O loading amount with lower PEB could get slower sensitivity for all Litho index's requirements. Through DOE works, we found out the volume of protection unit and PEB were key factors for good LWR. However, these factors are trades off DOF, EL, and MEEF against LWR, and they need to optimize for the best balanced Litho performances.

As the feature sizes continue to shrink, more overlay metrology data are needed to meet tighter overlay specifications which ensure high device yield. This study investigates the advantages of process corrections to overlay errors using various reduced measurement wafer schemes, and the improvement in yield that is realized using optimized overlay correction models. The capacitor layer of a 4x node DRAM product is chosen for verifying the sampling schemes in the experiment, because overlay errors of this layer are sensitive to device yield. The test wafers are split into five groups; four groups are sampled using various schemes and overlay correction models, and one group has a programmed overlay error. The post-correction overlay residuals in full wafer, baseline sampling and optimized sampling agree closely with predictions that are based on raw measurements. A scheme with iHOPC (intrafield high order process correction) partial third-order terms with a CPE (correction per exposure) function provides the best overlay performance. The averaged device yields of reduced sampling schemes are comparable with those of the full wafer scheme, however the reduction of the number of measurements that is made in optimized sampling reduce the metrology tool time by 26% from that required using the current scheme of factory. Therefore, the cost of metrology can be further reduced by applying the proposed optimized sampling map in the routine operations of fab.

As lithography moves into lower k1imaging, traditional illumination "source" shapes may perform marginally in resolving complex layouts. Subsequently hot-spots or warm-spots can result, leading to yield loss in production. Typically, lithographers solve such problems by modifying the local layout instead of optimizing the DOE (diffractive optical element) illumination shape. FlexRayTMcan easily implement freeform source shapes and allows a high degree of freedom in source optimization. Therefore, it becomes practical to use pixelated freeform sources to resolve hot spots or warm spots. In this paper, we investigate the use of freeform source optimization (SO) on a critical dynamic random access memory (DRAM) layer with warm spots to verify the effectiveness of a SO only flow using Tachyon SMO. In order to improve the warm spots without changing baseline performance for other patterns, we optimized not only the warm spot patterns of concern but also the critical reference patterns. Since the optimization minimizes EPE (edge placement error) and maximizes imaging quality for all enclosed patterns, the final optimized source shape performs similar to the baseline source for the base patterns while improving the performance of the warm spot pattern areas. Although the SO source is similar in shape to the baseline source, the optimized source provides enhanced depth of focus (DoF) for all warm spot patterns without suffering degradation in the normalized image log-slope (NILS) performance. Evaluation of the optimized SO source shows no obvious negative impact on modeled CDs across an array of L/S pattern combinations which cover all the pitches appearing in the periphery. Finally, the optimized source is demonstrated using ASML's FlexRayTMfor on-wafer evaluation. According to the observations from on-wafer experiments, consistent results to simulation are verified. Overall DoF for the identified warm spot patterns is definitely improved and no obvious pattern shape changes are found, as well. From the positive demonstration in simulation and on-wafer verification, the vast flexibility of the freeform source enables the SO flow with more powerful capability to improve local hot spot or warm spot problems without negatively impacting the other patterns.

Double Patterning Technology (DPT) was commonly accepted as the major workhorse beyond water immersion lithography for sub-38nm half-pitch line patterning before the EUV production. For dense hole patterning, classical DPT employs self-aligned spacer deposition and uses the intersection of horizontal and vertical lines to define the desired hole patterns. However, the increase in manufacturing cost and process complexity is tremendous. Several innovative approaches have been proposed and experimented to address the manufacturing and technical challenges. A novel process of double patterned pillars combined image reverse will be proposed for the realization of low cost dense holes in 30nm node DRAM. The nature of pillar formation lithography provides much better optical contrast compared to the counterpart hole patterning with similar CD requirements. By the utilization of a reliable freezing process, double patterned pillars can be readily implemented. A novel image reverse process at the last stage defines the hole patterns with high fidelity. In this paper, several freezing processes for the construction of the double patterned pillars were tested and compared, and 30nm double patterning pillars were demonstrated successfully. A variety of different image reverse processes will be investigated and discussed for their pros and cons. An economic approach with the optimized lithography performance will be proposed for the application of 30nm DRAM node.

In order to ensure long-term profitability, driving the operational costs down and improving the yield of a DRAM manufacturing process are continuous efforts. This includes optimal utilization of the capital equipment. The costs of metrology needed to ensure yield are contributing to the overall costs. As the shrinking of device dimensions continues, the costs of metrology are increasing because of the associated tightening of the on-product specifications requiring more metrology effort. The cost-of-ownership reduction is tackled by increasing the throughput and availability of metrology systems. However, this is not the only way to reduce metrology effort. In this paper, we discuss how the costs of metrology can be improved by optimizing the recipes in terms of the sampling layout, thereby eliminating metrology that does not contribute to yield. We discuss results of sampling scheme optimization for on-product overlay control of two DRAM manufacturing processes at Nanya Technology Corporation. For a 6x DRAM production process, we show that the reduction of metrology waste can be as high as 27% and overlay can be improved by 36%, comparing with a baseline sampling scheme. For a 4x DRAM process, having tighter overlay specs, a gain of ca. 0.5nm on-product overlay could be achieved, without increasing the metrology effort relative to the original sampling plan.

It is known that different overlay mark designs will have different responses to process setup conditions. An overlay mark optimized for the 45nm technology node might not be suitable for wafers using 30nm or 20nm process technologies due to changes in lithography and process conditions. As overlay control specifications become tighter and tighter, the process engineer requires metrics beyond precision, tool-induced shift (TIS) and TIS variability to determine the optimal target design. In this paper, the authors demonstrate a novel, comprehensive methodology which employs source of variance (SOV) to help engineers select the best overlay marks to meet overlay control requirements.

As is well recognized, source mask optimization (SMO) is a highly effective means of extending the lifetime of a certain photolithography generation without an expensive upgrade to the next generation optical system. More than an academic theory, source optimization first found practical applications in the debut of the pixel-like programmable illuminator in 2009 for producing near freeform illumination. Based on programmed illumination, related studies have demonstrated a nearly identical optical performance to that generated by the conventionally adopted diffractive optical element (DOE) device without the prolonged manufacturing time and relatively high cost of stocking up various DOEs. By using a commercially available pixel-like programmable illuminator from ASML, i.e. the FlexRay, this study investigates the effectiveness of FlexRay in enhancing image contrast and common process window. Before wafer exposure, full SMO and source-only (SO) optimization are implemented by Tachyon SMO software to select the optimum illumination source. Wafer exposure is performed by ASML XT:1950i scanner equipped with a FlexRay illuminator on a critical layer of DRAM process with known hotspots of resist peeling. Pupil information is collected by a sensor embedded in the scanner to confirm the produced source shape against the programmed source and the optically simulated CD. When the FlexRay illuminator is used, experimental results indicate that lithography hotspots are eliminated and depth of focus is improved by as much as 50% in comparison with those from a traditional AERIAL illuminator. Regular focus-exposure matrix (FEM) and the subsequent critical defects scanning reveal that the common process window of the tight-pitched array and the periphery can be enhanced simultaneously with no hotspot identified. Therefore, a programmed source is undoubtedly invaluable in terms of additional manufacturing flexibility and lower cost of ownership when attempting to improve product yield in high volume production.

As the cost of manufacturing high-end semiconductors continues to increase, the value of combining and streamlining metrology steps also increases. The two critical metrology steps for litho control are 1) overlay and 2) CD. In this study, the authors demonstrate the capability of just such a combination CD and Overlay metrology solution to improve not only the cost of manufacturing but also the quality of data and information feedback for better scanner control in high volume production. The authors demonstrate how using imaging and scatterometry technology on a single platform can provide a comprehensive litho control solution for both CD and overlay in the litho module. In the study, the authors will use full stack wafers from an advanced process node running in high volume manufacturing. Specifically, data will be generated using PROLITH for lithographic simulations for optimal target designs and then empirical data will be collected using the Archer 300 LCM from which optimal target selection and system performance will be determined and validated on wafers using this advanced process technology.

Overlay control in advanced integrated circuit (IC) manufacturing is becoming one of the leading lithographic challenges in the 3x and 2x nm process nodes. Production overlay control can no longer meet the stringent emerging requirements based on linear composite wafer and field models with sampling of 10 to 20 fields and 4 to 5 sites per field, which was the industry standard for many years. Methods that have emerged include overlay metrology in many or all fields, including the high order field model method called high order control (HOC), and field by field control (FxFc) methods also called correction per exposure. The HOC and FxFc methods were initially introduced as relatively infrequent scanner qualification activities meant to supplement linear production schemes. More recently, however, it is clear that production control is also requiring intense sampling, similar high order and FxFc methods. The added control benefits of high order and FxFc overlay methods need to be balanced with the increased metrology requirements, however, without putting material at risk. Of critical importance is the proper control of edge fields, which requires intensive sampling in order to minimize signatures. In this study we compare various methods of overlay control including the performance levels that can be achieved.