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The article discusses the development of a new optical technique to reveal invisible defects and contaminants in advanced packaging applications. It mentions that the technique can reveal contaminants that escape inspection technologies in many advanced packaging applications like wafer level packaging (WLP). It mentions challenges in advanced packaging applications like redistribution layer (RDL) line widths, use of metal and organic polymers.

The article offers the author's insights on the market trends for advanced packaging (AP) lithography. Topics discussed include the expected increase in the worldwide adoption and innovation of AP lithography, possible growth of wafer-level packaging (WLP) content, and the major lithography challenges which include high aspect ratios of imaging submicron redistribution layers (RDL), overlay errors reduction, and handling of warped substrates.

The article discusses improvement in safety, reliability, cost and yield with smart management in the sub-fab. Topics discussed include increase in number of 300mm wafer production-class fabs in operation worldwide, increasing application of high-flow chemical vapor deposition (CVD) processes in production of DRAM and other devices, and dilution of exhaust gases to mitigate flammability risks.

The article reports on the growth of chip carrier packaging with the adoption of quad flat no-lead (QFN) package design in the U.S. in 2013. Semiconductor market research firm IC Insights Inc. forecasts that the demand for QFN packages will stimulate the growth of flatpack/chip carrier (FP/CC) category of packages. The benefits of employing QFN and dual flat no-lead (DFN) packages in accelerating the manufacturing processes are outlined.

The article offers information on the chip-on-wafer-on-substrate (CoWoS) integrated process technology by TSMC Corp. It says that CoWoS uses a silicon wafer with through-silicon vias (TSVs) as a carrier to incorporate multiple chips in a device in order ot lessen power, lessen form factor, and enhance system performance. It states that CoWoS permits designers to partition die into smaller ones of partition subsystems through packaging multiple chips.

The article offers the author's insights regarding the transition of fan out from the niche technology to the mainstream. Topics include the difference between chip first and chip last fan out process in terms of the formation of redistribution trace structure, and singulation. It also mentions the Infineon Baseband chip which is the first embedded chip first type of fan out to go into mass production.