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To set up specification for 3D monolithic integration, for the first time, the thermal stability of state-of-the-art FDSOI (Fully Depleted SOI) transistors electrical performance is quantified. Post fabrication annealings are performed on FDSOI transistors to mimic the thermal budget associated to top layer processing. Degradation of the silicide for thermal treatments beyond 400 °C is identified as the main responsible for performance degradation for PMOS devices. For the NMOS transistors, arsenic (As) and phosphorus (P) dopants deactivation adds up to this effect. By optimizing both the n-type extension implantations and the bottom silicide process, thermal stability of FDSOI can be extended to allow relaxing upwards the thermal budget authorized for top transistors processing.

In this paper, we demonstrate low junction leakage for Fully Depleted Silicon On Insulator (FDSOI) devices fabricated with a low thermal budget (⩽650 °C), which commonly exhibit leakage problems due to the presence of defects in or close to depletion regions. We show through both experimental data and Kinetic Monte Carlo (KMC) simulations that the reduction of the film thickness and Raised Source Drain (RSD) allow the elimination of defects in critical regions in spite of the reduced thermal budget in the very early stage of the anneal. KMC simulations also show that defects are annealed-out in this critical region even for 500 °C anneals. Low temperature process appears then as a suitable process for advanced devices.

We have evaluated various Cyclic Selective Epitaxial Growth/Etch (CSEGE) processes in order to grow “mushroom-free” Si and SiGe:B Raised Sources and Drains (RSDs) on each side of ultra-short gate length Extra-Thin Silicon-On-Insulator (ET-SOI) transistors. The 750 °C, 20 Torr Si CSEGE process we have developed (5 chlorinated growth steps with four HCl etch steps in-between) yielded excellent crystalline quality, typically 18 nm thick Si RSDs. Growth was conformal along the Si3N4 sidewall spacers, without any poly-Si mushrooms on top of unprotected gates. We have then evaluated on blanket 300 mm Si(001) wafers the feasibility of a 650 °C, 20 Torr SiGe:B CSEGE process (5 chlorinated growth steps with four HCl etch steps in-between, as for Si). As expected, the deposited thickness decreased as the total HCl etch time increased. This came hands in hands with unforeseen (i) decrease of the mean Ge concentration (from 30% down to 26%) and (ii) increase of the substitutional B concentration (from 2 × 1020 cm−3 up to 3 × 1020 cm−3). They were due to fluctuations of the Ge concentration and of the atomic B concentration [B] in such layers (drop of the Ge% and increase of [B] at etch step locations). Such blanket layers were a bit rougher than layers grown using a single epitaxy step, but nevertheless of excellent crystalline quality. Transposition of our CSEGE process on patterned ET-SOI wafers did not yield the expected results. HCl etch steps indeed helped in partly or totally removing the poly-SiGe:B mushrooms on top of the gates. This was however at the expense of the crystalline quality and 2D nature of the ∼45 nm thick Si0.7Ge0.3:B recessed sources and drains selectively grown on each side of the imperfectly protected poly-Si gates. The only solution we have so far identified that yields a lesser amount of mushrooms while preserving the quality of the S/D is to increase the HCl flow during growth steps.

Thanks to ultimate Si nMOSFETs with physical gate length down to 16 nm, the main challenges related to conventional transistors have been estimated. Short channel effect control is difficult below 40 nm due to the large TED of BF 2 halos. Nevertheless drain current higher than 800 μA/μm @ V d =1.5 V can be reached. Such performance is not a consequence of non-stationary effects since these are limited by the degradation of the low longitudinal field mobility on conventional short transistor. Ultimate transport is also analysed thanks to short and narrow devices. At low temperature, these MOSFETs are shown to operate like single electron transistors.