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An EUV dark field image of a phase defect on a patterned mask was studied using simulation. The wafer images of the defect were obtained by simulation, and wafer CD deviation caused by the defect was calculated. The dark field image of the defect was also obtained by simulation, and the defect signal intensity was calculated and compared with the wafer CD deviation. There was a significant relationship between the wafer CD deviation and the defect signal intensity in the dark field image at the respective maximum in the through-focus range. Therefore, the wafer CD deviation can be estimated from the dark field image using though focus.

Recently, much attention has been paid on nanoimprint lithography (NIL) because of its capability for fabricating device at a low cost without multiple patterning. It is considered as a candidate for next generation lithography technology. NIL is one to one lithography and contact transfer technique using template. Therefore, the lithography performance depends greatly on the quality of the template pattern. And there are some challenges to be solved for defect repair of template because pattern size of template is as same as that of wafer. In order to realize the defect repair of template using electron beam (EB) repair tools, it is necessary to control the EB irradiated area and dose amount of EB repair process more accurately. By optimizing these conditions, EB repair process for template has been improved. In this paper, we evaluated etching repair of a master template and the imprinting to replica. Programmed missing defects on master template were repaired by changing parameters of EB repair tool. It was confirmed that the relationship of critical dimension (CD) and depth of etching repair process for master template and the influence on replica imprinting. As a result, the repair process for master template with hole pattern enables the corresponding CD error of the replica template to be less than ±10% of the target CD.

The introduction of EUV lithography to high volume manufacturing is now within reach for 7nm technology node and beyond (1), at least for some steps. The scheduling is in transition from long to mid-term. Thus, all contributors need to focus their efforts on the production requirements. For the photo mask industry, these requirements include the control of defectivity, CD performance and lifetime of their masks. The mask CD performance including CD uniformity, CD targeting, and CD linearity/ resolution, is predominantly determined by the photo resist performance and by the litho and etch processes. State-of-the-art chemically amplified resists exhibit an asymmetric resolution for directly and indirectly written features, which usually results in a similarly asymmetric resolution performance on the mask. This resolution gap may reach as high as multiple tens of nanometers on the mask level in dependence of the chosen processes. Depending on the printing requirements of the wafer process, a reduction or even an increase of this gap may be required. A potential way of tuning via the etch process, is to control the lateral CD contribution during etch. Aside from process tuning knobs like pressure, RF powers and gases, which usually also affect CD linearity and CD uniformity, the simplest knob is the etch time itself. An increased over etch time results in an increased CD contribution in the normal case. , We found that the etch CD contribution of ARC layer etch on EUV photo masks is reduced by longer over etch times. Moreover, this effect can be demonstrated to be present for different etch chambers and photo resists.

Semiconductor technology nodes are steadily miniaturizing. On the other hand, various efforts have been made to reduce costs, mass production lines have shifted from 200 mmφ of Si wafer to 300 mmφ, and technology development of Si wafer 450 mmφ is also in progress. As a photomask, 6-inch size binary Cr mask has been used for many years, but in recent years, the use of 9-inch binary Cr masks for Proximity Lithography Process in automotive applications, MEMS, packages, etc. has increased, and cost reduction has been taken. Since the miniaturization will progress in the above applications in the future, products corresponding to miniaturization are also desired in 9-inch photomasks. The high grade Cr - binary mask blanks used in proximity exposure process, there is a prospect of being able to use it by ULVAC COATING CORPORATION's tireless research. As further demands for miniaturization, KrF and ArF Lithography Process, which are used for steppers and scanners , there are also a demand for 9-inch size Mask Blanks. In ULVAC COATING CORPORATION, we developed a 9 - inch size KrF PSM mask Blanks prototype in 2016 and proposed a new high grade 9 - inch photomask. This time, we have further investigated and developed 9-inch size ArF PSM Mask Blanks corresponding to ArF Lithography Process, so we report it.

Nanoimprint Lithography (NIL) has been shown to be an effective technique for replication of nano-scale features. Jet and Flash Imprint Lithography* (J-FIL*) involves the field-by-field deposition and exposure of a low viscosity resist deposited by jetting technology onto the substrate. The patterned mask is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is removed, leaving a patterned resist on the substrate. There are many criteria that determine whether a particular technology is ready for high volume semiconductor manufacturing. Included on the list are overlay, throughput and defectivity. Imprint lithography, like any lithographic approach requires that defect mechanisms be identified and eliminated in order to consistently yield a device. NIL has defect mechanisms unique to the technology, and they include liquid phase defects, solid phase defects and particle related defects. Especially more troublesome are hard particles on either the mask or wafer surface. Hard particles run the chance of creating a permanent defect in the mask, which cannot be corrected through a mask cleaning process. If Cost of Ownership (CoO) requirements are to be met, it is critical to minimize particle formation and extend mask life. To meet the CoO requirements, mask life must meet or exceed 1000 wafers. If, we make the conservative assumption that every particles causes damage to the mask pattern, the number of particle adders must be less than 0.001 pieces per wafer pass in the NIL tool. Therefore, aggressive strategies are needed to reduce particles in the tool. In this paper, we will report on the techniques required to meet this condition and will describe how the particle reduction techniques can be extended to our FPA-1200NZ2C system.

Printing of thick resist patterns with a high aspect ratio and vertical side walls was investigated. Such resist patterns are required for using as molds of electroplating, and patterning feasibility in a small field of 2 mm square was verified in the past researches. However, it is necessary to print patterns homogeneously in an exposure field with a practical size of larger than 10 mm square, for example. As profiles of resist patterns for the use of electroplating molds, rectangular cross-sections are preferable. For this reason, patterns were printed in the negative resist SU-8 with a thickness of 50 μm using an exposure system with a field size of 15 mm square. Before using the thick SU-8, the best focus position of the exposure system was investigated. To find out the best focus position, line and space (LS) patterns were printed using a positive resist OFPR-800 with a thickness of approximately 1 μm. The focus position where patterns were most clearly formed on the wafer was decided to be the focus origin, and defocuses were controlled by moving wafers downward. Next, 50-μm LS patterns were printed in 50-μm thick SU-8. As a result, LS patterns with rectangular cross sections and a height of 40 μm were obtained when the defocus and the exposure time were set at 2000 μm and for 70 seconds, respectively. It was demonstrated that patterns with rectangular cross sections were printed in 3x5 mm2 exposure fields.

Continuous shrinking of the semiconductor device dimensions demands steady improvements of the lithographic resolution on wafer level. These requirements challenge the photomask industry to further improve the mask quality in all relevant printing characteristics. In this paper topography of the Phase Shift Masks (PSM) was investigated. Effects of hard mask etch on phase shift uniformity and mask absorber profile were studied. Design of experiments method (DoE) was used for the process optimization, whereas gas composition, bias power of the hard mask main etch and bias power of the over-etch were varied. In addition, influence of the over-etch time was examined at the end of the experiment. Absorber depth uniformity, sidewall angle (SWA), reactive ion etch lag (RIE lag) and through pitch (TP) dependence were analyzed. Measurements were performed by means of Atomic-force microscopy (AFM) using critical dimension (CD) mode with a boot-shaped tip. Scanning electron microscope (SEM) cross-section images were prepared to verify the profile quality. Finally CD analysis was performed to confirm the optimal etch conditions. Significant dependence of the absorber SWA on hard mask (HM) etch conditions was observed revealing an improvement potential for the mask absorber profile. It was found that hard mask etch can leave a depth footprint in the absorber layer. Thus, the etch depth uniformity of hard mask etch is crucial for achieving a uniform phase shift over the active mask area. The optimized hard mask etch process results in significantly improved mask topography without deterioration of tight CD specifications.

The aim of this work is to fabricate patterned nitride membranes with Si-MEMS-technology as a platform to build up new membrane-electrode-assemblies (MEA) for alkaline fuel cell applications. Two 6-inch wafer processes based on chemical vapor deposition (CVD) were developed for the fabrication of separated nitride membranes with a nitride thickness up to 1 μm. The mechanical stability of the perforated nitride membrane has been adjusted in both processes either by embedding of subsequent ion implantation step or by optimizing the deposition process parameters. A nearly 100% yield of separated membranes of each deposition process was achieved with layer thickness from 150 nm to 1 μm and micro-channel pattern width of 1μm at a pitch of 3 μm. The process for membrane coating with electrolyte materials could be verified to build up MEA. Uniform membrane coating with channel filling was achieved after the optimization of speed controlled dip-coating method and the selection of dimethylsulfoxide (DMSO) as electrolyte solvent. Finally, silver as conductive material was defined for printing a conductive layer onto the MEA by Ink-Technology. With the established IR-thermography setup, characterizations of MEAs in terms of catalytic conversion were performed successfully. The results of this work show promise for build up a platform on wafer-level for high throughput experiments.

Calibration and validation of fluorescence microscopy devices and components require a high level of stability and repeatability in their fluorescent properties, both spatially and temporally. In order to establish a dependable reference point, from which all variations within the microscope and peripheral devices can be tested, an exceedingly homogeneous fluorescence response must be provided through a calibration tool. We present material system optimization and microfabrication process development, as well as long-term stability considerations for such a calibration tool. Stringent specifications for film thickness ( Fluorescent, ligand capped core-shell quantum dots (SMQDs) were embedded in diluted PMMA at low concentrations. The formulations were spin-coated on silicon and glass wafers to obtain films with thicknesses under 1 μm and low variations on a 100 mm wafer. Fluorescence properties of the SMQD were preserved in the matrix material, and agglomerations were not detectable in the fluorescence response nor in SEM images. Gradual degradation of the fluorescence response due to film aging was managed through robust packaging solutions.

To improve the transmittance of THz component and overcome the difficulties of fragile structure as well as ensuring precise alignment of existing methods, a new method involving the mature 3DIC through-silicon via (TSV) technology has been proposed to make anti-reflection layer with suitable effective refractive index based on the robustness of Si wafer. Cu wire-grid polarizers were also fabricated on wafer. The THz polarizers were completed after wafer bonding with Cu sealing ring and In/Sn guard ring. Not only the new method is easier for production with better performance, but also the silicon substrate has several advantages. The novel method has proven that THz optical component could be constructed with a nearly 100% transmittance, or widened the transmittance spectrum range from 0.5 to 2 THz when transmittances is sacrificed to 70% instead of a near 100%. Furthermore, a robust structure could also be expected with broadband transmission and excellent extinction ratio. It is properly optimized for mass production because the fabrication method could be easily done and does not required high cost.

A real-time method based on laser scattering technology was used to detect the interaction process of GaAs with a 1080 nm laser. The detector collected the scattered laser beam from the GaAs wafer. The main scattering sources were back surface at first, later turn into front surface and vapor, so scattering signal contained much information of the interaction process. The surface morphologies of GaAs with different irradiation times were observed using an optical microscope to confirm occurrence of various phenomena. The proposed method is shown to be effective for the real-time detection of GaAs. By choosing a proper wavelength, the scattering technology can be promoted in detection of thicker GaAs wafer or other materials.

The increasing importance of extracting high optical power out of semiconductor lasers motivated several studies in catastrophic optical damage (COD) level improvement. In this study, the influence of the resonator length in high-power broad-area (BA) AlGaInP lasers on COD is presented. For the analyses, several 638 nm AlGaInP 60 μm BA lasers from the same wafer were used. Resonator lengths of 900, 1200, 1500, and 1800 μm were compared. In order to independently examine the effect of the resonator length on the maximum power reached by the lasers before COD (PCOD), the lasers used are uncoated and unmounted, and PCOD under pulsed mode was determined. It was found that higher output powers and eventually higher PCOD can be achieved using longer resonators; however, it was also found that this is mainly useful when working at high output powers far away from the laser threshold, since the threshold current and slope efficiency worsen when the resonator length increases.

Dimension shrinkage has been a major driving force in the development of integrated circuit processing over a number of decades. The Self-Aligned Quadruple Patterning (SAQP) technique is widely adapted for sub-10nm node in order to achieve the desired feature dimensions. This technique provides theoretical feasibility of multiple pitch-halving from 193nm immersion lithography by using various pattern transferring steps. The major concept of this approach is to a create spacer defined self-aligned pattern by using single lithography print. By repeating the process steps, double, quadruple, or octuple are possible to be achieved theoretically. In these small architectures, line roughness control becomes extremely important since it may contribute to a significant portion of process and device performance variations. In addition, the complexity of SAQP in terms of processing flow makes the roughness improvement indirective and ineffective. It is necessary to discover a new approach in order to improve the roughness in the current SAQP technique. In this presentation, we demonstrate a novel method to improve line roughness performances on 30nm pitch SAQP flow. We discover that the line roughness performance is strongly related to stress management. By selecting different stress level of film to be deposited onto the substrate, we can manipulate the roughness performance in line and space patterns. In addition, the impact of curvature change by applied film stress to SAQP line roughness performance is also studied. No significant correlation is found between wafer curvature and line roughness performance. We will discuss in details the step-by-step physical performances for each processing step in terms of critical dimension (CD)/ critical dimension uniformity (CDU)/line width roughness (LWR)/line edge roughness (LER). Finally, we summarize the process needed to reach the full wafer performance targets of LWR/LER in 1.07nm/1.13nm on 30nm pitch line and space pattern.

Single-event effects (SEEs) refer to phenomena that arise from the interaction of single energetic particles with microelectronic devices, as is experienced in harsh radiation environments. Carrier generation induced by two-photon absorption (TPA) has become a valuable tool for SEE investigations of microelectronic structures owing to its unique ability to inject carriers through the wafer, directly into well-defined locations in complex circuits. Recent effort has focused on putting the TPA SEE technique on a more quantitative basis. This paper addresses the recent successes in achieving this goal, as well as the challenges that are faced moving forward.

Silicon carbide (SiC) is a wide band-gap semi-conductor material that is used increasingly for high voltage power devices, since it has a higher breakdown field strength and better thermal conductivity than silicon. However, in particular its hardness makes wafer processing difficult and many standard semi-conductor processes have to be specially adapted. We measure the effects of (i) mechanical processing (i.e. grinding of the backside) and (ii) chemical and thermal processing (i.e. doping and annealing), using confocal microscopy to measure the surface roughness of ground wafers and micro-Raman spectroscopy to measure the stresses induced in the wafers by grinding. 4H-SiC wafers with different dopings were studied before and after annealing, using depth-resolved micro-Raman spectroscopy to observe how doping and annealing affect: i.) the damage and stresses induced on the crystalline structure of the samples and ii.) the concentration of free electrical carriers. Our results show that mechanical, chemical and thermal processing techniques have effects on this semiconductor material that can be observed and characterized using confocal microscopy and high resolution micro Raman spectroscopy.

There is a strong commercial incentive for characterizing power semiconductor devices during manufacture non-destructively. One area of concern are the stresses in the material introduced during manufacture by processes such as wafer thinning and chip separation. Raman spectroscopy can be used to measure stress in different semiconductor materials directly, non-destructively and quantitatively. Here, we describe Raman measurements on two semiconductor materials: silicon and silicon carbide. Measurements of silicon carbide are made on silicon carbide wafers; stress and material analyses of silicon are performed on: (i.) silicon wafers that had undergone different wafer thinning methods and (ii) along die sidewalls formed by mechanical and laser dicing. Our measurements demonstrate that micro-Raman spectroscopy is a feasible method for both measuring stress in thin wafers and for optimizing the thin wafer processes.

This work presents the deposition and characterization of AlxNy thin films for using them as pyroelectric detector material. To test the pyroelectric effect, capacitors with Au electrodes were fabricated. The diameter of the electrodes for capacitor used was 1100 μm while the distances between these two electrodes was 2200 μm. On a 3- inch diameter cleaned silicon wafer a 100-nm thick AlxNy films were deposited using an Al target and Ar:N2 = 1:1 flow and 5 mTorr chamber pressure. Finally, a 100-nm thick Au layer was deposited and lifted off by using conventional photo lithography to form the electrodes of capacitors. All the layers were deposited by radio frequency sputtering at room temperature. The AlxNy thin films were annealed at 700 0C in N2 environment for 10 minutes. X-ray diffraction showed that the films are poly-crystalline with peaks in (100), (002) and (101) directions. The pyroelectric current increased from 3.38 × 10-14 A at 303 K to 1.75 × 10-13 at 353 K. When the temperature varied between 303 K to 353 K the pyroelectric coefficient was increased from 8.60 × 10-9 C/m2K to 3.76 × 10-8 C/m2K while the loss tangent remains almost constant to ~1.5 × 10-5 when the temperature was varied in the same range.

As the industry marches on onto the 5nm node and beyond, scaling has slowed down, with all major IDMs & foundries predicting a 3-4 year cadence for scaling. A major reason for this slowdown is not the technical challenge of making features smaller, but effective control of variation that creeps in to the fabrication process. That variability manifests itself as edge placement error (EPE), which has a direct impact on wafer yield. Simply defined as the variance between design intent vs. actual on-wafer results, EPE is one of the foremost challenges being faced by the industry at the advanced node for both logic and memory. This is especially critical at three stages: the front end of line (FEOL) STI patterning; middle of line (MOL) contact patterning; and back end of line (BEOL) trench patterning where the desired tight pitch demands EPE control beyond the capability of 193i multi-patterning or even EUV single pattern. In order to mitigate this EPE challenge, we are proposing self-alignment of blocks & cuts through a multi-color materials integration concept. This approach, termed as “Self-aligned block or Cut (SAB or SACut)”, simply trades off the un-manageable overlay requirement into a more manageable etch selectivity challenge, by having multiple materials filled in every other trench or line. In this paper we will introduce self-alignment based block and cut strategies using multi-color materials integration and show implementation for BEOL trench block patterning. We will present a breakdown of the key unit process challenges that were needed to be resolved for enabling the self-alignment such as: (a) material selection of multi-color approach; (b) planarization of spin on materials; (c) void-free gap fill for high aspect ratio features; and last but not the least, (c) etch selectivity of etching one material with respect to all other materials exposed. Further, we will present a comparison of our new self-alignment approach with standard approaches where we will articulate the advantages in terms of EPE relaxation and mask number reduction. We will conclude our talk with a brief snapshot of the future direction of our EPE improvement strategies and our view on the future of patterning beyond 5nm node for the industry.

imec’s DTCO and EUV achievement toward imec 7nm (iN7) technology node which is industry 5nm node equivalent is reported with a focus on cost and scaling. Patterning-aware design methodology supports both iArF multiple patterning and EUV under one compliant design rule. FinFET device with contacted poly pitch of 42nm and metal pitch of 32nm with 7.5-track, 6.5-track, and 6-track standard cell library are explored. Scaling boosters are used to provide additional scaling and die cost benefit while lessening pitch shrink burden, and it makes EUV insertion more affordable. EUV pattern fidelity is optimized through OPC, SMO, M3D, mask sizing and SRAF. Processed wafers were characterized and edge-placement-error (EPE) variability is validated for EUV insertion. Scale-ability and cost of ownership of EUV patterning in aligned with iN7 standard cell design, integration and patterning specification are discussed.

The non-dispersive fundamental shear horizontal (SH0) and torsional [T(0,1)] waves are extremely useful in guidedwave-based inspection techniques. However, excitation of SH0 and T(0,1) waves using piezoelectrics is always a challenge. In this work, firstly, a newly defined face-shear d24 PZT wafer is proposed to excite and receive SH0 wave mode. The d24 wafer is in-plane poled and its working electric field is applied along another orthogonal in-plane direction. Both finite element simulations and experiments show that single SH0 mode can be excited by using the d24 wafer along two orthogonal directions (0° and 90°). Then an omnidirectional SH0 wave piezoelectric transducer (OSHPT) is developed which consists of a circular array of twelve face-shear d24 trapezoidal PZT elements. Results show that the proposed OSH-PT exhibits good omnidirectional properties, no matter it is used as a SH0 wave transmitter or receiver. Finally, the development of a T(0,1) wave transducer for pipes based on a ring array of d24 PZT elements is described. Both finite element simulations and experiments show that the d24 elements ring can excite single T(0,1) mode and suppress all the unwanted non-axisymmetric modes. This work may greatly promote the applications of SH0 and T(0,1) waves in nondestructive testing (NDT) and structural health monitoring (SHM).

A novel method of sub-nanometer uncertainty for the 3D-profile measurement and LWR (Line Width Roughness) measurement by using FIB (Focused Ion Beam) processing, and TEM (Transmission Electron Microscope) and CD-SEM (Critical Dimension Scanning Electron Microscope) images measurement is proposed to standardize 3D-profile measurement through reference metrology. In this article, we apply the methodology to line profile measurements and roughness measurement of advanced FinFET (Fin-shaped Field-Effect Transistor) features. The FinFET features are horizontally sliced as a thin specimen by FIB micro sampling system. Horizontally images of the specimens are obtained then by a planar TEM. LWR is calculated from the edges positions on TEM images. Moreover, we already have demonstrated the novel on-wafer 3D-profile metrology as "FIB-to-CDSEM method" with FIB slope cut and CD-SEM measuring. Using the method, a few micrometers wide on a wafer is coated and cut by 45-degree slope using FIB tool. Then, the wafer is transferred to CD-SEM to measure the cross section image by top down CD-SEM measurement. We applied FIB-to-CDSEM method to a CMOS image sensor feature. The 45-degree slope cut surface is observed using AFM. The surface profile of slope cut surface and line profiles are analyzed for improving the accuracy of FIB-to-CDSEM method.

A novel d36-type piezoelectric wafer fabricated from lead magnesium niobate-lead titanate (PMN-PT) is explored for the generation of in-plane horizontal shear waves in plate structures. The study focuses on the development of a linear phased array (PA) of PMN-PT wafers to improve the damage detection capabilities of a structural health monitoring (SHM) system. An attractive property of in-plane horizontal shear waves is that they are nondispersive yet sensitive to damage. This study characterizes the directionality of body waves (Lamb and horizontal shear) created by a single PMN-PT wafer bonded to the surface of a metallic plate structure. Second, a linear PA is designed from PMN-PT wafers to steer and focus Lamb and horizontal shear waves in a plate structure. Numerical studies are conducted to explore the capabilities of a PMN-PT-based PA to detect damage in aluminum plates. Numerical simulations are conducted using the Local Interaction Simulation Approach (LISA) implemented on a parallelized graphical processing unit (GPU) for high-speed execution. Numerical studies are further validated using experimental tests conducted with a linear PA. The study confirms the ability of an PMN-PT phased array to accurately detect and localize damage in aluminum plates.

The next generation technology and emerging memory devices require gradually tighter lithographic focus control on imaging critical layers. Especially in case of BEOL process, big PDO (Process Dependent Offset) from large intra-field topography steps affects the process margin directly. There are couple of scanner options to reduce PDO, such as AGILE which provides several benefits. However, for certain use cases the AGILE sensor may not be the optimal solution. In this paper, we introduce the concept and development background of iFPC (intra-field Finger Print Correction). iFPC is a scanner option that removes the generic 3D fingerprint seen in the leveling data so that both process dependency and actual wafer topography are not followed during wafer exposure. In addition, we compare the degree of process margin improvement when applying iFPC compared to that of AGILE on a critical layer. The achieved results demonstrate that by applying iFPC it is possible to gain an additional 15~20nm DoF. In other words, on this use case our feasibility suggests that by removing the generic 3D fingerprint seen in the leveling data, it is possible to achieve a better focus performance than when trying to follow the topography during scanning. In conclusion, we found another good way to improve the process margin through this comparative experiment. Therefore, our next step will be to setup the methodology to select the use cases where iFPC is the optimal solution.

Embedded and surface bonded piezoelectric wafers have been widely used for control, energy harvesting, and structural health monitoring applications. The basis for all these applications is the energy transfer between the piezoelectric wafer and the host structure, which takes place through the adhesive bonding layer. The characteristics of the bonding layer are found to have an important impact on the sensing and actuation capabilities of piezoelectric-based applications. In this paper, the high-frequency dynamic response of an elastic beam coupled with a piezoelectric wafer is investigated, including the bonding layer in between. A previously developed three-layer spectral element model, with high-frequency capabilities, is utilized for this purpose. Timoshenko beam and elementary rod theories are adopted to describe axial and lateral deformations in each of the three layers. A parametric study is conducted to evaluate the effects of bonding layer characteristics on the steady-state dynamic response of the coupled system, including frequency response functions and electromechanical impedance. The frequency-dependent nature of bonding layer effects is highlighted and discussed.

We demonstrate a tool which can function as an interface between VLSI designers and process-technology engineers throughout the Design-Technology Co-optimization (DTCO) process. This tool uses a Monte Carlo algorithm on the output of lithography simulations to model the frequency of fail mechanisms on wafer. Fail mechanisms are defined according to process integration flow: by Boolean operations and measurements between original and derived shapes. Another feature of this design rule optimization methodology is the use of a Markov-Chain-based algorithm to perform a sensitivity analysis, the output of which may be used by process engineers to target key process-induced variabilities for improvement. This tool is used to analyze multiple Middle-Of-Line fail mechanisms in a 10nm inverter design and identify key process assumptions that will most strongly affect the yield of the structures. This tool and the underlying algorithm are also shown to be scalable to arbitrarily complex geometries in three dimensions. Such a characteristic which is becoming more important with the introduction of novel patterning technologies and more complex 3-D on-wafer structures.

Many different advanced devices and design layers currently employ double patterning technology (DPT) as a means to overcome lithographic and OPC limitations at low k1 values. Certainly device layers with k1 value below 0.25 require DPT or other pitch splitting methodologies. DPT has also been used to improve patterning of certain device layers with k1 values slightly above 0.25, due to the difficulty of achieving sufficient pattern fidelity with only a single exposure. Unfortunately, this broad adoption of DPT also came with a significant increase in patterning process cost. In this paper, we discuss the development of a single patterning technology process using an integrated Inverse Lithography Technology (ILT) flow for mask synthesis. A single pattering technology flow will reduce the manufacturing cost for a k1 > 0.25 full chip random contact layer in a memory device by replacing the more expensive DPT process with ILT flow, while also maintaining good lithographic production quality and manufacturable OPC/RET production metrics. This new integrated flow consists of applying ILT to the difficult core region and traditional rule-based assist features (RBAFs) with OPC to the peripheral region of a DRAM contact layer. Comparisons of wafer results between the ILT process and the non-ILT process showed the lithographic benefits of ILT and its ability to enable a robust single patterning process for this low-k1 device layer. Advanced modeling with a negative tone develop (NTD) process achieved the accuracy levels needed for ILT to control feature shapes through dose and focus. Details of these afore mentioned results will be described in the paper.

To meet scaling requirements, the semiconductor industry has extended 193nm immersion lithography beyond its minimum pitch limitation using multiple patterning schemes such as self-aligned double patterning, self-aligned quadruple patterning and litho-etch / litho etch iterations. Those techniques have been declined in numerous options in the last few years. Spacer on spacer pitch splitting integration has been proven to show multiple advantages compared to conventional pitch splitting approach. Reducing the number of pattern transfer steps associated with sacrificial layers resulted in significant decrease of cost and an overall simplification of the double pitch split technique. While demonstrating attractive aspects, SAQP spacer on spacer flow brings challenges of its own. Namely, material set selections and etch chemistry development for adequate selectivities, mandrel shape and spacer shape engineering to improve edge placement error (EPE). In this paper we follow up and extend upon our previous learning and proceed into more details on the robustness of the integration in regards to final pattern transfer and full wafer critical dimension uniformity. Furthermore, since the number of intermediate steps is reduced, one will expect improved uniformity and pitch walking control. This assertion will be verified through a thorough pitch walking analysis.

Nanoimprint lithography (NIL) is a promising technique for fine-patterning with a lower cost than other lithography techniques such as EUV or immersion with multi-patterning. NIL has the potential of "single" patterning for both line patterns and hole patterns with a half-pitch of less than 20nm. NIL tools for semiconductor manufacturing employ die-by-die alignment system with moire fringe detection which gives alignment measurement accuracy of below 1nm. In this paper we describe the evaluation results of NIL the overlay performance using an up-to-date NIL tool for 300mm wafer. We show the progress of both "NIL-to-NIL" and "NIL-to-optical tool" distortion matching techniques. From these analyses based on actual NIL overlay data, we discuss the possibility of NIL overlay evolution to realize an on-product overlay accuracy to 3nm and beyond.

Laser-produced plasma (LPP) EUV sources have demonstrated approximately 125 W at customer sites, establishing confidence in EUV lithography as a viable manufacturing technology. However, beyond the 7 nm technology node existing scanner/source technology must enable higher-NA imaging systems (requiring increased resist dose and providing half-field exposures) and/or EUV multi-patterning (requiring increased wafer throughput proportional to the number of exposure passes. Both development paths will require a substantial increase in EUV source power to maintain the economic viability of the technology, creating an opportunity for free-electron laser (FEL) EUV sources. FEL-based EUV sources offer an economic, high-power/single-source alternative to LPP EUV sources. Should free-electron lasers become the preferred next generation EUV source, the choice of FEL emission architecture will greatly affect its operational stability and overall capability. A near-term industrialized FEL is expected to utilize one of the following three existing emission architectures: (1) selfamplified spontaneous emission (SASE), (2) regenerative amplification (RAFEL), or (3) self-seeding (SS-FEL). Model accelerator parameters are put forward to evaluate the impact of emission architecture on FEL output. Then, variations in the parameter space are applied to assess the potential impact to lithography operations, thereby establishing component sensitivity. The operating range of various accelerator components is discussed based on current accelerator performance demonstrated at various scientific user facilities. Finally, comparison of the performance between the model accelerator parameters and the variation in parameter space provides a means to evaluate the potential emission architectures. A scorecard is presented to facilitate this evaluation and provide a framework for future FEL design and enablement for EUV lithography applications.

Silicon testing results are regularly collected for a particular lot of wafers to study yield loss from test result diagnostics. Product engineers will analyze the diagnostic results and perform a number of physical failure analyses to detect systematic defects which cause yield loss for these sets of wafers in order to feedback the information to process engineers for process improvements. Most of time, the systematic defects that are detected are major issues or just one of the causes for the overall yield loss. This paper will present a working flow for using design analysis techniques combined with diagnostic methods to systematically transform silicon testing information into physical layout information. A new set of the testing results are received from a new lot of wafers for the same product. We can then correlate all the diagnostic results from different periods of time to check which blocks or nets have been highlighted or stop occurring on the failure reports in order to monitor process changes which impact the yield. The design characteristic analysis flow is also implemented to find 1) the block connections on a design that have failed electrical test or 2) frequently used cells that been highlighted multiple times.

As technology node shrinks down, hotspots, i.e. patterning failures on wafer after etching process, become an inevitable problem. The main cause of such hotspots is low contrast of aerial image. There are several methods that can improve aerial image contrast such as SRAF insertion and OPC. However, it is difficult to fix all hotspots by applying only SRAF and OPC in advanced technology node. This paper proposes a new post-layout optimization method, before SRAF and OPC, based on SOCS kernel for improving aerial image contrast and reducing hotspots. Experimental results show average 4nm PV-band improvement, as a result of contrast improvement.

Previous studies have quantified the impact of source error on wafer CDs in the presence of OPC. The studies found that when a 100% emitting source error is introduced into the OPC model, the corrected mask is minimally impacted through process when small errors are introduced on the source. However, as slightly larger errors are placed on the source used in the OPC mode, catastrophic failures are found. When the same errors are introduced to the exposure source when the mask is corrected with a perfect source, there is a significant through process CD variation in the system but there are no clearly catastrophic failures. The present study continues beyond the initial work to better understand the interaction between source errors and OPC. In this case, partial transmission and zero transmission errors are introduced into the study. The initial study found a CD bias and extra CD variation when the error was located in the transmissive area for the source error case. As the result of a previous study, these effects are thought to be due to scattered background illumination and pattern shift, respectively. These effects were not as readily observed in the mask error case. This study looks at the interaction of different errors in the source during both exposure and OPC generation to better understand the effects of source errors on the final pattern. A resulting analysis of study is presented. The analysis explains whether scattered background illumination and pattern shift are the mechanisms of the source effects. This can be concluded if the same effects can be generated in the mask error case using various source errors. The software methodology used to execute these studies is presented in detail.

DUV immersion lithography (ArFi) continues to be the primary lithographic method for semiconductor manufacturers. Use of ArFi lithography requires patterning budget improvements in the range of 1/10 nm especially for interconnect layers[1] ; for advanced process technology nodes, every Angstrom counts. Previous investigations into the effects of light source bandwidth on imaging performance have provided the foundation for this work[2-10]. This study will focus on the increase in image contrast that 200 fm light source E95 bandwidth enables on Self-Aligned Double Patterning (SADP) and Self-Aligned Quadruple Patterning (SAQP) features. The impact of 200 fm E95 bandwidth on the CD and Edge Placement Error (EPE) performance of core (grating) and block features will be assessed using an imec 7 nm process node test vehicle. The on wafer experimental results will be compared with the simulation predicted responses of the target features to lower light source bandwidth.

In the process nodes of 10nm and below, the patterning complexity, along with multiple pattern processing and the advance materials required, has in turn resulted in a need to optimize wafer alignment mark simulation capabilities in order to achieve the required precision and accuracy for wafer alignment performance. ASML’s Design for Control (D4C) application for wafer alignment mark design has been extended to support the computational prediction of alignment mark performance for the latest alignment sensor on the TwinScan NXT:1980Di platform and beyond. Additional new simulation functionality will also be introduced to enable aberration sensitivity matching between the alignment mark and the device cell patterns. As a result, the design of more robust alignment marks is achieved, extending simulation capabilities for the design of wafer alignment marks and the recommendation of alignment recipe settings.

Over the years, lithography engineers continue to focus on CD control, overlay and process capability to meet current node requirements for yield and device performance. Use of ArFi lithography for advanced process nodes demands challenging patterning budget improvements in the range of 1/10 nm especially for interconnect layers.(1) Previous experimental and simulation based investigations into the effects of light source bandwidth on imaging performance have provided the foundation for this work.(2-6) The goal from the light source manufacturer is to further enable capability and reduce variation through a number of parameters.(7-10) In this study, the authors focus on the increase in image contrast that Source Mask Optimization (SMO) and Optical Proximity Correction (OPC) models deliver when comparing 300 fm and 200 fm light source E95% bandwidth. Using test constructs that follow current N7 / N5 ground rules and multiple pattern deconstruction rules, improvements in exposure latitude (EL), critical dimension (CD) and mask error enhancement factor (MEEF) performance are observed when SMO and OPC are optimized for 200 fm light source bandwidth when compared with the standard 300 fm bandwidth. New SMO-OPC flows will be proposed that users can follow to maximize process benefit. The predicted responses will be compared with the experimental on wafer responses of 7 nm features to lower light source bandwidth.

We use the ZEISS MultiSEM to inspect patterns on separated chips of a semiconductor wafer suited for process window characterization at imec-N10 logic node. We systematically analyze the impact of imaging parameters of the MultiSEM on quantitative metrics extracted from the images, e.g., CD repeatability and relative defect capture, and demonstrate that the MultiSEM is able to image the wafer patterns, track their variations through the process conditions of the lithography scanner, and consistently find patterning defects limiting the lithographic process window.

Non-linear overlay deformation is a well-known problem in critical lithography steps. A significant root cause is nonuniform stress, often caused by high temperature processes. Non-uniform stress in the wafer causes vertical deformation of the wafer, which can be measured by topography measurement equipment. In this case study, clustering is done on the topography data to sort each wafer into groups. Using the context information from the clustering, overlay feedback is computed on a wafer level basis. The evaluation of the approach is done with a run-to-run simulation, which allows optimization of this method and evaluation of the on-product overlay performance improvement. In the analysis, different wafer zones are distinguished to characterize the improvement potential for the different zones.

We introduce an extreme ultraviolet lithography (EUVL) mask defect review system (EMDRS) which has been developing in SAMUSNG. It applies a stand-alone high harmonic generation (HHG) EUV source as well as simple EUV optics consisting of a folding mirror and a zoneplate. The EMDRS has been continuously updated and utilized for various applications regarding defect printability in EUVL. One of the main roles of the EMDRS is to verify either mask repair or mask defect avoidance (MDA) by actinic reviews of defect images before and after the process. Using the MDA, small phase defects could be hidden below absorber patterns, but it is very challenging in case of layouts with high density patterns. The EMDRS clearly verify the success of the MDA while conventional SEM could not detect the images. In addition, we emulate images of the sub-resolution assist features (SRAFs) by the EMDRS and compared them with the wafer exposure results.

General approaches to realize higher sensitivity in optical inspection system are using shorter wavelength including UV and higher NA for objective lens. Extreme performances of imaging and illumination systems in a situation of wellmatched to each other are inevitable for the further effort on an effective optical detection of fine defects in patterned wafer. This study focused on the dark field illumination systems satisfying hi areal uniformity and concentration efficiency for the specific conditions of non-symmetric illumination area and critical slanted angle. Three different types of anamorphic dark field illumination systems namely, Far-field Areal Illumination (FAI), Near-field Areal Illumination (NAI) and Farfield Linear Illumination (FLI), are designed and evaluated by brightness, uniformity and concentration efficiency of beam intensity.

ASML AH53 and AH74 with higher odd-order diffraction light are the widely used alignment marks in industry to achieve better alignment accuracy by reducing mark damage noise. During lithography alignment process, decent diffraction light power is the basic demand. However, with the use of some high absorption (k is not equal to 0 for detective wavelength) material, it is difficult to detect the light power reflecting from the thick and opaque film stacks with these standard alignment marks. Here we optimized four alignment marks with higher odd-order diffraction power with comparing with AH53 and AH74. One software based on Fourier optical theory is built to quickly calculate the wafer quality (WQ) of different film stacks and different alignment marks. ASML SMASH alignment system can accept customized alignment mark, with new mark type configuration file. In order to demonstrate the effectiveness of new alignment marks, we put the marks on a mask and do the experiments to compare with simulation results. All the experiments results show that new designed alignment marks have larger WQs of odd-order diffraction.

Scaling of interconnect design rules in advanced nodes has been accompanied by a reducing metrology budget for BEOL process control. Traditional inline optical metrology measurements of BEOL processes rely on 1-dimensional (1D) film pads to characterize film thickness. Such pads are designed on the assumption that solid copper blocks from previous metallization layers prevent any light from penetrating through the copper, thus simplifying the effective film stack for the 1D optical model. However, the reduction of the copper thickness in each metallization layer and CMP dishing effects within the pad, have introduced undesired noise in the measurement. To resolve this challenge and to measure structures that are more representative of product, scatterometry has been proposed as an alternative measurement. Scatterometry is a diffraction based optical measurement technique using Rigorous Coupled Wave Analysis (RCWA), where light diffracted from a periodic structure is used to characterize the profile. Scatterometry measurements on 3D structures have been shown to demonstrate strong correlation to electrical resistance parameters for BEOL Etch and CMP processes. However, there is significant modeling complexity in such 3D scatterometry models, in particlar due to complexity of front-end-of-line (FEOL) and middle-of-line (MOL) structures. The accompanying measurement noise associated with such structures can contribute significant measurement error. To address the measurement noise of the 3D structures and the impact of incoming process variation, a hybrid scatterometry technique is proposed that utilizes key information from the structure to significantly reduce the measurement uncertainty of the scatterometry measurement. Hybrid metrology combines measurements from two or more metrology techniques to enable or improve the measurement of a critical parameter. In this work, the hybrid scatterometry technique is evaluated for 7nm and 14nm node BEOL measurements of interlayer dielectric (ILD) thickness, hard mask thickness and dielectric trench etch in complex 3D structures. The data obtained from the hybrid scatterometry technique demonstrates stable measurement precision, improved within wafer and wafer to wafer range, robustness in cases where 3D scatterometry measurements incur undesired shifts in the measurements, accuracy as compared to TEM and correlation to process deposition time. Process capability indicator comparisons also demonstrate improvement as compared to conventional scatterometry measurements. The results validate the suitability of the method for monitoring of production BEOL processes.

The evaluation of scatterometry for monitoring intended variations in innovative scatterometry targets that mimic nonuniformities potentially caused by multibeam Maskless Lithography (MEB-ML2) is presented. Specialized scatterometry targets consisting of lines and spaces were produced that have portions exposed using the nominal, or POR (Process of Record), dose, and portions exposed with a slightly different dose. These exposure plans created targets with different line CDs (critical dimensions). Multiple target designs were implement, each with a different combination of magnitude of CD shift and size of the region containing lines with a shifted CD. The scatterometry, or OCD (Optical Critical Dimension), spectra show clear shifts caused by the regions with shifted CD, and trends of the scatterometry results match well with trends of the estimated CD as well as the trends produced by measurements using a critical dimension scanning electron microscope (CD-SEM) system. Finally, the OCD results are correlated to the CD-SEM measurements. Taking into account resist morphology variations across the wafer, correlations between OCD and CD-SEM of the weighted average CD across the various targets are shown to be very good. Correlations are done using the rigorous TMU analysis methodology. Due to the different targeted CD values within each scatterometry structure, a new methodology for estimating the error of the CD-SEM measurements for nominally non-uniform targets is presented.

As semiconductor manufacturing continues its march towards more advanced technology nodes, it becomes increasingly important to identify and characterize design weak points, which is typically done using a combination of inline inspection data and the physical layout (or design). However, the employed methodologies have been somewhat imprecise, relying greatly on statistical techniques to signal excursions. For example, defect location error that is inherent to inspection tools prevents them from reporting the true locations of defects. Therefore, common operations such as background-based binning that are designed to identify frequently failing patterns cannot reliably identify specific weak patterns. They can only identify an approximate set of possible weak patterns, but within these sets there are many perfectly good patterns. Additionally, characterizing the failure rate of a known weak pattern based on inline inspection data also has a lot of fuzziness due to coordinate uncertainty. SEM (Scanning Electron Microscope) Review attempts to come to the rescue by capturing high resolution images of the regions surrounding the reported defect locations, but SEM images are reviewed by human operators and the weak patterns revealed in those images must be manually identified and classified. Compounding the problem is the fact that a single Review SEM image may contain multiple defective patterns and several of those patterns might not appear defective to the human eye. In this paper we describe a significantly improved methodology that brings advanced computer image processing and design-overlay techniques to better address the challenges posed by today’s leading technology nodes. Specifically, new software techniques allow the computer to analyze Review SEM images in detail, to overlay those images with reference design to detect every defect that might be present in all regions of interest within the overlaid reference design (including several classes of defects that human operators will typically miss), to obtain the exact defect location on design, to compare all defective patterns thus detected against a library of known patterns, and to classify all defective patterns as either new or known. By applying the computer to these tasks, we automate the entire process from defective pattern identification to pattern classification with high precision, and we perform this operation en masse during R & D, ramp, and volume production. By adopting the methodology, whenever a specific weak pattern is identified, we are able to run a series of characterization operations to ultimately arrive at the root cause. These characterization operations can include (a) searching all pre-existing Review SEM images for the presence of the specific weak pattern to determine whether there is any spatial (within die or within wafer) or temporal (within any particular date range, before or after a mask revision, etc.) correlation and (b) understanding the failure rate of the specific weak pattern to prioritize the urgency of the problem, (c) comparing the weak pattern against an OPC (Optical Procimity Correction) Verification report or a PWQ (Process Window Qualification)/FEM (Focus Exposure Matrix) result to assess the likelihood of it being a litho-sensitive pattern, etc. After resolving the specific weak pattern, we will categorize it as known pattern, and the engineer will move forward with discovering new weak patterns.

As device shrink, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge due to tighter overlay and focus control requirement. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. A novel technique for measuring distortion is Coherent Gradient Sensing (CGS) interferometry, which is capable of generating a high-density distortion data set of the full wafer within a time frame suitable for a high volume manufacturing (HVM) environment. In this paper, we describe the adoption of CGS (Coherent Gradient Sensing) interferometry into high volume foundry manufacturing to overcome these challenges. Leveraging this high density 3D metrology, we characterized its In-plane distortion as well as its topography capabilities applied to the full flow of an advanced foundry manufacturing. Case studies are presented that summarize the use of CGS data to reveal correlations between in-plane distortion and overlay variation as well as between topography and device yield.

As the demand of the technology node shrinks from 14nm to 7nm, the reliability of tool monitoring techniques in advanced semiconductor fabs to achieve high yield and quality becomes more critical. Tool health monitoring methods involve periodic sampling of moderately processed test wafers to detect for particles, defects, and tool stability in order to ensure proper tool health. For lithography TWINSCAN scanner tools, the requirements for overlay stability and focus control are very strict. Current scanner tool health monitoring methods include running BaseLiner to ensure proper tool stability on a periodic basis. The focus measurement on YIELDSTAR by real-time or library-based reconstruction of critical dimensions (CD) and side wall angle (SWA) has been demonstrated as an accurate metrology input to the control loop. The high accuracy and repeatability of the YIELDSTAR focus measurement provides a common reference of scanner setup and user process. In order to further improve the metrology and matching performance, Diffraction Based Focus (DBF) metrology enabling accurate, fast, and non-destructive focus acquisition, has been successfully utilized for focus monitoring/control of TWINSCAN NXT immersion scanners. The optimal DBF target was determined to have minimized dose crosstalk, dynamic precision, set-get residual, and lens aberration sensitivity. By exploiting this new measurement target design, ~80% improvement in tool-to-tool matching, >16% improvement in run-to-run mean focus stability, and >32% improvement in focus uniformity have been demonstrated compared to the previous BaseLiner methodology. Matching

When design rule is mitigating to smaller dimension, process variation requirement is tighter than ever and challenges the limits of device yield. Masks, lithography, etching and other processes have to meet very tight specifications in order to keep defect and CD within the margins of the process window. Conventionally, Inspection and metrology equipments are utilized to monitor and control wafer quality in-line. In high throughput optical inspection, nuisance and review-classification become a tedious labor intensive job in manufacturing. Certain high-resolution SEM images are taken to validate defects after optical inspection. These high resolution SEM images catch not only optical inspection highlighted point, also its surrounding patterns. However, this pattern information is not well utilized in conventional quality control method. Using this complementary design based pattern monitor not only monitors and analyzes the variation of patterns sensitivity but also reduce nuisance and highlight defective patterns or killer defects. After grouping in either single or multiple layers, systematic defects can be identified quickly in this flow. In this paper, we applied design based pattern monitor in different layers to monitor process variation impacts on all kinds of patterns. First, the contour of high resolutions SEM image is extracted and aligned to design with offset adjustment and fine alignment [1]. Second, specified pattern rules can be applied on design clip area, the same size as SEM image, and form POI (pattern of interest) areas. Third, the discrepancy of contour and design measurement at different pattern types in measurement blocks. Fourth, defective patterns are reported by discrepancy detection criteria and pattern grouping [4]. Meanwhile, reported pattern defects are ranked by number and severity by discrepancy. In this step, process sensitive high repeatable systematic defects can be identified quickly Through this design based process pattern monitor method, most of optical inspection nuisances can be filtered out at contour to design discrepancy measurement. Daily analysis results are stored at database as reference to compare with incoming data. Defective pattern library contains existing and known systematic defect patterns which help to catch and identify new pattern defects or process impacts. On the other hand, this defect pattern library provides extra valuable information for mask, pattern and defects verification, inspection care area generation, further OPC fix and process enhancement and investigation.

Process-induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget including non-uniform wafer stress. Previous studies have shown the correlation between process-induced stress and overlay and the opportunity for improvement in process control, including the use of patterned wafer geometry (PWG) metrology to reduce stress-induced overlay signatures. Key challenges of volume semiconductor manufacturing are how to improve not only the magnitude of these signatures, but also the wafer to wafer variability. This work involves a novel technique of using PWG metrology to provide improved litho-control by wafer-level grouping based on incoming process induced overlay, relevant for both 3D NAND and DRAM. Examples shown in this study are from 19 nm DRAM manufacturing.

At 28nm technology node and below, hot spot prediction and process window control across production wafers have become increasingly critical to prevent hotspots from becoming yield-limiting defects. We previously established proof of concept for a systematic approach to identify the most critical pattern locations, i.e. hotspots, in a reticle layout by computational lithography and combining process window characteristics of these patterns with across-wafer process variation data to predict where hotspots may become yield impacting defects [1,2]. The current paper establishes the impact of micro-topography on a 28nm metal layer, and its correlation with hotspot best focus variations across a production chip layout. Detailed topography measurements are obtained from an offline tool, and pattern-dependent best focus (BF) shifts are determined from litho simulations that include mask-3D effects. We also establish hotspot metrology and defect verification by SEM image contour extraction and contour analysis. This enables detection of catastrophic defects as well as quantitative characterization of pattern variability, i.e. local and global CD uniformity, across a wafer to establish hotspot defect and variability maps. Finally, we combine defect prediction and verification capabilities for process monitoring by on-product, guided hotspot metrology, i.e. with sampling locations being determined from the defect prediction model and achieved prediction accuracy (capture rate) around 75%

Multi-patterning processes have become common in the leading-edge semiconductor industry. These processes require a good patterning uniformity over the wafer while different process steps have impact. The initial lithography steps can be nearly perfect, but the CD variation after a trim process may cause CD variation after the spacer deposition. In fact, that leads to final non-uniformity of the final CD. Monitoring and controlling the individual CD parameters is not sufficient to ensure a stable process. We define a set of new KPIs, taking all contributions into account and using macro measurement data. We show that a reliable monitoring is achieved to meet the process specifications.

Device scaling has not only driven the use of measurements on more complex structures, in terms of geometry, materials, and tighter ground rules, but also the need to move away from non-patterned measurement sites to patterned ones. This is especially of concern for very thin film layers that have a high thickness dependence on structure geometry or wafer pattern factor. Although 2-dimensional (2D) sites are often found to be sufficient for process monitoring and control of very thin films, sometimes 3D sites are required to further simulate structures within the device. The measurement of film thicknesses only a few atoms thick on complex 3D sites, however, are very challenging. Apart from measuring thin films on 3D sites, there is also a critical need to measure parameters on 3D sites, which are weak and less sensitive for OCD (Optical Critical Dimension) metrology, with high accuracy and precision. Thus, state-ofthe-art methods are needed to address such metrology challenges. This work introduces the concept of Enhanced OCD which uses various methods to improve the sensitivity and reduce correlations for weak parameters in a complex measurement. This work also describes how more channels of information, when used correctly, can improve the precision and accuracy of weak, non-sensitive or complex parameters of interest.