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Majorana bound states (MBSs) can occur in Josephson junctions of conventional s-wave superconductors coupled via a strong topological insulator. In configurations of multiple line junctions meeting at a point, the criterion for the MBS to exist coincides with the presence of a fractional Josephson vortex with 2π phase winding. We investigate the dynamic stability of such vortices in arrays of tri- and quad-junctions. The existence of fractional vortices in arrays is demonstrated, but the dynamic stability is found to depend critically on the current-phase relation and the inductance. We propose the idea, and study the feasibility, of manipulating the location of the vortices in arrays by using current pulses, compatible with rapid single flux quantum technology. It is shown theoretically, using a modified resistively shunted junction model, that braiding operations can be achieved using current pulses injected from the edge of the array. It is necessary to use vortex sites with elevated critical current as traps.

Half-flux-quantum (HFQ) circuits store and propagate half-flux quanta. The basic circuit element is a 0-π SQUID, which is a superconducting quantum interference device with a conventional Josephson junction (0-junction) and a π-shifted ferromagnetic junction (π-junction). A 0-π SQUID achieves a small critical current in the absence of an external magnetic field, thus reducing power consumption. It is easy to set up 0-0-π SQUIDs with two 0-junctions and a π-junction which serves as a π phase-shifter. We simulated 0-0-π SQUID-based HFQ circuits driven by low bias voltages, referred to as LV-HFQ circuits. In these circuits, shunt resistors are not required for switching junctions because there is no hysteresis in the current–voltage characteristics of 0-0-π SQUIDs. We estimated the power consumption and maximum operating frequency of an HFQ Josephson transmission line based on 0-0-π SQUIDs. When operating at 43.5 GHz, the power dissipation of a single element composed of a 0-0-π SQUID and a bias resistor fell to about 0.165 nW when biased at 60 μV. The LV-HFQ circuit is potentially more power-efficient than all other currently available superconducting logic circuits.

This paper presents a new class of sharp-selectivity low-temperature superconducting filter that incorporates lumped element resonant couplings. Dependent on a novel synthesis approach, the proposed filter exhibits great advantages such as: (1) a very simple in-line topology (without any cross coupling), (2) extremely compact size based on lumped inductor-capacitor (LC) elements, and (3) multiple transmission zeros (TZs) independently generated and controlled (via each resonant coupling). To facilitate the physical implementation, a group of lumped element circuit models are detailed, where series LC units are adopted for both the resonators and the resonant couplings. Considering an in-line topology here, the entire filter layout is then designed by cascading the lumped models one after another. For verification, a 5th-order bandpass filter centered at 5 GHz, with 500 MHz bandwidth and 3 TZs, is designed, simulated, and tested at cryogenic temperature (4.2 K). Moreover, preliminary simulations of the presented filter in series with an on-chip rapid single-flux-quantum microwave pulse generator are discussed for superconducting quantum applications.

A vital precondition for the realization of rapid single-flux quantum (RSFQ) digital circuits with reduced critical currents of the Josephson junctions is the implementation of an efficient technique for superconductive phase dropping. In this paper, we present a novel phase shifting element consisting of a miniature superconductive ring located over a ground plane hole. Contrary to the solutions reported up to now, this topology can be simply integrated within complex digital RSFQ circuits realized with conventional fabrication technology.

A detailed design is given for a flux qubit readout using ballistic fluxons. In this scheme, fluxons propagate through an underdamped Josephson transmission line (JTL) coupled to the qubit, whose state affects the fluxon propagation time. For strong qubit–JTL coupling, and far from the symmetry point, a qubit can be measured with fidelity greater than 99% and measurement time of 4 ns. The readout circuit requires additional rapid single flux quantum (RSFQ) interface circuitry to launch and receive the delayed flux solitons. The parameters of this driver and receiver have been optimized to produce low fluxon speed at launch and impedance matching at the receiver. The delayed solitons are compared to a reference line using a detector with time resolution of better than 16 ps. Both the JTL and RSFQ interface were designed for the Nb 30 A cm^-2 process developed at VTT, Finland, with postdeposition of the Al qubit at IPHT, Germany

There is a great deal of interest in amplifiers with extremely high bandwidth, low noise and low power consumption which interface RSFQ circuits with commercial room temperature electronics or amplifying SFQ pulses. In this special application a hybrid amplifier should interface an RSFQ circuitry with a Josephson junction array quantizer chip (JA-Q) at 4.2 K. The input signal for the amplifier is generated by an RSFQ signal generator and the output signal fed-in to a Josephson array quantizer. A voltage gain of about 104 with a pattern frequency of 2 GHz for a good transfer of the SFQ pulses is required. Additionally, the JA-Q requires a high output current at low power consumption of the amplifier at the same time. Various hybrid amplifiers based on commercially available p-HEMT transistors in an embedded microwave design were designed and characterized. For the p-HEMT transistor characterization at cryogenic temperatures the biasing settings according to an optimum between voltage gain AV and low power consumption PV were determined. Thus a power consumption of PV = 2 mW and a voltage gain of about AV = 4 per stage were achieved. For a preamplifier and an amplifier concept a number of these stages were implemented in a microstrip and a coplanar transmission line design with a special matched interconnect taper towards the RSFQ components. Measurements of the amplifiers and the combination of the amplifiers and the JA-Q at 4.2 K showed their good performance without any disturbances of the quantized voltage steps.

In order to integrate superconducting qubits with rapid-single-flux-quantum (RSFQ) control circuitry, it is necessary to develop a fabrication process that fulfills at the same time the requirements of both elements: low critical current density, very low operating temperature (tens of milliKelvin) and reduced dissipation on the qubit side; high operation frequency, large stability margins, low dissipated power on the RSFQ side. For this purpose, VTT has developed a fabrication process based on Nb trilayer technology, which allows the on-chip integration of superconducting qubits and RSFQ circuits even at very low temperature. Here we present the characterization (at 4.2 K) of the process from the point of view of the Josephson devices and show that they are suitable to build integrated superconducting qubits.

The fabrication of self-shunted SNS (superconductor/normal conductor/superconductor) Josephson junctions for rapid single flux quantum (RSFQ) logic could potentially facilitate increased circuit density, as well as reduced parasitic capacitance and inductance over the currently used externally shunted SIS (superconductor/insulator/superconductor) trilayer junction process. We report the deposition, fabrication, and device characterization of Josephson junctions prepared with Nb1?yTiyN electrodes and TaxN barriers tuned near the metal?insulator transition, deposited on practical large-area oxide-buffered silicon wafers. When scaled to practical device dimensions, this type of junction is found to have an IcRn product of over 0.5?mV and a critical current (Ic) and normal resistance (Rn) of magnitudes suitable for single flux quantum digital circuits. A longer than expected normal-metal coherence length (?n) of 5.8?nm is inferred from the thickness dependence of Jc at 4.2?K for junctions fabricated using a barrier resistivity of 13?m??cm. Although not well understood and not quantitatively predicted by conventional theories, this results in a sufficiently high Ic and IcRn to make the junctions suitable for practical applications. Similar observations of unexpectedly large Josephson coupling currents in SNS junctions have been documented in other systems, particularly in cases when the barrier is near the M?I transition, and have become known as the giant proximity effect. The temperature dependence of ?n, IcRn, and Jc are also reported. For this technology to be used in practical applications, significant improvements in our fabrication process are needed as we observe large variations in Ic and Rn values across a 100?mm wafer, presumably as a result of variations in the Ta:N stoichiometry and the resulting changes in the TaxN barrier resistivity.

We propose a simple method of measuring bit error rates (BERs) for rapid single flux quantum (RSFQ) circuits operating at high frequencies. An error detector based on a SQUID current comparator, which operates without a timing clock, is employed to simplify the test system and measurements. We successfully investigated high-frequency operation of RSFQ cells that were utilized to implement our RSFQ digital-to-analogue converter for metrology applications. Sufficiently low BERs were demonstrated in the circuit operation at several tens of gigahertz.

Single flux quantum (SFQ) electronics is extremely fast and has very low on-chip power dissipation. SFQ VLSI is an excellent candidate for high-performance computing and other applications requiring extremely high-speed signal processing. Despite this, SFQ technology has generally not been accepted for system implementation. We argue that this is due, at least in part, to the use of outdated tools to produce SFQ circuits and chips. Assuming the use of tools equivalent to those employed in the semiconductor industry, we estimate the density of Josephson junctions, circuit speed, and power dissipation that could be achieved with SFQ technology. Today, CMOS lithography is at 90?65?nm with about 20 layers. Assuming equivalent technology, aggressively increasing the current density above 100?kA?cm?2 to achieve junction speeds approximately 1000?GHz, and reducing device footprints by converting device profiles from planar to vertical, one could expect to integrate about 250?M Josephson junctions cm?2 into SFQ digital circuits. This should enable circuit operation with clock frequencies above 200?GHz and place approximately 20?K gates within a radius of one clock period. As a result, complete microprocessors, including integrated memory registers, could be fabricated on a single chip.

The Multiply-Accumulate Unit (MAC) is a central component of a Successive Interference Canceller, an advanced receiver for W-CDMA base stations. A 4*4 two's complement fixed point RSFQ MAC with rounding to 5 bits has been simulated using VHDL and maximum performance is equal to 24 GMACS (giga multiple-accumulates per second). The clock distribution network has been re-designed from a linear ripple to a binary tree network in order to eliminate data dependence of the clock propagation speed and reduce number of Josephson junctions in clock lines. The 4*4 bits MAC has been designed for the HYPRES 4.5 kA/cm^2 process and its components have been experimentally tested at low frequency: the 5 bit combiner, using an exhaustive test pattern, had margins on DC bias voltage of +-18% and the 4*4 parallel multiplier had margins equal to +-2%.

This paper presents results of optimization of Multi-Chip-Module (MCM) contact pads and driver circuitry for gigabit chip-to-chip communication. Optimization has been done using 3D Electromagnetic (EM) simulations of flip-chip contacts and time domain simulations of drivers and receivers. A single optimized flip-chip contact has signal refection of less than -20 dB for up to 503 GHz bandwidth. The MCM data link with optimized SFQ driver, receivers and two MCM contact has operational margins on global bias current of +-30% at 30 Gbit/s speed and can operate at maximum 113 Gbit/s of operational speed. High bandwidth transmission requires realization of an advanced flip-chip process with small dimension of contact pads (less 30 micro meter) and small hight of bumps in the order of 2 micro meter. Current processes with about 7 micro meter hight of the bumps requires application of Double Flux Quantum (DFQ) driver. The data link with DFQ driver was also simulated. It has operational margins on global bias current of +-30% at 30 Gbit/s, however the maximum speed of operation is 61 Gbit/s. Several test structures have been designed for measurements signal re°ection, bit error rate (BER) and operational margins of the data link.

Rapid single-flux-quantum (RSFQ) technology has been proposed as control electronics for superconducting quantum bits because of the material and working temperature compatibility. In this work, we consider practical aspects of RSFQ circuit design for low noise low power operation. At the working temperature of 20 mK and operational frequency of 2 GHz, dissipated power per junction is reduced to 25 pW by using 6 νA critical current junctions available at the Hypres and VTT low Jc fabrication process. To limit phonon temperature to 30 mK, a maximum of 40 junctions can be placed on a 5 mm × 5 mm chip. Electron temperature in resistive shunts of Josephson junctions is minimized by use of cooling fins, giving minimum electron temperatures of about 150 mK for the Hypres process and 70 mK for the VTT process.

We have designed and experimentally verified a test bench for high frequency testing of Rapid Single Flux Quantum (RSFQ) circuits. This test bench uses an external tuneable clock signal that is stable in amplitude, phase and frequency. The high frequency external clock reads out the clock pattern stored in a long shift-register. The clock pattern is consequently shifted out at high speed and splitted to feed both the circuit under test and an additional shift register in the test bench for later verification at low speed. This method can be employed for reliable high speed verification of RSFQ circuit operation, with use of only low speed readout electronics. The test bench consists of 158 Josephson junctions and occupied area is 3300 * 660 (mikro meter)^2. It was experimentally verified up to 33 GHz with +- 21.7 % margins on the global bias supply current.

Highly sensitive measurement of magnetic fields can be made by analogue SQUIDs with analogue-to-digital conversion in a semiconductor environment. An alternative way is the use of digital SQUIDs consisting of superconducting digital Josephson electronics. Previously we presented a full digital SQUID device based on the bidirectional single flux quantum (SFQ) technique, which featured a very high dynamic range due to intrinsic flux compensation, a high slew rate and low complexity of the superconducting digital electronics. Analogue external feedback circuitry is replaced by the internal digital feedback. The intrinsic digital processing of measured flux makes external analogue-to-digital conversion dispensable. The remaining semiconducting electronics is reduced to a high-speed up–down counter. The whole system will be clocked by a bidirectional bias signal. The achieved tristate operation ensures a serial data output stream in the range of gigabits per second. The proper function of such a single-stage digital SQUID was recently proved by experiments. This concept of flux counting suffers intrinsically from its resolution of one flux quantum, which is not sufficient for the measurement of small magnetic fields. In this paper we present investigations on novel circuit topologies utilizing digital SQUID devices to overcome the restrictions in flux resolution without losing the dynamics advantages of a full digital SQUID device.

The application of superconducting rapid single-flux quantum (RSFQ) digital electronics for highly sensitive measurement of magnetic fields can provide significant advantages in the use of conventional analogue SQUIDs, especially in terms of operation speed and dynamic range. Furthermore, utilizing an unconventional generalized single-flux-quantum (SFQ) logic with a bidirectional operation principle allows an additional decrease in effort in superconducting electronics. Our novel fully digital SQUID based on the SFQ technique can be assumed to be operating at frequencies in the gigahertz range corresponding to slew rates of several 109 Φ0 s−1. We present first experimental results for the proper digital function as a preliminary stage for a digital SQUID magnetometer device. The measurements presented are performed for a reliable low temperature superconductor technology at liquid helium temperature; nevertheless the very low complexity of the superconducting digital circuitry holds promise as regards prospects for a working digital SQUID based on high temperature superconductor technology.

In this paper, issues related to the optimization of superconducting passive interconnects are discussed. Results of the microwave optimization of bends, via connections and crossings of superconducting microstrip lines (SMSLs) are reported. The optimum design of the SMSL cross gives more than 95% of transmission and can be well used in a two-bus cross design with up to 14 signal wires. The results have been confirmed by time-domain simulations and measurements.

We present a novel asynchronous RSFQ demultiplexer based on dual-rail information coding. The electrical scheme of the circuit is designed and optimized to maximize the margins of its elements and to improve the fabrication yield. This optimized scheme has been fabricated with the 4 µm 1 kA cm−2 Nb/Al2O3–Al/Nb technology of PTB-Braunschweig. The demultiplexer has been tested with different samples of the low-speed incoming data stream and in all cases a correct circuit functionality has been observed.

We have designed, fabricated, and tested a rapid single flux quantum (RSFQ) 1 bit arithmetic logic unit (ALU) block. The circuit consists of three DC current driven SFQ switches and a half-adder. We successfully tested the half-adder cell at clock frequency up to 20 GHz. The switches were commutating output ports of the half-adder to produce AND, OR, XOR, or ADD functions. For a high-speed test, we attached two switches at the input ports of the half-adder to control the high-speed input data by low-frequency pattern generators. The output in this measurement was an eye-diagram. Using this set-up, the circuit was successfully tested up to 20 GHz. The chip was fabricated using a standard HYPRES 1 kA cm−2 Nb Josephson junction fabrication process.

In the design of electronic applications (for example, rapid single flux quantum (RSFQ) circuits), the properties of Josephson junctions (JJs) provided by technology are the major requirement. The characteristic voltage IcRn an dt he dynamic parameter βc are non-negligibly important, bu tt he external shunted junctions are only completely described by including the parasitic inductance between the junction area and the shunt resistor. The first publications of the RSFQ circuit technique were closely followed by many studies on the dynamic influence of this inductance. It has been pointed out that no practical value of this parameter has to be taken into account in the circuit design and optimization process. The operation of RSFQ logic circuits made of high-temperature superconductors (HTS) are strongly influenced by thermal noise. Our paper contains the determination of the digital bit-error rate for all different types of JJs by using a Fokker–Planck equation for describing the influence of thermal fluctuations. Ou ra nalysis shows that the parasitic inductance cannot be neglected in terms of noise. The intrinsic shunted junctions like high current density-, SINIS- and all kinds of HTS-JJs provide the best noise immunity for a fixed temperature.

We present a scheme of a new buffered RSFQ shift register, having reversible input and output. This scheme is extended to a new dual-rail reversible buffered RSFQ shift register, suitable for asynchronous applications. Finally, a new proposal for a buffered RSFQ shift register performing both shift-left and shift-right operations is given.

A demultiplexer (DMUX) is a key subsystem of rapid single flux quantum (RSFQ) circuits and systems in practical applications. High-speed data from RSFQ circuits should be converted into sufficiently low-speed ones for transmission to and processing by room temperature electronics. We designed, fabricated and successfully tested an RSFQ DMUX based on the synchronous shift-and-dump architecture whose advantages are modularity and compactness. A 1-to-8 DMUX was implemented using our standard cell library on 1.6 kA cm−2 Nb trilayer technology. Fully functional operation was confirmed by low speed testing. Experimental bias margins were as large as ±16%. Results of average voltage measurements implied that the DMUX was operated at data rates up to 25 Gb s−1.

A set of standard rapid-single-flux-quantum logic cells has been established in order to build blocks for complex high-speed superconducting digital applications. Special emphasis has been put on the implementation with Nb and NbN technologies as well as with high-Tc superconductors. The influence of the different technological parameters on the projected performance of some basic cells is presented along with a comparative study of their margins of operation. In particular, the performance of a D-flip-flop has been studied as a function of frequency of operation for the different technologies.

Thermal noise strongly influences the operation of RSFQ (rapid single flux quantum) logic circuits made of high-temperature superconductors (HTS). In the past, the circuit design was based on fabrication yield optimization. A new theoretical study using a method of general determination of the digital bit-error rate (BER) gives hope to develop such devices with a large immunity against noise. With regard to this study the design parameters of a circuit optimized with respect to fabrication yield are far from its minimum bit-error rate. Only for temperatures close to 4 K the parameters determined for fabrication yield match the parameters obtained with BER optimization. For this reason, a new reliable technology for fabrication of HTS circuits is required. We have developed a new fabrication process to serve as a basis for a proof of this new design approach. We have calculated the bit-error rate of a newly designed RSFQ chip with realistic values derived from a test chip which has been fabricated with this new multilayer technology. The new technology contains three superconductor thin films. An inductance smaller than 0.5 pH per square has been reached by using a ground plane.

We are developing a digital-to-analog (D/A) converter based on rapid single flux quantum (RSFQ) logic circuits. Since the RSFQ D/A converter operates according to the Josephson frequency–voltage relationship, arbitrary waveforms can be synthesized with an accuracy equivalent to that of the Josephson dc voltage standard. We have examined the characteristics of magnetically coupled voltage multipliers (VMs). The VM is a key component in the RSFQ D/A converter for use in metrological applications.

We have proposed a cell-based design approach based on a binary decision diagram (BDD) for the design of rapid single flux quantum (RSFQ) logic circuits. In this design approach, any logic function can be implemented by simply embedding the limited number of basic cells. We have constructed a BDD RSFQ cell library and prepared a top-down CAD environment. In this study, we investigated the tolerance of the BDD RSFQ basic cells to the circuit parameter variations. It was found that theoretical and measured dc bias margins of the basic cells agree well if we assume appropriate parameter variations due to the fabrication process. The dependence of the dc bias margin of the circuits on the circuit size was also examined, where we have implemented a 2-bit multiplexer, a 4-bit data-driven self-timed shift register and a 1-bit ALU. The low-speed test results reveal that dc bias margin of the circuits containing several hundreds of Josephson junctions is about ±15%, whereas theoretical dc bias margin is about ±33%. This paper was presented at the 8th International Superconductive Electronics Conference, Osaka, Japan, 19–22 June 2001.

In this paper we discuss the application of rapid single flux quantum (RSFQ) superconducting digital technology for multiuser detection in wideband code division multiple access base stations. The extraordinary speed of the RSFQ circuits allows us to implement one of the most reliable types of multiuser detector, the successive interference canceller (SIC). The RSFQ SIC consists of the partial cross-correlation unit, responsible for the regeneration of the interference at the receiver and linear combinations of the partial cross-correlations using the path gains, and the iterative linear system solver, which removes the interference from the received signal. We expect that the receiver can yield a capacity gain a factor of two greater than that of a conventional receiver. This article was presented at the 8th International Superconductive Electronics Conference, Osaka, Japan, 19-22 June 2001.

We are developing an analog-to-digital converter (ADC) based on rapid single-flux quantum technology for radio-astronomic spectroscopy applications where very wide bandwidth is required and relatively small resolution is sufficient. The ADC consists of periodic-flash comparators, a demultiplexer and output drivers; and is sufficiently simple to be implemented on a single chip using a conventional 2?3 ?m Nb trilayer technology. A 2-bit ADC has been designed for operation at 16 GHz of the sampling frequency. All the subsystems of the ADC have been fabricated using standard 1.6 kA cm?2 Nb/AlOx/Nb technology and have been successfully tested.

This paper reports on the evaluation of the effective suppression parameter eff in double-barrier Josephson junctions realized in Nb-Al/Alx Oy /Al/Alx Oy /Al-Nb SINIS technology. This parameter describes the overall resistance of current flow across the interfaces within the whole structure configuration and characterizes its I C R N product attainable. By comparison with theoretical descriptions of tunnelling structures in the dirty-limit approximation, the effective suppression parameter eff has been extracted from the measured temperature dependence of the I C R N product. For SINIS junctions of a series of different wafer productions with various critical currents of the fabricated junctions, the evaluated values of eff range between 80 and 250. With reference to the proximity effect and to the possibility of removing the Al layers at the Nb electrodes, a value of eff has been deduced, which ranges between 50 and 120. This is very close to the assigned value between 10 and 20 ideally suitable for integrated circuit applications, e.g. Josephson voltage standards and rapid single flux quantum circuits.

As shown elsewhere, double-barrier SIS´IS structures (I is the tunnel barrier, S´ is a thin film with TcS´

We propose a cell-based design approach for rapid single flux quantum (RSFQ) circuits based on a binary decision diagram (BDD). The BDD is a way to represent a logical function using a directed graph which consists of binary switches having one input and two outputs. Since complex logic circuits can be implemented in the form of regular arrays of the BDD binary switches, we can use a cell-based layout methodology for the design of the RSFQ circuits. In this study, we implemented the BDD binary switches by a D2 flip-flop. In the BDD design approach we made a cell library which contains a binary switch, pulse splitters, confluence buffers and Josephson transmission lines. All cell layouts in the library have identical widths and heights, so that any logic function can be laid out by simple connection of the library cells. As a case study, we implemented a 1-bit RSFQ half-adder and a 3-bit encoder for a flash AD converter.

We have designed a 16 kbit superconducting latching/SFQ hybrid (SLASH) RAM, which enables high-frequency clock operation up to 10 GHz. The 16 kbit SLASH RAM consists of four 4 × 4 matrix arrays of 256 bit RAM blocks, block decoders, latching block drivers, latching block senses, impedance matched lines and the powering circuits. The 256 bit RAM block is composed of a 16 × 16 matrix array of vortex transitional memory cells, latching drivers, SFQ NOR decoders and latching sense circuits. We have also designed and implemented an SFQ NOR decoder that is composed of magnetically coupled multi-input OR gates and RSFQ inverters.

The output voltage of a rapid-single-flux-quantum digital-to-analog converter (RSFQ-DAC) is generated with a voltage multiplier (VM) that comprises multiple voltage mirror cells. We have demonstrated a new operation mode of a voltage mirror cell. It is a second-mode operation that doubles the input voltage, like the second-order Shapiro step. That is, a single cell works as a voltage doubler (VD). In this work, we propose a new parameter set of the VD (VD revision 1: VDr1) that improves the tolerance for multi-stage operation. Experimental results of a 16-stage VDr1 circuit are presented.

The paper reports on recent developments in a new technology process in LTS implementation to fabricate intrinsically shunted tunnel junctions. The process has been realized in SINIS multilayer thin-film technology. In various test series, circuits containing a large variety of single junctions and junction arrays of different contact areas and sizes were fabricated and measured. By variation of the oxidation parameters the fabrication process has been optimized for application in integrated circuits operating in RSFQ impulse logic. The junction parameter values realized for the critical current density range to up to about , those for the characteristic voltage to up to about . The junctions show nearly non-hysteretic current-voltage characteristics; the intra-wafer parameter spread is below 10%. The junctions realized fulfil the requirements imposed for digital RSFQ circuit operation at clock frequencies in the lower GHz frequency range.

We have designed and simulated a circuit for the experimental determination of the rate of dynamic switching errors in high-temperature superconductor RSFQ circuits. The proposal is that a series-connected pair of Josephson junctions is read out by SFQ pulses circulating in a ring-shaped Josephson transmission line at high frequency. Suitable bias currents determine the switching thresholds of the junction pair. By measuring the voltage across the transmission line, it is proposed that the occurrence of a switching error can be detected. The bit error rate can be determined from the mean time before false switching together with the SFQ circulation frequency. The circuit design allows measurements over a wide temperature range.

The operational functionality of rapid-single-flux-quantum (RSFQ) T-flipflop circuits has been experimentally investigated in the frequency range from dc up to nearly three times the characteristic frequency . The operational range found is divided into two domains different in nature. In the first domain, ranging up to frequencies of 120 GHz , correct digital operation of the device has been found. Beyond this range a second domain has been found, ranging from about 200 GHz to nearly 350 GHz, in which quasi-analogous operation of frequency dividing is suggested. Typical bias current margins are in the first domain and in the second. The circuits have been fabricated using - Al/Nb trilayer technology with externally shunted Josephson tunnel junctions of critical current densities of and smallest areas of about . The characteristic voltage is and the McCumber parameter .

The discovery of the superconductive properties of magnesium diboride enables us to attempt to produce a rapid single flux quantum (RSFQ) logic device with an operation temperature of about 20 K which can be easily reached with cryocoolers. As elevated temperatures significantly increase the probability of noise-induced errors, we examine the situation in this particular temperature range. We calculate bit-error rates (BER) due to thermal noise for a toggle flip-flop as a typical RSFQ circuit with a clock frequency of 100 GHz. For this, we consider parameter spread and noise separately and observe a very low noise-induced BER. The critical margin diminishes by a small amount only.

This paper presents a study on the merits of single flux quantum (SFQ) logic in superconducting digital electronics. With no requirements for an external RF clock source, the speed of SFQ logic circuits can exceed 100 GHz, orders of magnitude higher than latching logic circuits. Use of overdamped junctions in SFQ circuits makes this logic available for already developed high-Tc junctions. Simulations show the operation of SFQ circuits at above 10 GHz with the junctions having characteristics similar to those of YBa2Cu3O7-x/Au/YBa2Cu3O7-x planar junctions. A similar concept is applied to NbN circuits operable above 10 K. A flip-flop counter using NbN junctions with Vm (1.5 mV)=3 mV and Delta =1.9 mV to model 12 K operation has been successfully simulated up to 5 GHz. Operating margins of only 26% on MVTL shift register were obtained by simulations, which is comparable to the margins for SFQ logic circuits. A counting SFQ analogue-to-digital converter can be improved by using an output buffered quantizer.

A new generation of the Josephson digital circuits-rapid single flux quantum (RSFQ) devices-based on overdamped externally shunted high quality Nb-AlOx-Nb tunnel junctions have been designed, fabricated and experimentally investigated. All-refractory material 11-layer 5 mu m integrated technology has been successfully employed for the preparation of the RSFQ microcircuits. The T flip-flop has been demonstrated to operate properly up to clock frequencies of 100 GHz at 25% margins. The proper operation of the buffer stage for a one-directional SFQ pulse transmission at clock frequencies up to 125 GHz has been achieved. The possibilities to convert the information from the usual DC form to SFQ and vice versa have been demonstrated. An output signal in an SFQ/DC converter as high as 220 mu V has been measured. A new counter type A/D converter which includes a comparator and reversible binary counter with DC outputs has been fabricated and tested. The proposed ADC seems to be very promising for high-accuracy measurement of medium-bandwidth signals. The possibilities of creating a number of SFQ devices with outstanding parameters are discussed.

We propose an inductance-load-biasing method in order to reduce power consumption of rapid single flux quantum (SFQ) logic circuits. The main idea arises from the fact that a current source can be made of a large inductor accompanied by a large flux. In our proposal, the current source is composed of a large inductor Lb, a small resistor Rb and a small voltage source Vb. Computer simulations of inductance-load-biased Josephson transmission lines (JTLs) show that an SFQ pulse propagates correctly when Lb is large enough even if Rb is very small. In order to implement the inductance-load-biased JTL, we have made two different layouts: one uses a large bias inductance Lb of a typical stripline structure on a ground plane which occupies a rather large area; the other uses Lb in the shape of a coplanar stripline, which costs a smaller area.

We have experimentally demonstrated high-speed operation of RSFQ circuits using on-chip testing system and confirmed normal operation up to 30 GHz. The system includes high-frequency pulse generators and shift registers (SRs) serving as an interface circuit between high-speed internal signals and low-speed external signals. We adopted two ladder-type pulse generators. One generates clock pulses of 10 GHz and the other generates 25 GHz. By increasing bias currents of JTLs, clock pulses can be generated at higher frequency. By using the system, an SR and a T flip-flop (TFF) gate are examined. The circuits were fabricated by NEC's standard process based on Nb/AlOx/Nb junction technology with Jc = 2.5 kA cm-2. We optimized circuit parameters by using Monte Carlo simulation. In addition, the effect of parasitic inductances can be reduced by decreasing Ic. As a result, the systems for SR and TFF worked correctly up to 30 GHz and 27.5 GHz, respectively. The SR and TFF have wide bias margins of ±39% and ±20%, respectively. We confirmed that the bias margins of the SR are independent of operation frequency. The limits of operation frequency are thought to be much higher than 30 GHz.

We consider the time characteristics of a balanced comparator formed by two Josephson junctions connected in series. Such a decision-making junction pair is an essential component of all RSFQ cells. The analysis is performed within the framework of a simple time-dependent oscillator model. Turn-on delay and uncertainty (jitter) of comparator switching times are analysed taking into account the influence of thermal fluctuations and the finite time duration of clock pulse. Restrictions on speed performance of RSFQ cells caused by both times are considered. Some practical recommendations on the clock frequency increase are also discussed.

A rapid single-flux quantum (RSFQ) set-reset trigger circuit has been implemented using YBaCuO grain boundary junctions on an asymmetric 32 degrees Y-ZrO2 bicrystal. The circuit contains 18 Josephson junctions aligned along the grain boundary and required six film layers: a YBaCuO base electrode, two amorphous SrTiO3 insulating layers, a superconducting Pb/Au/Cr ground plane and Au/Cr wiring. It consists of two DC-to-SFQ converters, two Josephson transmission lines and an SFQ-to-DC converter. Two pulse trains, 'signal' and 'clock', were applied to change the state of the trigger from '0' to '1' and vice versa, and registered at the SFQ-to-DC: output. All experiments were performed at 4.2 K.

We designed and tested new energy-efficient single flux quantum (eSFQ) circuits. The eSFQ design approach is based on biasing logic gates via decision-making pairs (DMPs) which connect clock lines to synchronous gates. The eSFQ design of asynchronous gates is more challenging, since these gates are not clocked. We demonstrate eSFQ designs of asynchronous circuits and implemented two versions of eSFQ toggle flip-flops (eTFF) cells embedded in a synchronous shift register environment. The first design is based on the bias-free version of a TFF operating in the ballistic mode. In the second design, the TFFs dc bias is applied symmetrically, while the necessary half-quantum phase skew is achieved by magnetic flux bias, which can also be done with a pi-junction phase shifter. Surrounding shift registers are the eSFQ versions of the RSFQ shift register with two junctions per bit. In this work, we report the functional operation of these eSFQ circuits and their energy consumption.

The authors propose a new type of sampler design based on shunted junctions ( beta c=1). The sampler is to be used for the investigation of single flux quantum devices (RSFQ) employing similar junctions (Kaplunenko et al. 1989, Filippenko et al. 1991). They measure the time resolution of the sampler and delay time of the shunted Josephson junction array. The circuit was manufactured on a single chip and was DC powered. They employed Nb-AlOx-Nb tunnel junctions of 300 A m-2 critical current density and observed Josephson oscillations of the output junction at frequencies from 6 to 50 GHz. Despite a long plasma period of 20 ps the time resolution was 5 ps. The transmission line of 27 Josephson junctions (critical current 165 mu A each) demonstrated time delay of 0.5 ps mu A-1.

The novel element of the rapid single flux quantum (RSFQ) logic family-the quasi digital voltage amplifier (QDVA)-which was recently proposed theoretically, has now been designed and experimentally investigated. The QDVA can be employed both as a logic element in digital circuits and as analogue voltage amplifier. The correct operation of the SFQ doubler has been demonstrated up to the output voltage 0.5 mV and with very large margins (up to 60%). The proposed QDVA can be integrated on the same chip with a SQUID sensor; it significantly simplifies the matching circuits and seems to be very attractive for the multichannel and digital SQUID systems.

Single flux quantum (SFQ) pulses used by the elements of RSFQ logic/memory family should be transformed into the usual DC-voltage form before leaving an RSFQ chip. To provide a high output voltage level (about the gap voltage Vg) the author suggests an SFQ/DC converter using unshunted hysteresis Josephson junctions. The converter employs a DC flip-flop of a HUFFLE type. It does not require AC power supply and can easily be integrated with the RSFQ elements.

As the complexity of rapid single flux quantum (RSFQ) circuits increases, both current and power consumption of the circuits become important design criteria. Various new concepts such as inductive biasing for energy efficient RSFQ circuits and inductively coupled RSFQ cells for current recycling have been proposed to overcome increasingly severe design problems. Both of these techniques use ground plane holes to increase the inductance or coupling factor of superconducting integrated circuit wires. New design tools are consequently required to handle the new topographies. One important issue in such circuit design is the accurate calculation of networks of inductances even in the presence of finite holes in the ground plane. We show how a fast network extraction method using InductEx, which is a pre- and post-processor for the magnetoquasistatic field solver FastHenry, is used to calculate the inductances of a set of SQUIDs (superconducting quantum interference devices) with ground plane holes of different sizes. The results are compared to measurements of physical structures fabricated with the IPHT Jena 1 kA cm−2 RSFQ niobium process to verify accuracy. We then do a parameter study and derive empirical equations for fast and useful estimation of the inductance of wires surrounded by ground plane holes. We also investigate practical circuits and show excellent accuracy.

We report the first experimental demonstration of recently proposed energy-efficient single flux quantum logic, eSFQ. This logic can represent the next generation of RSFQ logic eliminating dominant static power dissipation associated with a dc bias current distribution and providing over two orders of magnitude efficiency improvement over conventional RSFQ logic. We further demonstrate that the introduction of passive phase shifters allows the reduction of dynamic power dissipation by about 20%, reaching ~0.8 aJ per bit operation. Two types of demonstration eSFQ circuits, shift registers and demultiplexers (deserializers), were implemented using the standard HYPRES 4.5 kA/cm2 fabrication process. In this paper, we present eSFQ circuit design and demonstrate the viability and performance metrics of eSFQ circuits through simulations and experimental testing., Comment: 28 Pages