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Abstract: A two-dimensional (2-D) analytical subthreshold model is developed for a graded channel double gate (DG) fully depleted SOI n-MOSFET incorporating a gate misalignment effect. The conformal mapping transformation (CMT) approach has been used to provide an accurate prediction of the surface potential, electric field, threshold voltage and subthreshold behavior of the device, considering the gate misalignment effect to be on both source and drain side. The model is applied to both uniformly doped (UD) and graded channel (GC) DG MOSFETs. The results of an analytical model agree well with 3-D simulated data obtained by ATLAS-3D device simulation software. [Copyright &y& Elsevier]

An explicit surface potential and subthreshold current model for novel Dual Metal Gate (DMG) Asymmetric Vacuum (AV) as gate dielectric Schottky Barrier (SB) Cylindrical Gate All Around (CGAA) MOSFET with the incorporation of localized charges (N f ) is developed to provide excellent immunity against threshold voltage (V th ) degradation due to hot carriers. Hot carrier induced Localized Charges (LC) either positive or negative leads to degrade the threshold of the device. The major advantage of the proposed DMG-AV-SB-CGAA MOSFET is that it mitigates the ambipolar behavior thus offering very good on current to off current ratio; and also reduces the electron temperature which leads to less hot carrier generation thus lesser degradation in V th and improved Hot Carrier reliability. The surface potential is determined for three different regions by solving 1-D Poisson’s and 2-D Laplace equation through separation of variable method to facilitate an optimal model for calculating the subthreshold drain current from Si-SiO 2 interface boundary. The developed model results are in good agreement with that of ATLAS-TCAD simulation. [ABSTRACT FROM AUTHOR]

A physics-based analytical model for Schottky Barrier (SB) Cylindrical Gate All Around (CGAA) MOSFET with high- k dielectric is presented with Evanescent Mode Analysis (EMA). The electrostatic potential is obtained using the Superposition method. An exact expression for threshold voltage and subthreshold slope is also obtained. The proposed model also includes the effect of Barrier height lowering at metal semiconductor interface along with the effect of high-k (HfO 2 ) gate stack. Diffusion current and tunneling currents are combined to evaluate the total subthreshold current. The analytical results so obtained are compared with simulated data and they are in good agreement. The proposed model of SB-CGAA device with high-k dielectric is very useful for the design and optimization for high current and improved performance. [ABSTRACT FROM AUTHOR]

Abstract: In this work an extensive study on the linearity distortion behaviour of AlGaN/GaN MISHFET is performed and compared with those of conventional HFET structures. The contribution of higher order terms in a Taylor series expansion of small signal drain current is considered by evaluating higher order transconductance coefficients. Linearity figures of merit such as input intercept power, intermodulation distortion and other higher order harmonics have been investigated for both the structures. The impact of gate biasing on the linearity is also examined. The influence of critical technology parameters such as gate length, doping density, dopant layer thickness and gate insulator thickness is investigated to optimize the MISHFET structure for better linearity characteristics. Improved linearity performance has been observed for insulated gate structure proving its superiority over conventional HFETs for RF wireless and low noise applications. The results obtained reveal that by careful optimization of technology parameters, a suitably designed MISHFET architecture is more linear than its conventional counterparts. [Copyright &y& Elsevier]

Abstract: In Single Gate HEMT (SGHEMT) shortening of gate length below 100 nm leads to reduction in Transconductance , which reduces the unloaded voltage gain of the device, thereby reducing the maximum frequency of oscillation . The main reason for this reduction in with in the Single Gate HEMT (SGHEMT) is its inability to maintain the desired channel aspect ratio (). At such a miniaturization level, not only depends on the channel depth but also on the channel thickness of the device . Moreover, the variation of may switch the device characteristics from quantum regime to classical regime . The Double Gate HEMT (DGHEMT)  has emerged as a solution for further reduction in and provides enhancements over SGHEMT by virtue of its double gate and also for same due to double heterojunctions, which virtually increases the value of . In the present work, extensive simulation work has been carried out using ATLAS device simulator  in order to study the effect of and on DGHEMT and SGHEMT. An analytical model has also been proposed for SGHEMT and DGHEMT to incorporate the effect of variation of and . [Copyright &y& Elsevier]

In this work, a physics based analytical model has been proposed for an open gate AlGaN/GaN HEMT for electrical detection of biomolecules-uricase, glucose, biotin and cytochrome -c. The proposed device is easy to fabricate and offers high sensitivity at low operating voltages as complete gate area has been used for immobilizing biomolecules. The analytical model has been developed for evaluating drain current sensitivity and threshold voltage sensitivity by considering that the gate electrode is immersed in solution of de-ionized (DI) water. Results obtained by analytical model are in good agreement with previously reported experimental data and have also been verified with simulation results. Detailed sensitivity analysis has been carried out by evaluating additional electrical parameters such as gate-source capacitance, channel potential, channel conductance and transconductance to detect the presence of biomolecules. Barrier thickness, channel width to length ratio (W/L sd) and Al composition in barrier layer have been optimized to obtain high sensitivity. The maximum drain current and threshold voltage sensitivity obtained for uricase is 3.95 × 108 and 820 mV respectively. • A physics based analytical model has been developed for detection of biomolecules using open gate AlGaN/GaN MOS-HEMT. • Due to the superior properties of AlGaN/GaN MOS-HEMT it shows high sensitivity for polar liquids. • The maximum drain current and threshold voltage sensitivity obtained for Uricase is 3.95×108 and 820mV respectively. • The proposed sensor uses open gate surface for biomolecule immobilization, therefore it is easy to fabricate. [ABSTRACT FROM AUTHOR]

Abstract This work is an extension of our previous work where the major focus was to understand the device physics and optimize its performance. In this extended work, we intend to investigate the applicability of Dielectric pocket (DP) based TFETs for low power applications. For that, firstly the device architecture is well optimized by imposing several gate and dielectric engineering techniques and thereafter the well optimized architecture is verified for analog, digital and wireless applications. Different TFET based device architectures have been examined using ATLAS simulation software. The key points citing each of the device architectures i.e. DP Hetero-Dielectric (H-D) TFET, DP Dual Material Gate (DMG) TFET and DP Dual Material Gate Hetero-Dielectric (DMG H-D) TFET with their merits and limitations for the future applications have been explained. During the analysis, it was found that DP H-D TFET outperforms other two cases and hence it has been further examined for analog applications using g m1 /I ds (transconductance versus drain current) factor. For low power oriented digital applications, parasitic capacitances and inverter circuit with resistive load was analyzed. Further, for wireless applications device linearity and distortion governing parameters have been analyzed. It was concluded that DP H-D TFETs are highly applicable to be used for upcoming energy efficient applications. Highlights • DP TFET architecture is well optimized by imposing several gate and dielectric engineering techniques. • The merits and limitations of DP H-D TFET, DP DMG TFET and DP DMG H-D TFET for the future applications have been explained. • For low power oriented digital applications, parasitic capacitances and inverter circuit with resistive load was analyzed. • For wireless applications device linearity and distortion governing parameters have been analyzed. • DP H-D TFETs are highly applicable to be used for upcoming energy efficient applications. [ABSTRACT FROM AUTHOR]

The AlGaN/GaN High Electron Mobility Transistor (HEMT) on Silicon Carbide (SiC) substrate with SiO 2 passivation is proposed in this paper. The maximum drain current of 0.8 A/mm is observed at V gs  = 0 V for gate width (W G ) = 600 μm. The breakdown voltage of device with SiO 2 passivation is compared with breakdown voltage of device with SiN passivation and it is found that the breakdown voltage improved in the device with SiO 2 passivation. The breakdown voltage of the device with SiO 2 and SiN passivation are 312 V and 287 V, respectively. Furthermore, the improvement in the breakdown voltage is observed with increase of buffer thickness. The obtained breakdown voltages are 312 V, 390 V and 412 V for buffer thickness of 2 μm, 3 μm and 5 μm, respectively. In addition to breakdown analysis, the impact of passivation on intrinsic capacitance is investigated and found that the device with SiO 2 passivation exhibits a reduction in gate-source capacitance (C SG ) and gate - to - drain capacitance (C GD ). [ABSTRACT FROM AUTHOR]

The sub-threshold model formulation of Gaussian Doped Double Gate JunctionLess (GD-DG-JL) FET including source/drain depletion length is reported in the present work under the assumption that the ungated regions are fully depleted. To provide deeper insight into the device performance, the impact of gaussian straggle, channel length, oxide and channel thickness and high-k gate dielectric has been studied using extensive TCAD device simulation. [ABSTRACT FROM AUTHOR]

In this work, an analytical drain current model for Gate and Channel Engineered RingFET (GCE-RingFET) has been developed by solving 2D-Poisson equation in cylindrical coordinates. The authenticity of proposed model for GCE-RingFET architecture has been justified by comparing the analytical results with simulation results obtained using ATLAS 3D device simulation. Performance comparison of GCE-RingFET with the conventional RingFET device architectures has been performed. Various important performance metrics such as surface potential, transfer characteristic (I ds -V gs ), I ON /I OFF ratio, Threshold voltage roll off, Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL), Trans -conductance Generation Efficiency (g m /I ds ), have been investigated. [ABSTRACT FROM AUTHOR]

In this paper, the influence of hot electron injection induced gate leakage current on the noise performance of InAlAs/InGaAs double-gate HEMT has been studied following a comprehensive analytical approach. The presence of two gates on both sides of the channel in a double-gate HEMT not only provides significant improvement in its ultra-high speed and noise performance, but is also responsible for higher gate leakage current which becomes very dominant in high field conditions. Therefore, in order to explore the reliability and potential of this device under high gate and drain bias conditions, a thorough investigation of the effect of gate leakage current induced shot noise gate current on the Minimum Noise Figure of the device has been carried out. [ABSTRACT FROM AUTHOR]

In this paper, drain current model has been formulated for Double Gate (DG) p-n-i-n Tunnel FET (TFET) using Lambert-W function. The model includes the impact of mobile charges, gate dielectric thickness (t ox ) and channel thickness (t si ) on quasi fermi level, gate threshold voltage (V TG ), onset voltage (V Gonset ) and Tunneling Barrier Width (TBW) over the entire operating range i.e. accumulation to inversion state. Important electrostatic and electrical parameters such as the effective potential (φ effective ) at the center of the channel, 2-D channel potential, electric field, energy band profile and Tunneling Barrier Width (TBW) dependent drain current have been modeled. Moreover, gate and drain bias controllability in different operating regimes has also been investigated by varying oxide thickness (t ox ), channel thickness (t si ), intrinsic channel length (L int ) and at different temperatures. Important FOMs required for analog circuit performance such as transconductance (g m ), drain conductance (g d ), output resistance (R out ), early voltage (V EA ) have also been evaluated and verified using ATLAS device simulation software. [ABSTRACT FROM AUTHOR]

An analytical model for Junctionless Accumulation Mode Surrounding Gate (JLAMSG) MOSFET is developed using superposition technique. The model incorporates source/drain and channel depletion for an accurate analysis. The device parameter dependent electrostatic center potential, drain current (I DS ) and subthreshold slope (SS) have been evaluated. The numerical simulation results using ATLAS-3D device simulator are in good agreement with the results obtained from the developed analytical model. A comparative assessment between Junctionless (JL) and Junctionless Accumulation Mode (JLAM) Surrounding Gate (SG) devices for analog/RF performance is also carried out. The superiority of JLAMSG MOSFET over Junctionless Surrounding Gate (JLSG) is discussed for Analog and RF application. [ABSTRACT FROM AUTHOR]

The performance of conventional Tunnel FETs struggling from ambipolar issues, insufficient on-current, lower transconductance value, higher delay and lower cut off frequency has been improved by introducing several material and device engineering concepts in past few years. Keeping this in view, another interesting and reliable option i.e. Dielectric Pocket TFET (featuring a dielectric pocket placement near tunneling junction) has been comprehensively and qualitatively demonstrated using ATLAS device simulator. The architecture has been explored in terms of various device electrostatic parameters such as potential, energy band profile, electron and hole concentration, electric field variation and band to band generation rate (G BTB ) near the tunneling junction where the Dielectric Pocket (DP) has been introduced. Subsequently, a detailed investigation by changing the position and dielectric constant of pocket at respective junctions has been made where DP induced variations in drain current, transconductance and parasitic capacitance have been examined. The work highlights major improvements over conventional TFET in terms of lower subthreshold swing and threshold voltage, higher drain current and transconductance, improved on-to-off current ratio, suppressed ambipolar conduction and improved dynamic power dissipation issues for low voltage analog and digital applications. [ABSTRACT FROM AUTHOR]

The present work demonstrates the investigation of T-shaped Double Gate MOSFET for analog and digital performance. The 2D analytical modeling scheme is presented using Evanescent Mode Analysis (EMA). The applicability of the proposed model has been verified using ATLAS 3D device simulation. The device exploits peaks in the electric field inside the channel (due to T-shaped gate) for better carrier transport efficiency and subsequently higher drain current and trans-conductance. The impact of dielectric constant of the void layer (due to T-shaped gate) on the electrostatic of the device has been investigated using basic electrical parameters such as: sub-threshold slope, Drain Induced Barrier Lowering DIBL, device gain and I on /I off ratio. The comparative study between T-shaped DG with the conventional DG MOSFET is also presented. [ABSTRACT FROM AUTHOR]

In this paper, a physics based model has been presented for the Cylindrical Surrounding Double Gate (CSDG) Nano-wire MOSFET. The analytical model is based on the solution of 2-D Poisson's equation in a cylindrical coordinate system using super-position technique. CSDG MOSFET is a cylindrical version of double gate MOSFET which offers maximum gate controllability over the channel. It consists of an inner gate and an outer gate. These gates render effective charge control inside the channel and also provide excellent immunity to short channel effects. Surface potential and electric field for inner and outer gate are derived. The impact of channel length on electrical characteristics of CSDG MOSFET is analysed and verified using ATLAS device simulator. The model is also extended for threshold voltage modelling using extrapolation method in strong inversion region. Drain current and transconductance are compared with conventional Cylindrical Surrounding Gate (CSG) MOSFET. The excellent electrical performance makes CSDG MOSFET promising candidates to extend CMOS scaling roadmap beyond CSG MOSFET. [ABSTRACT FROM AUTHOR]

This paper presents charge based analytical drain current and capacitance model of material engineered Cylindrical/Surrounded Gate (CGT/SGT) MOSFET with nanogap cavity region for sensor applications. Material engineered i.e. dual material gate provides improvement in Short Channel Effects (SCEs) and cylindrical shape nanogap cavity region is used for sensing of biomolecule strength. The material engineered CGT/SGT MOSFET sensor electrically detect the targeted biomolecules of different strength by change in drain current and gate capacitance. Analysis has been carried out by using unified charge control based model derived from Poisson's equation. It is shown that sensitivity of changing biomolecules strength is more in gate capacitance than the drain current. The results so obtained are in good agreement with the 3D simulated data which validate the model. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model for gate drain underlap channel Double-Gate Metal-Oxide-Semiconductor Field-Effect Transistor (DG-MOSFET) for label free electrical detection of biomolecules has been proposed. The conformal mapping technique has been used to derive the expressions for surface potential, lateral electric field, energy bands (i.e. conduction and valence band) and threshold voltage (V th ). Subsequently a full drain current model to analyze the sensitivity of the biosensor has been developed. The shift in the threshold voltage and drain current (after the biomolecules interaction with the gate underlap channel region of the MOS transistor) has been used as a sensing metric. All the characteristic trends have been verified through ATLAS (SILVACO) device simulation results. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model for Junctionless (JL) Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET) based biosensor for label free electrical detection of biomolecules like enzyme, cell, DNA etc. using the Dielectric Modulation (DM) technique has been developed. The analytical results are validated with the help of “Sentaurus” device simulation software. For the biomolecule immobilization, nanogap cavity is formed in the JL MOSFET by etching gate oxide layer from both source as well as drain end of the channel. As a result, the surface potential in the channel underneath the nanogap cavity region is affected by the neutral and charged biomolecules that binds to SiO 2 adhesion layer in the cavity. The surface potential solution is obtained by solving a 2-D Poisson’s equation assuming parabolic potential profile in the channel. The shift in threshold voltage and drain current of the device has been considered as the sensing metric for detection of biomolecules under dry environment condition. [ABSTRACT FROM AUTHOR]

Abstract: Part I of this paper dealt with the hot carrier reliability evaluation of Gate Electrode Workfunction Engineered Recessed Channel (GEWE-RC) MOSFET involving channel recession and gate electrode workfunction engineering integration onto the conventional MOSFET, using an ATLAS device simulator. It was demonstrated that with the gate stack architecture incorporated onto the GEWE-RC MOSFET and tuning of various structural design parameters such as gate length (), negative junction depth (NJD), substrate doping (), gate metal workfunction, substrate bias (), drain bias () and gate oxide permittivity (), excellent hot carrier immunity can be achieved in terms of conduction band offset, reduced electron velocity, electron temperature, hot electron injected gate current and impact ionization substrate current. This paper focuses on the analog and large signal performance metrics in terms of linearity, intermodulation distortion, device efficiency and speed-to-power dissipation design parameters. Moreover, the paper also discusses the effect of gate stack architecture and various design parameters such as , NJD, , gate metal workfunction and for different substrate () and drain to source () voltages. The work, thus, proves the effectiveness of GEWE-RC for RFICs with a higher efficiency, better linearity performance; and designing and modeling of power amplifiers. [Copyright &y& Elsevier]

Abstract: In order to achieve superior RF performance, short gate length is required for the compound semiconductor field effect transistors, but the limitation in lithography for submicrometer gate lengths leads to the formation of various metal–insulator geometries like T-gate [Sandeep R. Bahl, Jesus A. del Alamo, Physics of breakdown in InAlAs/ n+-InGaAs heterostructure field-effect transistors, IEEE Trans. Electron Devices 41 (12) (1994) 2268–2275]. These geometries are the combination of various Metal-Semiconductor (MS)/Metal–Air-Semiconductor (MAS) contacts. Moreover, field plates [S. Karmalkar, M.S. Shur, G. Simin, M. Asif Khan, Field-plate engineering for HFETs, IEEE Trans. Electron Devices 52 (2005) 2534–2540] are also being fabricated these days, mainly at the drain end (-gate) having Metal–Insulator-Semiconductor (MIS) instead of MAS contact with the intention of increasing the breakdown voltage of the device. To realize the effect of upper gate electrode in the T-gate structure and field plates, an analytical model has been proposed in the present article by dividing the whole structure into MS/MIS contact regions, applying current continuity among them and solving iteratively. The model proposed for Metal–Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) [R. Gupta, S.K. Aggarwal, M. Gupta, R.S. Gupta, Analytical model for metal insulator semiconductor high electron mobility transistor (MISHEMT) for its high frequency and high power applications, J. Semicond. Technol. Sci. 6 (3) (2006) 189–198], is equally applicable to High Electron Mobility Transistors (HEMT) and has been used to formulate this model. In this paper, various structures and geometries have been compared to anticipate the need of T-gate modeling. The effect of MIS contacts has been implemented as parasitic resistance and capacitance and has also been studied to control the middle conventional gate as in dual gate technology by applying separate voltages across it. The results obtained using the proposed analytical scheme has been compared with simulated and experimental results, to prove the validity of our model. [Copyright &y& Elsevier]

Abstract: The paper presents an accurate charge control model for a fully strained (FS), and partially relaxed (PR) lattice mismatched AlGaN/GaN HEMT, taking into consideration the effect of spontaneous and piezoelectric polarization. The model also accounts for the mobility degradation with increase in temperature, which is one of the major causes in deterioration of the driving current. By using the variation of band gap with temperature, the temperature dependence on threshold voltage, sheet carrier concentration and drain current is studied. Further, the temperature variation shows the applicability of the device in a variable thermal environment. A close agreement of calculated data with simulated/experimental data proves the validity of the model. [Copyright &y& Elsevier]

Abstract: The distortion and linearity behaviour of MOSFETs is imperative for low-noise applications and RFICs design. In this paper, an extensive study on the RF-distortion and linearity behaviour of Laterally Amalgamated DUal Material GAte Concave (L-DUMGAC) MOSFET is performed and the influence of technology variations such as gate length, negative junction depth (NJD), substrate bias, drain bias and gate material workfunction is explored using ATLAS device simulator. Simulation results reveal that L-DUMGAC MOSFET significantly enhances the linearity and intermodulation distortion performance in terms of figure of merit (FOM) metrics: , , IIP3, IMD3 and higher order transconductance coefficients: gm1, gm2, gm3, proving its efficacy for RFIC design. The work, thus, optimize the device’s bias point for RFICs with higher efficiency and better linearity performance. [Copyright &y& Elsevier]

Abstract: A two-dimensional (2-D) analytical model for a Dual Material Gate (DMG) AlGaN/GaN High Electron Mobility Transistor (HEMT) has been developed to demonstrate the unique attributes of this device structure in suppressing short channel effects (SCEs). The model accurately predicts the channel potential, electric field variation along the channel, and sub-threshold drain current, taking into account the effect of lengths of the two gate metals, their work functions, barrier layer thicknesses, and applied drain biases. It is seen that the SCEs and hot carrier effects in DMG AlGaN/GaN HEMT are suppressed due to the work function difference of the two metal gates, thereby screening the drain potential variations by the gate near the drain. Besides, a more uniform electric field along the channel leads to improved carrier transport efficiency. The accuracy of the results obtained from our analytical model has been verified using ATLAS device simulations. [Copyright &y& Elsevier]

Numerical assessment of Dual-Gate AlGaN/GaN MISHEMT have been presented in this paper. Analytical model has been developed and the various parameters extracted are surface potential, electric field and threshold voltage for different device specifications. Threshold voltage of nearly 0.15 V has been computed which is nearly same to that of simulated Dual-Gate MISHEMT. Simulations have been performed using ATLAS TCAD tool. Dual-Gate MISHEMT with different gate dielectric materials such as Si 3 N 4 and gate stack combinations like HfO 2 /Al 2 O 3 has been analyzed. From the results it has been inferred that at higher temperature, drain current and transconductance reduces due to lower electron sheet concentration. Different combinations of gate biases (applied at the second gate i.e. Gate 2 presented near the drain side) has been used for optimizing the device parameter for better switching performance. For DG-MISHEMT with barrier thickness of 22 nm (both the gates connected together), I ON /I OFF ratio reduces from 109 to 106 for high temperature (upto 423 K) due to reduced sheet carrier concentration. For inductance load, output drain voltage exhibits voltage range of 9.2V/2.3V for gate pulse of -8V/+2V with 30% duty cycle. Also, it is seen that as barrier thickness is varied from 18 nm to 30 nm, I OFF increases and results in reduced output drain voltages. Performance of Single Gate and Double Gate MISHEMTs has also been compared for DC-to DC converter using inductance load circuit. • Analytical model for Dual-Gate AlGaN/GaN MISHEMT. • Temperature based investigation upto 500K for Dual-Gate AlGaN/GaN MISHEMT. • Effect of barrier thickness on the I ON /I OFF ratio has been investigated. • DC-to-DC converter using Dual-Gate AlGaN/GaN MISHEMT and inductor load. [ABSTRACT FROM AUTHOR]

In this paper, effect of gamma radiation on SOI-based Tunnel Field Effect Transistor and its application as radiation dosimeter has been investigated. Throughout the paper, the exhaustive simulations have been carried out in order to investigate the generation of the electrons and holes in the oxide region and to anticipate the characteristics of the device from subthreshold region to strong accumulation/inversion region. It is found that under the radiation environment, the radiation induced degradation in threshold voltage shift and interface trap charge could not be ignored. It is concluded that the impact of radiation is visible in the subthreshold region of the drain current than on-state of drain current. Moreover, the radiation characteristics of SOI TFET have been compared with SOI MOSFET to assess its application as a dosimeter. In order to obtain the radiation characteristics of the SOI TFET, Gamma radiation model of sentaurus TCAD has been used. • Impact of gamma radiation on SOI TFET is investigated using gamma radiation model of sentaurus TCAD. • Impact of radiation is more visible in the subthreshold region than in on-state of drain characteristics. • The magnitude of threshold voltage shift in SOI TFET is order of mV. • The electrical characteristics of SOI TFET have been compared with SOI MOSFET. [ABSTRACT FROM AUTHOR]