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III-nitride heterostructure-based metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs), compared with Schottky and p-GaN gate HEMTs, have demonstrated significant potential in the next-generation high-power electronic devices due to their exceptional gate reliability. This study presents a comprehensive investigation of threshold voltage (VTH) instability in III-nitride heterostructure-based MIS-HEMTs, with a specific emphasis on the interfaces of the multi-heterostructures. Two widely studied amorphous materials, namely, Al2O3 and SiNx, have been extensively examined as primary gate insulators in GaN-based MIS-HEMTs. To efficiently remove native oxides from the (Al)GaN surface, a novel in situ high-temperature remote plasma pretreatment (RPP) technique has been developed. This technique involves sequential application of NH3/N2 plasmas on the (Al)GaN surface before depositing the gate insulators using plasma-enhanced atomic layer deposition. The remarkable RPP process has proven to be a highly effective method for revealing atomic steps on the GaN surface, irrespective of whether the surface has undergone oxidation or etching processes. To further enhance the interface quality and potentially reduce bulk traps in the gate insulator, optimization of deposition temperature and post-deposition annealing conditions have been explored. Additionally, an electron-blocking layer, such as SiON, is incorporated into the MIS-HEMTs to prevent electron injection into bulk traps within the insulator. Novel characterization techniques including constant-capacitance and isothermal-mode deep-level transient spectroscopy have also been developed to explore the failure mechanisms in MIS-HEMTs. These techniques allow for the differentiation between bulk traps in the GaN epitaxy and those present within the gate insulators. This in-depth physical understanding provides valuable insights into the sources of failure in GaN-based MIS-HEMTs. [ABSTRACT FROM AUTHOR]

Ultrathin oxides (UOs) and ultrathin nitrides (UNs) play a crucial role in forming lattice-mismatched semiconductor heterostructures that are fabricated by using semiconducting grafting approach. The grafting approach has shown its great potential to realize GaN-based heterojunction bipolar transistors by fulfilling the missing high-performance p-type nitrides with other p-type semiconductors. A handful of UO and UN dielectrics readily available by atomic layer deposition (ALD) satisfy the requirements of double-sided surface passivation and quantum tunneling for semiconductor grafting. Due to the states existing between the UO or UN conduction band and that of the GaN, the ALD deposited UO or UN layer can generate significant effects on the surface band-bending of GaN. Understanding the band parameters of the interface between UO or UN and c-plane Ga-face GaN can guide the selection of interfacial dielectrics for grafted GaN-based devices. In this study, we performed x-ray photoelectron spectroscopy measurements to obtain the band-bending properties on c-plane, Ga-face GaN samples coated by different ALD cycles of ultrathin-HfO2 or ultrathin AlN. The valence band spectra of GaN coated with ultrathin-ALD–Al2O3, ALD–HfO2, or PEALD–AlN/ALD–Al2O3 were further analyzed to calculate the valence and conduction band offsets between the ALD dielectrics and the Ga-face GaN under different thicknesses and post-deposition annealing conditions of the dielectrics. [ABSTRACT FROM AUTHOR]

In this work, we manifest that the epitaxial structure for p-GaN gate high-electron-mobility transistor is a versatile platform to develop electronics for operating in an extremely wide temperature range (X-WTR) from 2 to 675 K, with comprehensive X-WTR studies on device operation and circuit behaviors. The key enabler for the high-temperature operation is the wide bandgap that substantially suppresses the thermal excitation of the intrinsic carrier. However, for the low-temperature side, the two-dimensional electron and hole gas (2DEG and 2DHG) channels at the heterojunctions are formed by the temperature-insensitive polarization fields, which free the carriers from freezing out. The monolithically integrated GaN n-FET, p-FET, and the resultant complementary circuits are, therefore, shown to operate in X-WTR. [ABSTRACT FROM AUTHOR]

In this work, AlN polarization-enhancement interlayer (AlN-PEL) is adopted to enhance two-dimensional hole gas (2DHG) density in a p-GaN/AlN-PEL(∼2 nm)/AlGaN(<6 nm)/GaN heterostructure, aiming at monolithic integration of p/n-channel field effect transistors (p-FETs) on GaN-on-Si substrate. Owing to the strong built-in polarization of the AlN-PEL, high density 2DHG over 2.3 × 1013 cm−2 with good immunity to thermal freeze out effect is realized. Assisted by a two-step gate trench etching process, enhancement-mode (E-mode) buried-channel GaN p-FETs with temperature independent ON-resistance RON, and ON/OFF current ratio ION/IOFF (>108), have been fabricated. The fabricated p-FETs also deliver thermally stable subthreshold swing as well as threshold voltage Vth, and smaller Vth shift than that of p-FETs without the AlN-PEL, which is primarily due to enhanced 2DHG confinement by the AlN-PEL. The proposed structure is an attractive platform for monolithic integration of GaN-based logic and power devices for cryogenic applications as low as 10 K. [ABSTRACT FROM AUTHOR]

The p-GaN/AlGaN/GaN heterostructure, predominantly epitaxially grown on large-scale silicon wafers, has been widely used for producing consumer power switching devices and recently manifested favorable for developing GaN-based complementary devices and circuits. This work investigates the hole distribution and transport in this structure based on wide-temperature-range (20–600 K) Hall measurements and TCAD simulations. It is revealed that the p-channel thereof is composed of the bulk holes in the p-GaN and the two-dimensional hole gas (2DHG) at the p-GaN/AlGaN interface, and both substantially contribute to the lateral p-type conduction at room temperature. Their complementary temperature responses lead to conductivity enhancement at both high- and low-temperature regimes. The high-density (1.2 × 1013 cm−2) 2DHG is formed owing to the polarization-induced potential well and the ionization of the Mg acceptors that thermally diffused into the barrier during the epi-growth. Such ionized Mg acceptors would partially deplete the two-dimensional electron gas (2DEG) at the access region in the n-channel side where the p-GaN is removed and result in a trade-off between the carrier density of 2DHG and 2DEG. [ABSTRACT FROM AUTHOR]

A normally-off SiC-JFET/GaN-HEMT cascode device is recently proposed, featuring a cascode configuration that incorporates a high-voltage (HV, e.g., 1200 V) silicon-carbide (SiC) junction field effect transistor (JFET) delivering the HV blocking capability and a low-voltage (LV) enhanced-mode (E-mode) gallium-nitride (GaN) high electron mobility transistor (HEMT) providing the normally-off gate control. This all-wide-bandgap device exhibits superior thermal stability and high switching speed compared to its counterparts, e.g., the SiC/Si cascode device. In this article, we study short-circuit (SC) characteristics of a 1200-V/80-mΩ SiC/GaN cascode device by considering the interactions between the SiC and GaN devices. The single-event SC withstand time (SCWT) of the demonstrated SiC/GaN cascode device is tested to be ∼3 μs under a dc-bus voltage (Vdc) of 600 V when the turn-on gate voltage (VG-on) is set to 5 V. The SC failure occurs due to the formation of hot spots induced by thermal-runaway leakage currents inside the SiC JFET. The SCWT of the cascode device could be improved by applying a moderate VG-on (e.g., SCWT = ∼6.5 μs at VG-on = 3.5 V under v dc = 600 V) without affecting the on-state resistance (r on). However, it is identified that current oscillations tend to be triggered during the SC period when VG-on is too low (e.g., lower than 3 V). The oscillation behavior is attributed to the energy stored in the interconnection parts between the SiC and GaN devices. The harmful oscillations could be suppressed by applying higher VG-on, which drives the SiC JFET into low-transconductance mode by modulating the drain-to-source voltage (VDS-G) of the LV GaN HEMT. [ABSTRACT FROM AUTHOR]

A GaN on engineered bulk silicon (GaN-on-EBUS) power IC platform featuring an industry-standard 200-V GaN power HEMT epi-structure has been recently demonstrated, showing effective isolation and crosstalk suppression between the high-side (HS) and low-side (LS) GaN transistors in half-bridge configuration. In this work, we scale up the vertical breakdown voltage (BV) of the GaN film on the EBUS substrate to be over 600 V. Meanwhile, the built-in back-to-back PN junctions along the trench created in the Si substrate are employed to provide an overvoltage-protection scheme through their intrinsic avalanche capability for the overlaying GaN half-bridge circuit. [ABSTRACT FROM AUTHOR]

${p}$ -channel GaN field-effect transistors (FETs) with a SiNx/GaON gate stack have been demonstrated with enhanced stability within a wide range of voltage bias and temperature. In this letter, the gate leakage characteristics and reliability of this unconventional staggered gate stack are investigated. At relatively low gate voltages, the gate current is suppressed owing to the buried-channel structure and the presence of GaON that presents an effective hole barrier. With more negative gate biases, the gate leakage was found to be dominated by the transport of holes that spillover from the ${p}$ -channel through the SiNx via Poole-Frenkel emission. Based on this gate leakage mechanism at large gate bias, $\sqrt {{\mathrm {E}}} $ model was used for gate lifetime prediction. The maximum applicable ON-state gate voltage of −7.3 V is obtained for a 10-year lifetime with a 1% gate failure rate. [ABSTRACT FROM AUTHOR]

Hot electrons with high kinetic energy could be generated in the channel of GaN high-electron-mobility transistors (HEMTs) during hard switching operation. Those “lucky” hot electrons scattered to the vulnerable interface between the passivation and barrier layers could bombard the interface region and create new defects that would lead to degradation of the dynamic on-resistance (${R}_{ON}$) after long-term operations. In this work, we propose a solution to the hot-electron induced device degradation through channel engineering, i.e., deploying a double-channel structure in place of the conventional single-channel structure in ${p}$ -GaN gate HEMTs. It is revealed that hot electrons are mostly generated in the lower channel and thus the additional scattering interface can effectively deter the hot electrons from reaching the vulnerable surface. Dynamic ${R}_{ON}$ degradation induced by long-term stresses at “semi-on” states is shown to be substantially suppressed in the ${p}$ -GaN gate HEMT with the double-channel structure. [ABSTRACT FROM AUTHOR]

With a switching drain bias, the gate reliability of Schottky-type ${p}$ -GaN gate high-electron-mobility transistors (HEMTs) under AC positive gate bias stress has been systematically investigated. The mean-time-to-failure (MTTF) under such application-relevant stress is found to be prolonged compared to that extracted from static and AC gate bias stress tests with the absence of a switching drain bias and exhibits positive coefficients with frequency and OFF-state drain bias (${V} _{\text {DSQ}}$). Such results can be explained by the drain-induced hole insufficiency in the gate stack at large ${V} _{\text {DSQ}}$ , a physical mechanism that results in elevated energy band at ON-state when ${V} _{\text {DSQ}}$ is just switched to low voltage. This non-equilibrium transient status could suppress injection of electrons from the 2DEG channel to the ${p}$ -GaN gate, which in turn substantially weakens the hot-electron’s generation in the depleted ${p}$ -GaN layer and the subsequent bombardment to the gate-metal/ ${p}$ -GaN interface, and thus prolongs the gate lifetime. [ABSTRACT FROM AUTHOR]

The rat surgical anterior cruciate ligament transection (ACLT) model is commonly used to investigate intra‐articular osteoarthritis (OA) therapies, and histological assessment is often the primary outcome measure. However, histological changes do not always correlate well with clinical outcomes. Therefore, this study evaluated functional outcomes in the rat surgical ACLT model and compared intra‐articular injection volumes ranging from 20 to 50 μl. Unilateral ACLT was surgically induced and static weight‐bearing, mechanical allodynia, motor function, and gait were assessed in four groups of male, Sprague‐Dawley rats (n = 6 per group). Intra‐articular injections of 20 µl Dulbecco's phosphate‐buffered saline (DPBS), 50 µl DPBS, or 50 µl of synthetic biomimetic boundary lubricant were administered once weekly for 3 weeks postoperatively. Structural changes were evaluated histologically at 20 weeks. Rat cadaver knees were injected with 20, 30, 40, or 50 µl of gadolinium solutions and were imaged using magnetic resonance imaging (MRI). Static weight‐bearing, mechanical allodynia, and gait parameters in ACLT groups revealed differences from baseline and naïve controls for 4 weeks post‐ACLT; however, these differences did not persist beyond 6 weeks. Different intra‐articular DPBS injection volumes did not result in functional or histological changes; however, peri‐articular leakage was documented via MRI following 50, 40, and 30 µl but not 20 µl gadolinium injections. Statement of clinical significance: Differences in functional parameters were predominantly restricted to early, postoperative changes in the rat surgical ACLT model despite evidence of moderate histologic OA at 20 weeks. Injection volumes of 20–30 µl are more appropriate for investigating intra‐articular therapies in the rat knee. [ABSTRACT FROM AUTHOR]

A 650-V/84-mΩ normally-off GaN/SiC cascode device is demonstrated with systematic static and dynamic characterizations. The cascode device features a low-voltage enhancement-mode (E-mode) gallium nitride (GaN) high electron mobility transistor (HEMT) to enable normally-off gate control, and a 650-V normally-on silicon carbide (SiC) JFET provides the high-voltage blocking capability. The GaN/SiC cascode device exhibits many application-desired behaviors, including reverse conduction capability, avalanche breakdown capability, thermally stable threshold voltage, low input/output capacitances, no dynamic RON degradation, and negligible dynamic VTH shift. In addition, a customized double-pulse test board is built to evaluate the switching performance of this cascode device and other 650-V SiC-based power devices. This cascode device adopting low-voltage GaN HEMT has low QG×RON and exhibits excellent switching performance. The switching losses (EON and EOFF) are much smaller than that of the 650-V Si/SiC cascode device and comparable to that of the state-of-the-art 650-V SiC MOSFETs. [ABSTRACT FROM AUTHOR]

A cost-effective engineered bulk silicon (EBUS) substrate technology is presented, featuring p-n junction implemented on bulk Si substrates using mainstream ion implantation and thermal annealing processes. Standard p-GaN/AlGaN/GaN heterostructures are successfully grown on the EBUS substrate and used to fabricate 200-V enhancement-mode p-GaN gate HEMTs. By creating deep trenches in the EBUS substrate to isolate the local P+ silicon regions underneath the high-side (HS) and low-side (LS) power switches, adverse effects (e.g., back-gating and dynamic ON-resistance degradation) in the use of conventional bulk Si substrate are all eliminated. The mechanism of crosstalk suppression in the GaN-on-EBUS platform is revealed in comparison with conventional GaN-on-Si platform and verified by a series of designed tests. [ABSTRACT FROM AUTHOR]

The high-speed superiority of GaN power devices with silicon-based peripheral circuits is not yet fully leveraged, mainly due to the parasitic inductance of interconnections. In this article, we demonstrate a GaN-based gate driver with an overcurrent (OC) protection circuit and an undervoltage lockout (UVLO) circuit on a p-GaN gate power HEMT platform. The gate driver features a rail-to-rail output voltage, suppressed gate ringing, and tunable driving speed, all of which are highly desired in high-efficiency and high-speed GaN power systems. To offer timely but reliable protections, the OC protection and UVLO circuit are designed with reference to the switching speed and the threshold voltage of GaN power devices. The OC protection is implemented with a separated sensing branch and blanking time controller, and the response time to an OC event is reduced to 10 ns after the blanking time. The UVLO circuit has a fixed hysteresis of 0.5 V, and its threshold voltage is especially tailored for the GaN integrated circuits. [ABSTRACT FROM AUTHOR]

Although the gallium nitride (GaN) high-electron-mobility transistor/silicon carbide (SiC) junction field-effect transistor (JFET) cascode device exhibits certain performance advantages over the SiC metal–oxide–semiconductor field-effect transistor (MOSFET), its robustness in harsh operating conditions is unknown. In this work, the short-circuit (SC) robustness of 650-V GaN/SiC cascode devices is characterized, analyzed, and compared with that of several mainstream SiC MOSFETs. GaN/SiC cascode devices exhibit competitive SC capability. Different failure modes are observed: thermal runaway in the SiC JFET of the cascode device and gate-to-source breakdown in the SiC MOSFET. The difference is associated with the configuration of the dielectric above SiC in the JFET and the source pad layout. According to the waveforms in SC events, failure spots, and thermal simulation results, a thermal runaway in the SiC JFET is attributed to the positive feedback between the drain leakage current and the junction temperature in the local area (hotspot) without the source pad on the top. The SC withstand time of the cascode device can be extended by reduction of the active area without the source pad. [ABSTRACT FROM AUTHOR]

In this article, the impacts of the off-state gate bias (VGS,OFF) on dynamic on-resistance (RON) are systematically investigated in commercial Schottky-type p-GaN Gate high-electron-mobility transistors. Double-pulse tester and pulsed I–V system are adopted to evaluate the dynamic RON with various off-state gate and drain bias (VDS,OFF) under hard- and soft-switching conditions. More negative VGS,OFF can aggravate the dynamic RON degradation under both soft- and hard-switching, especially when switching with a high VDS,OFF. The impacts of VGS,OFF on switching transients and off-state stress are investigated separately to reveal the underlying mechanisms, which are found to be associated with the generation and movements of holes. The off-state gate bias of the voltage-driving scheme needs to be carefully considered according to the identified mechanisms in terms of dynamic on-resistance degradation. [ABSTRACT FROM AUTHOR]

A tunnel-oxide-free GaN-based non-volatile memory (NVM) device is proposed to untangle the trilemma among speed, retention, and endurance in the implementation of conventional NVM. The program and erase (P/E) are based on bipolar charge injection controlled by individual junction barriers, whereas the data retention relies on bipolar charge trapping in an interfacial charge storage layer. The wide bandgap energy of GaN allows the formation of deep-level traps at a dielectric/GaN interface and high junction barriers in GaN, both of which benefit long-term retention. As such, the GaN-based NVM device could get rid of the tunnel oxide, thereby enabling faster P/E processes and facilitating to decouple the enhancement of endurance from that of speed and retention. The proposed device demonstrates a P/E time of 100 ns, endurance over 106 cycles, and long retention time. [ABSTRACT FROM AUTHOR]

Enhancement-mode (E-mode) p-channel gallium nitride (GaN) field-effect transistors (p-FETs) are essential components for GaN-based complementary logic circuits. For the ease of integration with n-FETs, they could be fabricated on the commercial p-GaN gate high-electron-mobility-transistor (HEMT) platform, on which the two-dimensional electron gas at the AlGaN/GaN hetero-interface is completely depleted in as-grown epi-structures. However, under the gated region where p-GaN is recessed and depleted at thermal equilibrium, a parasitic electron channel (PEC) could appear at the AlGaN/GaN interface. This Letter reports experimental investigations on the PEC with specifically designed structures, confirming that the PEC does exist but imposes limited impacts on electrical characteristics of p-FETs. When connected with an external contact, the PEC could act as a back gate to modulate the overlaying p-channel. If isolated from external contacts, which is the case of p-FETs under normal operations, electrons in the PEC would redistribute under the active region of p-FETs in the horizontal direction (i.e., parallel to the surface) under different biases but are mostly confined near the AlGaN/GaN interface in the vertical direction (i.e., perpendicular to the surface). [ABSTRACT FROM AUTHOR]

We report GaN high-electron-mobility transistors (HEMTs) with a thick (7.7 µm) GaN buffer on a Czochralski low resistivity Si (LRS) substrate. The GaN HEMTs exhibit high performance for both radio-frequency (RF) amplification and power conversion. The thick GaN buffer was grown by means of vacancy engineering, delivering a low dislocation density of ∼1.6 × 108 cm−2, contributing to suppressed RF signal coupling to the lossy Si substrate and a high vertical voltage blocking capability. For RF performance, GaN HEMTs with a 650 nm gate exhibit an fT/fMAX value of 25.1/32.3 GHz and a maximum output power POUT of 2.2 W/mm at 4 GHz with a drain voltage VDS of 20 V, which is comparable with the performance of RF GaN HEMTs on a high-resistivity silicon substrate without the existence of the field plate. For power performance, the vertical breakdown voltage of the wafer is 1160 V, and the three-terminal lateral breakdown voltage is 885 V in a GaN HEMT with a gate-to-drain distance of 8 µm. The thick GaN layer on the LRS substrate scheme thus provides a compelling platform for monolithic integration of high-performance RF devices and high-voltage power devices. [ABSTRACT FROM AUTHOR]

In this work, a deliberate etching-based top-down approach is proposed to fabricate the GaN nanorod (NR) Schottky barrier diode (SBD). As a key step during the fabrication, the impact of the wet-etching process on device performance is systematically studied. By virtue of the reduced surface states at the sidewall, the performance of NR SBD with the wet-etching process is substantially improved, delivering a forward turn-on voltage of 0.65 V, a current density of ∼10 kA/cm2 at 3 V, an ideality factor of 1.03, an ON/OFF current ratio of ∼1010, and no severe current collapse, along with a reverse breakdown voltage of 772 V. [ABSTRACT FROM AUTHOR]

This article was originally published online on 27 December 2023 with an error in the affiliation. The affiliation appears correct above. All online versions of this article were corrected on 4 April 2024.By Yingjie Wang; Sen Huang; Qimeng Jiang; Xinhua Wang; Zhongchen Ji; Jie Fan; Haibo Yin; Ke Wei; Xinyu Liu; Qian Sun and Kevin J. ChenReported by Author; Author; Author; Author; Author; Author; Author; Author; Author; Author; Author [Extracted from the article]

Recently, a GaN reverse-conducting high-electron-mobility transistor (RC-HEMT) has been demonstrated. The RC-HEMT features built-in distributive Schottky contacts, which provide a low-loss freewheeling path. The RC-HEMT offers the same functionality as an HEMT/Schottky barrier diode (SBD) pair, but consumes much less chip area, thus its ${R}_{ \mathrm{\scriptscriptstyle ON}}$ (ON-resistance $\times $ total device width) is significantly reduced. Theoretically, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT can approach that of an HEMT. In practice, due to certain geometry limitations, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of an RC-HEMT lies between an HEMT/SBD pair and a single HEMT. This work investigates the factors that influence ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT using both experimental measurements and numerical simulations. It is found that ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT is strongly affected by the geometry of the source and channel regions, where HEMT sections and SBD sections are interdigitally distributed. With coarse patterning of these regions, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT is close to the HEMT/SBD pair. Through proper geometry scaling, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of RC-HEMT is reduced and approaches that of HEMT. [ABSTRACT FROM AUTHOR]

The short circuit (SC) behavior of a newly developed GaN-HEMT/SiC-JFET cascode device is investigated in this work. The reverse leakage current through the drain-side PN junction (IR) of the SiC JFET under SC conditions is measured simultaneously during the SC event. IR of the SiC JFET increases to 6.4 A at the end of a 5-μs nondestructive SC pulse. The increase of IR during the SC pulse induces a turning point in the SC current waveform and a dramatic negative threshold voltage shift (>30 V) in the SiC JEFT, resulting in high transient drain-to-source voltage in the GaN HEMT. The underlying mechanism is associated with the increase of local potential in the P-type layer of the SiC JFET with inevitable spread resistance (RSPD). It is suggested that reducing RSPD can improve SC capability and high IR should be considered in SC failure mechanism analysis and the design of external gate resistance of the SiC JFET. [ABSTRACT FROM AUTHOR]

GaN ${p}$ -channel field-effect transistors (${p}$ -FETs) are essential components for implementing the energy-efficient complementary logic circuitry for monolithic GaN power integration. This letter reports the threshold voltage (${V}_{\mathrm {TH}}$) instability of ${p}$ -channel GaN MOSFETs with Al2O3 as the gate dielectric. When the gate-to-source bias sweeps toward the negative direction, the ${V}_{\mathrm {TH}}$ exhibits a shift toward more negative values. The impacts of such ${V}_{\mathrm {TH}}$ instability on GaN complementary logic circuits are characterized using logic inverters and ring oscillators. It is shown that impacts on circuit functions are limited with an operating voltage swing below 5 V. However, the propagation delay could be gradually prolonged, as a result of the drifting ${V}_{\mathrm {TH}}$. [ABSTRACT FROM AUTHOR]

Background: Anaplastic thyroid cancer (ATC) is a rare cancer with poor prognosis and few treatment options. The objective of this study was to investigate new immune-associated therapeutic targets by identifying ATC-derived, human leukocyte antigen (HLA) class II-presenting peptides. One protein that generated multiple peptides in ATC was chondroitin sulfate-proteoglycan-4 (CSPG4), a transmembrane proteoglycan with increased expression in multiple aggressive cancers, but not yet investigated in ATC. Methods: We applied autologous peripheral blood T cells to ATC patient-derived xenografted mice to examine whether ATC induces a tumor-specific T cell response. We then identified peptide antigens eluted from the HLA-DQ complex in ATC patient-derived cells using mass spectrometry, detecting abundant CSPG4-derived peptides specific to the ATC sample. Next, we analyzed the surface expression level of CSPG4 in thyroid cancer cell lines and primary cell culture using flow cytometry. In addition, we used immunohistochemistry to compare the expression level and localization of the CSPG4 protein in ATC, papillary thyroid cancer, and normal thyroid tissue. We then investigated the correlation between CSPG4 expression and clinicopathological features of patients with thyroid cancer. Results: We found that ATC tissue had a high level of HLA-DQ expression and that the patient's CD4+ T cells showed activation when exposed to ATC. By eluting the HLA-DQ complex of ATC tissue, we found that CSPG4 generated one of the most abundant and specific peptides. CSPG4 expression at the cell surface of thyroid cancer was also significantly high when determined by flow cytometry, with the majority of ATC cell lines exhibiting ∼10-fold higher mean fluorescence intensity. Furthermore, most ATC patient cases expressed CSPG4 in the cytoplasm or membrane of the tumor cells. CSPG4 expression was correlated with tumor size, extrathyroidal extension, and intercellular adhesion molecule-1 (ICAM-1) circumferential expression. CSPG4 mRNA overexpression was associated with worse overall survival in patients with ATC and poorly differentiated thyroid cancer. Conclusions: CSPG4 expression is significantly elevated in aggressive thyroid cancers, with a strong correlation with a poor prognosis. The vast number of HLA-DQ eluted CSPG4 peptides was identified in ATC, demonstrating the potential of CSPG4 as a novel immunotherapeutic target for ATC. [ABSTRACT FROM AUTHOR]

Short circuit (SC) capability of 650-V Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) under single and repetitive tests is characterized in this article. The investigated devices exhibit strong capability under a single SC test, but weak capability under repetitive SC tests with a bus voltage of 400 V and a gate drive voltage of 6 V. The failure mechanism under repetitive SC tests is revealed through electrothermal simulation and microscale failure spot analysis. Thermal fatigue cracks are formed due to the high temperature spike and local temperature fluctuations in the narrow GaN channel and buffer layers, leading to weak repetitive SC capability. The unique heat confinement effect in the GaN layer plays an important role in the formation of high temperature spike and fatigue cracks. The withstand time in a single SC test is several hundred microseconds due to fast drain current drop that results from high temperature and, to a lesser degree, the dynamic threshold voltage shift during the SC transient. The device failure in a single-event SC test is related to heat diffusion to a wider region. Some guidelines are proposed for handling and improving the repetitive SC capability. [ABSTRACT FROM AUTHOR]

The surface of the p-GaN layer in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) can be reinforced with enhanced immunity to hot electron bombardment by reconstructing the surface region of p-GaN into GaON. The surface region of p-GaN is treated by remote oxygen plasma and subsequently annealed at 800 °C, thereby becoming a thin crystalline gallium oxynitride (GaON) layer that will be in direct contact with the Schottky metal. The GaON exhibits a lower valence band maximum energy than that of the p-GaN, which leads to a higher Schottky barrier at the metal/GaON interface to holes and, thus, greatly suppresses the forward gate leakage. More importantly, with higher thermodynamic stability and a larger bandgap of ∼4.1 eV, the GaON reinforces the susceptible metal/p-GaN interface against the hot electrons and, thus, substantially enhances the long-term gate reliability of p-GaN gate HEMTs under forward bias stress. The high-temperature thermal process is indispensable for the surface reconstruction, without which the plasma oxidation only reduces the gate leakage but fails to prolong the time-dependent gate breakdown lifetime. [ABSTRACT FROM AUTHOR]

Background: Sentinel physician surveillance in communities has played an important role in detecting early signs of epidemics. The traditional approach is to let the primary care physician voluntarily and actively report diseases to the health department on a weekly basis. However, this is labor-intensive work, and the spatio-temporal resolution of the surveillance data is not precise at all. In this study, we built up a clinic-based enhanced sentinel surveillance system named "Sentinel plus" which was designed for sentinel clinics and community hospitals to monitor 23 kinds of syndromic groups in Taipei City, Taiwan. The definitions of those syndromic groups were based on ICD-10 diagnoses from physicians. Methods: Daily ICD-10 counts of two syndromic groups including ILI and EV-like syndromes in Taipei City were extracted from Sentinel plus. A negative binomial regression model was used to couple with lag structure functions to examine the short-term association between ICD counts and meteorological variables. After fitting the negative binomial regression model, residuals were further rescaled to Pearson residuals. We then monitored these daily standardized Pearson residuals for any aberrations from July 2018 to October 2019. Results: The results showed that daily average temperature was significantly negatively associated with numbers of ILI syndromes. The ozone and PM2.5 concentrations were significantly positively associated with ILI syndromes. In addition, daily minimum temperature, and the ozone and PM2.5 concentrations were significantly negatively associated with the EV-like syndromes. The aberrational signals detected from clinics for ILI and EV-like syndromes were earlier than the epidemic period based on outpatient surveillance defined by the Taiwan CDC. Conclusions: This system not only provides warning signals to the local health department for managing the risks but also reminds medical practitioners to be vigilant toward susceptible patients. The near real-time surveillance can help decision makers evaluate their policy on a timely basis. [ABSTRACT FROM AUTHOR]

A closely coupled double-channel (DC) structure realized on an 8-inch GaN-on-Si wafer is utilized to fabricate GaN high-electron-mobility-transistors (HEMTs) with enhanced RF linearity. The strong channel-to-channel coupling from this DC structure enables efficient transport of electrons between the two parallel channels to accommodate balanced carrier concentration and current density between the two channels. Consequently, the nonlinearity of source resistance under high current operations and the external bias dependence of cut-off frequencies could be substantially mitigated, leading to device linearity enhancement. Meanwhile, the DC structure enables simple top gate control that favors a high-yield planar process. Two-tone measurements at 4 GHz show that the DC GaN HEMT delivers an output 3rd-order intermodulation point (OIP3) that is improved by 5.2 dB over a single-channel GaN HEMT. [ABSTRACT FROM AUTHOR]

A study was performed to characterize an optimum return trajectory for a sailplane after a rope-break failure during an aerotow launch procedure. The performance of an SGS 1-26E sailplane was simulated using the equations of motion for quasi-steady flight in a time-stepping routine and published aerodynamic polar data. A gradient-based optimization algorithm was implemented using the simulated trajectory considering the glide velocity, bank angles, and runway offset angle to determine the minimum rope-break altitude from which a successful return could be theoretically produced. The SGS 1-26E sailplane was used in a flight-test campaign for empirical turn modeling and validation of the performance simulation. The minimum altitude where a return trajectory and downwind runway landing could be successfully completed after a rope-break event was observed to be 76.4 ft above ground level. A headwind and crosswind presence was observed to decrease the minimum rope-break altitude with increasing wind velocity up to a critical value, after which rope-break altitudes began to increase. These minimum rope-break altitudes serve as a theoretical indication that safe trajectories can be performed at lower failure altitudes than the commonly practiced decision altitude of 200 ft for certain wind conditions. [ABSTRACT FROM AUTHOR]

Background: During the COVID-19 pandemic, a school closure policy was adopted to prevent cluster transmission in schools and subsequent household transmission. However, the effectiveness of school closure is not consistent in studies conducted in different countries., Objective: This study aimed to explore the association between school closure and the daily standardized incidence of COVID-19-related syndromes in an outpatient syndromic surveillance system., Methods: We calculated the incidence of COVID-19-related syndromes derived from a community-based syndromic surveillance system between the first week of January and the second or fourth weeks after school closure in 2021 and 2022 in Taipei City, Taiwan. The effect of school closure on the standardized incidence of COVID-19-related syndromes was evaluated by interrupted time series analysis using an autoregressive integrated moving average with a distributed lag function. The exogenous variables were changes in human mobility measured by Google COVID-19 community mobility reports. Furthermore, the models quantified the influence of different age groups and the hierarchy of medical facilities, such as clinics or community hospitals., Results: School closure was only negatively and significantly associated with the overall standardized incidence of COVID-19-related syndromes in 2021 for 2 weeks after the intervention (coefficient -1.24, 95% CI -2.40 to -0.08). However, in different age groups, school closure had a significantly negative association with the standardized incidence among people aged 13-18 years and ≥65 years for 2 weeks after the intervention in clinics in 2021. In community hospitals, school closure was significantly positively associated with the standardized incidence among people aged 19-24 years in 2021. In 2022, 2 weeks after the intervention, school closure had a significantly negative association with the standardized incidence among people aged 0-6, 7-12, and 19-24 years in community hospitals and aged >45 years in clinics. Furthermore, the standardized incidence was positively associated with movement change toward grocery and pharmacy stores in all age groups in 2022. In addition, movement changes toward residences were significantly positively associated with the standardized incidence among all age groups., Conclusions: Overall, school closure effectively suppresses COVID-19-related syndromes in students owing to the reduction of physical contact. In addition, school closure has a spillover effect on elderly people who stay at home., (©Ping-Chen Chung, Kevin J Chen, Hui-Mei Chang, Ta-Chien Chan. Originally published in the Interactive Journal of Medical Research (https://www.i-jmr.org/), 15.12.2023.)

Pancreatic neuroendocrine tumors (PNETs) are malignancies arising from the islets of Langerhans. Therapeutic options are limited for the over 50% of patients who present with metastatic disease. We aimed to identify mechanisms to remodel the PNET tumor microenvironment (TME) to ultimately enhance susceptibility to immunotherapy. The TMEs of localized and metastatic PNETs were investigated using an approach that combines RNA-Seq, cancer and T cell profiling, and pharmacologic perturbations. RNA-Seq analysis indicated that the primary tumors of metastatic PNETs showed significant activation of inflammatory and immune-related pathways. We determined that metastatic PNETs featured increased numbers of tumor-infiltrating T cells compared with localized tumors. T cells isolated from both localized and metastatic PNETs showed evidence of recruitment and antigen-dependent activation, suggestive of an immune-permissive microenvironment. A computational analysis suggested that vorinostat, a histone deacetylase inhibitor, may perturb the transcriptomic signature of metastatic PNETs. Treatment of PNET cell lines with vorinostat increased chemokine CCR5 expression by NF-κB activation. Vorinostat treatment of patient-derived metastatic PNET tissues augmented recruitment of autologous T cells, and this augmentation was substantiated in a mouse model of PNET. Pharmacologic induction of chemokine expression may represent a promising approach for enhancing the immunogenicity of metastatic PNET TMEs.