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The five-level nested neutral-point-clamped (5L-NNPC) converter is one of the most promising topologies for medium-voltage (2.3–7.2 kV) high-power applications such as medium-voltage drives, wind energy conversion systems, and grid-connected systems. The 5L-NNPC requires a fewer number of switching devices, freewheeling and clamping diodes, and flying capacitors compared to the existing five-level multilevel converters. In the 5L-NNPC topology, each flying capacitor voltage is regulated at one-fourth of the dc-bus voltage to obtain the five-level operation. Due to the lack of redundant switching states, it is difficult to control the flying capacitor voltages by using the pulse-width-modulation-based classical control methods. This paper proposes a model-predictive current control (MPCC) approach to control the flying capacitor voltages along with the output currents of the 5L-NNPC converter. The discrete-time model of 5L-NNPC is developed to implement the MPCC scheme. The simulation and experimental studies are conducted to verify the dynamic and steady-state performance of 5L-NNPC with the MPCC scheme. The performance of the proposed MPCC approach is compared with the conventional space-vector-modulation-based voltage-balancing approach. Furthermore, the flying capacitor voltage control capability of MPCC is verified at different load power factors. [ABSTRACT FROM AUTHOR]

This paper proposes a control method for a five-level hybrid flying-capacitor (5L-HFC) inverter, of which structure stems from the conventional five-level active neutral-point-clamped (5L-ANPC) topology by dividing the dc-link stage into three series-connected capacitors. In this inverter, the voltage stress on the power switches connected to the dc link is reduced by a half compared with that of the 5L-ANPC topology, thus the lower number of equally voltage-rated power devices can be employed. Also, the power losses in the 5L-HFC inverter are more evenly distributed than in the 5L-ANPC. In order to balance the dc-link capacitor voltages, a third-order harmonic offset injection is applied. When a diode rectifier is used to supply the dc bus voltage, the balancing method is not effective if the modulation index is higher than 0.64. Thus, an auxiliary circuit is needed to support the balancing of the dc-link capacitor voltages. However, the unbalancing problem can be overcome in a full-range operation without the auxiliary circuit if the back-to-back configuration is utilized. Finally, simulation and experiment results have verified the performance of the 5L-HFC inverter with the proposed control method. [ABSTRACT FROM AUTHOR]

Fault detection and isolation (FDI) is currently considered a crucial way to increase the reliability of modular multilevel converters (MMCs), which consist of a large number of power electronics submodules (SMs). This paper proposes a fast FDI approach to identifying single open-circuit faults of insulated-gate bipolar transistors in SMs for MMCs with model-predictive control (MPC). The fault detection approach is simply implemented by checking the voltage errors between the measured arm voltages and the estimated ones in the former control cycle. The fault isolation is achieved by checking the switching state directly. The proposed FDI scheme is straightforward, and no additional transducer or measurement is required. Compared with the phase-shifted pulse-width-modulation-based scheme, the MPC has a known and unchanged switching state in a sampling period, which can be utilized for fast location of open-circuit faults. Experimental results show that an open-circuit fault in the MMC can be accurately detected and located in several sampling periods. [ABSTRACT FROM AUTHOR]

This paper demonstrates a two-stage implementation of a step-down power factor preregulator design that achieves a high efficiency across the entire universal input voltage range ($\text{85}\text{--}\text{265}\,\textrm {V}_{\textrm {rms}}$) for an offline power supply application. In this implementation, a resonant LLC converter supplies power to a boost converter operating in a continuous conduction mode. A variable frequency multiplier technique is used in a resonant LLC converter stage to provide different dc gains and compress the effective input voltage range. The efficiency performance achieved is flatter and higher than other conventional offline power converter design consisting of a boost power factor correction circuit followed by a resonant LLC converter, whose efficiency tends to drop significantly at low-line input voltages. The proposed circuit allows MOSFETs with lower voltage ratings and better conduction/switching characteristics to be used in both converter stages. Both of the LLC stage and boost circuit can be better optimized due to the compressed operation range and better semiconductor switches. A scaling law of power losses versus breakdown voltage requirement for boost circuit under the condition of the same output power is presented. Experimental results demonstrated a flatter high efficiency performance across a wide input range. [ABSTRACT FROM AUTHOR]

A single-inductor multiple-output (SIMO) dc–dc converter with output-voltage-aware charge control (OVACC) is presented in this paper. The OVACC scheme reduces the cross regulation by computing the total energy required by all outputs to extract exactly the same amount of energy from the input. Moreover, the proposed design also extends the load capability range of the SIMO converter by supporting the operation in both continuous conduction mode and discontinuous conduction mode while boosting the overall power efficiency. The proposed SIMO (five outputs) dc–dc converter has been implemented in a 0.18 μm 1P6M CMOS process. Measurement results show that the best cross regulation is 0.016 mV/mA when the output current of 250 mA abruptly changes. And no cross regulation is observed when the first output current changes 150 mA, the second output current changes 160 mA, the third and fourth output currents change 180 mA, and the last output current changes 250 mA. Also, the measured peak power efficiency is 86%. [ABSTRACT FROM AUTHOR]

This paper proposes a novel nonisolated single-input dual-output three-level dc–dc converter (SIDO-TLC) appropriate for medium- and high-voltage applications. The SIDO-TLC is an integration of the three-level buck and boost converters, whose output voltages are regulated simultaneously. Reducing voltage stress across semiconductor devices, improving efficiency, and reducing inductors size are among the main merits of the new topology. Moreover, due to the considerably reduced volume of the step-down filter capacitor, a small film capacitor can be used instead, whose advantages are lower equivalent series resistance and a longer lifespan. A closed-loop control system has been designed based on a small-signal model derivation in order to regulate the output voltages along with the capacitors’ voltage balancing. In order to verify the theoretical and simulation results, a 300-W prototype was built and experimented. The results prove the aforementioned advantages of the SIDO-TLC, and the high effectiveness of the balancing control strategy. Furthermore, the converter shows very good stability, even under simultaneous step changes of the loads and input voltage. [ABSTRACT FROM AUTHOR]

In this paper, a three-level quasi-switched boost T-type inverter (3L qSBT2I) is proposed. A new pulse-width modulated (PWM) control method is presented to reduce the inductor current ripple of the qSBT2 I. In the introduced PWM technique, the shoot-through duty cycle is maintained constant to keep the modulation index as high as possible. Then, the only control parameters of the qSBT2I are the duty cycles of the two additional switches. By controlling the duty cycles of the two additional switches, the voltage gain of the proposed qSBT2 I can be improved to a value larger than that of the conventional 3L impedance source inverters. The steady-state analysis, operating principles, and comparisons with the impedance source-based 3L inverters are presented. A 1-kW prototype is constructed to verify the operating principle of the 3L qSBT2I. An indirect dc-link voltage regulator and a capacitor voltage-balance controller are applied to the proposed qSBT2I. Simulation and experimental results are presented. [ABSTRACT FROM AUTHOR]

This paper presents a new concept and approach for topology control and switching in distribution systems by extending the traditional circuit switching to laterals and single-phase loads. Voltage unbalance and other key performance indicators including voltage magnitudes, line loading, and energy losses are used to characterize and demonstrate the technical value of optimizing system topology on a per-phase basis in response to feeder conditions. The near-optimal per-phase topology control is defined as a series of hierarchical optimization problems. The proposed approach is applied to IEEE 13-bus and 123-bus test systems for demonstration, which included the impact of integrating electric vehicles (EVs) in the test circuit. It is concluded that the proposed approach can be effectively leveraged to improve voltage profiles with electric vehicles, the extent of which depends on the performance of the base case without EVs. [ABSTRACT FROM AUTHOR]

A new approach to the control of three-phase two-level grid-connected power converters is proposed in this paper. The proposed control is an extended state observer (ESO)-based second order sliding mode (SOSM), which comprises two control loops: the outer loop is a voltage regulation loop, as well as inner loop is an instantaneous power tracking loop. The outer loop is accomplished by an ${H}_{\infty }$ controller plus an ESO, which is designed to regulate dc-link capacitor voltage of the converter and asymptotically reject external disturbances and parameter perturbations. The SOSM strategy is employed in the inner loop to drive the active and reactive power convergence to their desired values. Control objectives of nearly unity power factor and dc-link capacitor voltage regulation are simultaneously satisfied. Availability of the ESO-based SOSM is compared with the classic proportional-integral control in simulations, and the comparison implies that the proposed strategy not merely achieves an almost perfect tracking performance, but also provides a complete robustness against resistance load variation. [ABSTRACT FROM AUTHOR]

The neutral-point potential fluctuation in single-phase three-level rectifiers leads to coupling between the line current regulation and dc-link capacitor voltage balancing, deteriorating waveform quality of the line current. For addressing this issue, this paper proposes a low-complexity model predictive current control (MPCC) with constant switching frequency, which achieves a decoupling control of the line current and the neutral-point potential under the unbalanced load condition. The switching frequency is fixed by combining the MPCC scheme with predefined switching sequences. The boundary of the durations for voltage vectors in switching sequences is presented to balance the capacitor voltage without worsening the line current quality. The optimal switching sequence and the corresponding optimal durations of voltage vectors in the switching sequence are readily derived without the assessment of the cost function, which dramatically simplifies the complexity of the MPCC scheme. Finally, simulations and experimental results are conducted to verify the effectiveness of the proposed MPCC scheme. [ABSTRACT FROM AUTHOR]

High-frequency (HF) switching and ac-side unbalanced loads challenge smart transformer (ST)-fed hybrid grids (both ac and dc), causing common-mode (CM) voltage variations and dc-link oscillation. The HF switching introduces an HF CM voltage and the ac grid unbalanced loads introduce a fundamental frequency CM voltage in hybrid grids. The CM voltage in ST-fed distributed grids degrades the power quality, threatens the safety of the connected devices, and potentially constitutes a health risk for the operators of such devices. Therefore, this paper systematically analyzes the root causes of the ST CM voltage variations and the impacts on hybrid grids. Based on the two typical configurations (three- and four-leg converters), the performance and requirements of CM inductor filter and bypass CM filter on HF CM voltage suppression are studied in detail. By considering the CM voltage suppression and dc capacitor lifetime, a four-leg converter with improved modulation strategy and small dc bypass film capacitor is proposed. The simulation and experimental results clearly verify the feasibility and correctness of the proposed strategies. [ABSTRACT FROM AUTHOR]

In this paper, a modular control approach has been proposed for a single- and three-phase differential-mode Ćuk inverter (DMCI) operating with a recently proposed discontinuous-modulation scheme that offers tangible performance benefits over conventional continuous modulation scheme. The modular control scheme uses a combination of a transformation and adaptive control law to meet tracking requirements in the presence of converter nonlinearity. Experimental results for the single- and three-phase DMCI are provided for startup, steady state, load transition, and total harmonic distortion using different types of loads, which validate the efficacy of the implemented modular tracking controller. Further, detailed stability of the closed-loop DMCI module is provided. [ABSTRACT FROM AUTHOR]

In this paper, a fifth-order boost point-of-load converter is developed by cascading a modified fourth-order boost converter with a combination of L–C and diode. This topology has the following salient features: Single-switch topology, common ground between source and load, low-voltage stress across intermediate capacitors, and voltage gain same as other reported fifth-order boost converters with no common ground. Steady-state and dynamic analyses demonstrate the proposed converter's boosting feature and dynamic performance, respectively. A contoured robust Bode plot methodology is employed to design the robust voltage-mode controller to ensure load voltage regulation in the presence of uncertainties. The necessary and sufficient conditions under which the designed controller guarantees the load voltage regulation and robust stability are obtained. A step-by-step robust controller design procedure is outlined. The salient features of the proposed converter and its robust performance are studied analytically, using the MATLAB platform, and validated experimentally on a 60-W prototype module. [ABSTRACT FROM AUTHOR]

This paper presents a dual output power factor correction (PFC) converter for switched reluctance motor (SRM) drives. Here, a modified single-ended primary inductance converter (SEPIC) is proposed for a wide range of speed control and to achieve PFC at ac mains. The switching frequency of the converter is considered to be 20 kHz. The converter is designed to operate in the discontinuous conduction mode (DCM) of operation, which reduces the size of the output inductor. The DCM mode to obtain PFC also reduces the sensor requirement as compared to the continuous conduction mode (CCM), where two voltage sensors and one current sensor add to the drive cost. The drive is proposed for universal ac mains (90–270 V ac). Simulated and experimental results are demonstrated to validate the performance of the drive during different operating conditions. The input current total harmonic distortion is reduced to comply with an IEC 61000-3-2 standard. [ABSTRACT FROM AUTHOR]

This paper investigates an ac–dc–ac multilevel power converter. The studied configuration is composed of two single-phase ac–dc–ac three-leg modules and series-connected H-bridges in the shared part of system. Because the proposed converter has shared legs between the input and output, it is employed in applications with same input and output frequency. Uninterrupted power supply and unified power quality conditioner are application examples for this converter. Such multilevel topology has lower dc-link voltage rating, which, consequently, presents low switch blocking voltages when compared to conventional topologies. System model, a space-vector pulsewidth modulation (PWM) strategy to symmetrical and asymmetrical dc-link voltages, and an overall control strategy to adjust the system variables are presented. A power flux analysis shows the operation zone in which the individual dc-link voltage balancing is possible. PWM and control strategies are developed to reduce the semiconductor total losses, harmonic distortion, and switching stress. Two ac–dc–ac multilevel conventional structures are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

Microinverters operating into the single-phase grid from new energy source with low-voltage output face the challenges of efficiency bottleneck and twice-line-frequency variation. This paper proposed a multilevel inverter based on bridge modular switched-capacitor (BMSC) circuits with its superiority in conversion efficiency and power density. The topology is composed of dc–dc and dc–ac stages with independent control for each stage, aiming to improve system stability and simplify the control method. The BMSC dc–dc stage, which can be expanded to synthesize more levels, not only features multilevel voltage gain but also partially replaces the original bulk input capacitor and functions as an active energy buffer to enhance power-decoupling ability between dc and ac sides. In dc–ac stage, the control strategy of optimized unipolar frequency doubling sine-wave pulse width modulation is proposed to improve the quality of output waveform. Meanwhile, the multilevel voltage phase has been optimized to further reduce the power loss. Finally, a prototype has been built and tested. Associated with the simulation, the experimental results validate the practicability of these analyses. [ABSTRACT FROM PUBLISHER]

This paper proposes a circuit structure that can improve the power-conversion efficiency \eta e of an AC–DC boost converter. The circuit uses a 1:1 transformer and a voltage boost circuit composed of an inductor, a capacitor, and a diode. The transformer forces the converter to operate in continuous conduction mode for input current, and thereby reduces input ripple. The voltage boost circuit enables the switch to operate in critical conduction mode, so the power loss due to turn-on of switch and reverse recovery of diode is minimized. The proposed converter has high \eta e over a wide range of AC input voltage $V_{{\rm{ac}}}:\,\eta _{e}= 92.9\% $ at $V_{{\rm{ac}}}= {\text{85}}\,{\text{V}} and \eta e= 97.4\% at V{\rm{ac}}= {\text{265}}\,{\text{V}}, when the converter was operated at DC output voltage of 400 V and output power of 500 W. The temperature of the switch stabilized at ∼84 °C for $V_{{\rm{ac}}}= {\text{85}}\,{\text{V}}$ , at ∼70 °C for $V_{{\rm{ac}}}= {\text{110}}\,{\text{V}}$, and at ∼42 °C for $V_{{\rm{ac}}}= {\text{220}}\,{\text{V}}$, whereas that in other AC–DC converters either failed or stabilized at much higher levels. The proposed converter is well suited to systems that require an input voltage range of 85–265 V in root-mean-square value. [ABSTRACT FROM AUTHOR]

The switching frequency is an important control parameter of pulse-width-modulation (PWM) rectifier to reduce switching losses and electromagnetic interference noise. This paper proposed a variable switching frequency PWM (VSFPWM) strategy for dc-link voltage ripple control in two-level rectifier. DC-link voltage ripple is determined by the dc-link current directly, and can be predicted synchronously with PWM signals. A real-time prediction model of dc-link voltage ripple is derived for a common voltage-oriented control PWM rectifier. Then, VSFPWM control is introduced, which changes the switching frequency cycle to cycle with a restriction of dc-link voltage ripple peak value. Furthermore, the dynamic behavior is also observed when the proposed VSFPWM control scheme is adopted. Detail simulation and experimental comparisons are carried out between VSFPWM and normal constant switching frequency PWM, which demonstrate the advantages of the proposed method. [ABSTRACT FROM AUTHOR]

Conventional implementations of fully integrated, battery-connected, switched-capacitor voltage regulators (SCVRs) require either thick-oxide mosfets or stacked thin-oxide mosfets as power switches to sustain the voltage stress induced by a nominal 3.7-V Li-ion battery voltage. These approaches, however, exacerbate power loss, thus unable to achieve good power efficiency. Therefore, this paper proposes a solution to overcome the breakdown issue while improving the power efficiency by using only nonstacked, thin-oxide mosfets. This is realized by using a three-state, low-voltage-stress SCVR with a cross-phase-switching technique to decrease the output impedance and increase the total equivalent capacitance in a multiphase configuration. A prototype 3:1 SCVR is implemented fully on-chip in a standard 130-nm CMOS process. The chip is capable of delivering a maximum load current of 45 mA with an input voltage range from 3.2 to 4 V. Measurement results show 78–80% efficiency over a range of output power 4–28 mW, and a power density up to 38 mW/nF. The measured output ripple is 30–50 mV over a load range of 11–45 mA, and the measured voltage droop is 69 mV with 200-ns settling time under a 13-mA load step. [ABSTRACT FROM AUTHOR]

Modularity and high reliability from redundancy are the two attractive advantages of modular multilevel converters (MMCs). This paper elaborates a switch open-circuit fault diagnosis and a fault-tolerant operation scheme for MMCs with distributed control. The proposed fault diagnosis and fault-tolerant control method can significantly improve the reliability of the MMC while maintaining the modularity of its software implementation. By distributing fault diagnosis into submodules, its local controller is capable of identifying the switching devices in open-circuit fault without extra hardware circuitry. Based on the real-time measurements of submodule terminal voltage and arm current, single, or multiple faulty switches can be identified within 3.5 ms without triggering faulty alarms. Furthermore, a new fault-tolerant operation is proposed to maintain the output current, internal dynamics, and switching harmonics unchanged after the faulty submodule is bypassed. This is achieved by resetting the period and phase registers in the local controller according to the information of bypassed submodules. The control loops of the MMC are not influenced by the proposed fault diagnosis and fault-tolerant operation, making the operation transition seamless and reliable. Experimental results show that fault identification and system reconfiguration can be completed within 5 ms, and the MMC can seamlessly and smooth ride through the switch open-circuit faults without severe malfunction and catastrophic damages. [ABSTRACT FROM AUTHOR]

This paper presents the active capacitor voltage-balancing (ACVB) methods based on the dynamic model for a five-level nested neutral-point piloted (NNPP) converter using hybrid carrier modulation. The traditional hybrid carrier modulation provides natural voltage balancing of floating capacitors and dc-link capacitors. First, the natural voltage-balancing ability under steady-state and ideal conditions is theoretically proved. However, there are accumulated errors and deviations of capacitor voltages in practical applications, especially under dynamic conditions. In order to address the accumulated errors and deviations of capacitor voltages, the dynamic models of floating-capacitor voltages and neutral-point voltage are established. Moreover, the ACVB method based on the dynamic model of the neutral-point voltage is proposed by injecting the zero-sequence voltage. And the ACVB method based on the dynamic model of floating-capacitor voltages is proposed by introducing the adjustment variables. The proposed ACVB methods have the advantages of simple formula, definite physical meaning, and high accuracy. Furthermore, the output voltage quality and current quality are evaluated in term of total harmonic distortion and the effect of model parameter mismatch on the proposed ACVB methods is presented. Finally, the comparative simulation and experimental results verify the correctness of the proposed ACVB methods based on the dynamic model under different conditions. [ABSTRACT FROM AUTHOR]

An H-bridge hybrid modular converter (HBHMC) is proposed for high-voltage direct current (HVDC) applications. It uses a wave-shaping circuit consisting of series-connected full-bridge submodules (FBSMs) at the output of the main H-bridge converter. For a three-phase system, three HBHMCs are connected either in series (series-HBHMC) or in parallel (parallel-HBHMC) across the dc-link. The operating modes of HBHMC, novel modulation strategies for voltage balancing of FBSMs, and control of HBHMC-based HVDC system are presented in this paper. A detailed comparison between HBHMC and other hybrid topologies is performed on the basis of required number of switches and capacitors. The HBHMC has the features of dc fault blocking capability, lower footprint structure, and extra degree of freedom for submodules capacitor voltage balancing. The efficacy of the HBHMC-based HVDC system for three-phase balanced and unbalanced grid conditions and its fault-tolerant capability are validated using PSCAD simulation studies. Furthermore, the feasibility of the proposed converter under normal and dc fault conditions and of the proposed capacitor voltage control scheme is validated experimentally by using a three-phase grid-connected HBHMC laboratory prototype. The results demonstrate the effectiveness of the proposed HBHMC topology, control techniques, and satisfactory responses of the HBHMC-based HVDC system. [ABSTRACT FROM AUTHOR]

This paper presents a hybrid pulse width modulation-based discontinuous modulation (D-HPWM) strategy with dc-link voltage balancing for a three-level neutral-point-clamped (NPC) traction inverter drive. The results are then compared with continuous-hybrid-PWM (C-HPWM) to check the performance improvement. The HPWM strategy uses both the advantages of carrier- and space-vector-based PWM strategies. The duty cycles are generated using the carrier-based strategy to reduce the computational time and complexity of the system and redundant vector states are used to keep the two dc-link capacitor voltages balanced. As discontinuous PWM (DPWM) reduces the switching losses considerably compared to the continuous PWM, the DPWM strategy is developed in this paper for the HPWM-based strategy. Detailed comparison studies are then carried out in MATLAB/Simulink and PLECS to show the conduction and switching loss distribution with change in modulation index for different power switches. A 54.0-kW surface permanent magnet synchronous machine (PMSM) is used for this simulation studies. Moreover, the total inverter loss and losses in each insulated gate bipolar transistor (IGBT) are also compared. Detailed experimental performance analysis is also carried out with a scaled down prototype of a 6.0-kW surface PMSM, NPC inverter, and real-time emulator DSpace, to show the capacitor voltage deviation with both control strategies. [ABSTRACT FROM PUBLISHER]

This paper proposes a practical solution of high-frequency-link dc transformer based on switched capacitor (SCDCT) for medium-voltage dc (MVDC) power distribution application. Compared to the traditional dc transformer scheme, the proposed SCDCT can disconnect from MVDC distribution grid effectively as a dc breaker when a short fault occurs in the distribution, can enhance power transfer capacity, and always ensures high-frequency-link voltage match to improve current impact and efficiency performances, and the redundancy design can be achieved when some submodules fail to improve the reliability. In the paper, the topology, voltage and power characterization, control strategy, startup, and fault solution of SCDCT are presented and analyzed comprehensively. At last, an SCDCT prototype is built and the experimental results verify the correctness and effectively of the proposed solution. [ABSTRACT FROM AUTHOR]

A new pulsewidth modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is proposed in this paper. A three-level NPC inverter is completely mature and very well-established topology in high-power applications. However, the three-level NPC inverter has an inheritance problem of the neutral-point voltage unbalancing due to the split dc-link capacitors. This structure can cause large neutral-point voltage ripple. Furthermore, output currents of the three-level NPC inverter are distorted by the neutral-point voltage ripple. Therefore, the neutral-point voltage must be controlled. In this paper, a new DPWM method using two different offsets for the neutral-point ripple reduction is proposed and the effectiveness of the proposed DPWM method is verified by using the simulation and the experimental results. [ABSTRACT FROM PUBLISHER]

The five-level active neutral-point-clamped (5L-ANPC) converter is becoming an attractive topology of multilevel converter family. A novel SVPWM algorithm based on line voltage coordinate was studied in this paper to overcome shortcomings of the traditional algorithm. Through coordinate transformation, steps of determining the basic vectors and the solution about the basic vector corresponding action time are simplified. Combining with the characteristics of 5L-ANPC converter and the new control algorithm, a method of controlling the voltage balancing of dc-link capacitors and floating-capacitors is proposed. According to the voltage of dc-link capacitors, the suitable switching sequence which can balance the voltage of dc-link capacitors is chosen. The high common-mode voltage will affect the service life of motor and reduce the reliability of the system especially in high-voltage converter. The common-mode voltage is also reduced by choosing the right switching state in this paper. The validity of the proposed method was proved by the experimental results. [ABSTRACT FROM AUTHOR]

Modular multilevel converters (MMCs) are widely used in different applications. Due to low-loss operation, compactness, and high modularity, MMC is extremely attractive for high-voltage direct-current (HVDC) transmission systems. The HVDC station loss is highly related to the converter switching pulse pattern, which is generated by modulation algorithm and cell selection methods. This paper formulates the switching pulse pattern generation, as a versatile optimization problem. The problem constraints and objectives are formulated for HVDC applications and compared with similar problems in the field of computer science. To overcome the computational complexity in solving the introduced optimization problem, a heuristic method is proposed for cell selection algorithm. The method utilizes the current level in order to obtain lossless switching at zero-current crossings. The study of the proposed method, in a time-domain simulation platform, shows that the method can reduce the switching converter losses by 60% compared to carrier-based modulation, maintaining the same capacitor voltage ripple. Eventually, the practical functionality of the proposed method is verified in a real-time digital simulator, RTDS, for a 512-level converter in a point to point HVDC link. Although this paper focuses on HVDC, the mathematical model is applicable for any MMC application. [ABSTRACT FROM PUBLISHER]

In this paper, a modulation and control method for the new transformerless unified power flow controller (UPFC) is presented. As is well known, the conventional UPFC that consists of two back-to-back inverters requires bulky and often complicated zigzag transformers for isolation and reaching high power rating with desired voltage waveforms. To overcome this problem, a completely transformerless UPFC based on an innovative configuration of two cascade multilevel inverters has been proposed. The new UPFC offers several advantages over the traditional technology, such as transformerless, light weight, high efficiency, low cost and fast dynamic response. This paper focuses on the modulation and control for this new transformerless UPFC, including optimized fundamental frequency modulation for low total harmonic distortion and high efficiency, independent active and reactive power control over the transmission line, dc-link voltage balance control, etc. The new UPFC with proposed control method is verified by experiments based on 4160-V test setup. Both the steady-state and dynamic-response results will be shown in this paper. [ABSTRACT FROM PUBLISHER]

This paper presents an improved dc-link voltage balancing algorithm for a three-level neutral-point-clamped inverter by considering phase current direction. Detailed studies on the effects of change in load current direction on the dc-link capacitor voltages are presented. A maximum value of power factor is numerically derived, above which it affects the capacitor voltage balancing capability. Compared with the previously presented research work, the inputs to the space-vector pulsewidth-modulation block are the three phase currents and the difference between the two capacitor voltages. Depending on the states of the two dc-link capacitor voltages and phase current direction, redundant voltage vector sequences are selected. The selected vectors keep the capacitor voltage deviations within 5% of the total dc-link voltage. Two zero switching vectors (i.e., PPP and NNN) are also removed from all subsectors of the earlier proposed strategy, which one used to produce higher common-mode voltages. Detailed simulation and experimental results are presented in this paper for a 6.0-kW surface permanent-magnet synchronous machine. Both the simulation and experimental results show the required performance of the proposed system. [ABSTRACT FROM AUTHOR]

Single-stage power-factor-corrected (S2PFC) power supplies usually suffer from high voltage stress, due to lack of control on the intermediate bus capacitor voltage. In the past, analysis of such voltage stress was mostly based on steady-state condition without providing sufficient explanation during the transient circuit operation. This paper revisits the problem at circuit level and reports that the root cause is due to the inherent negative current feedback property of the output inductor or the transformer operating in continuous conduction mode (CCM). Based on the finding, this paper further proposes a new approach to reducing the voltage stress by adding an auxiliary circuit branch to existing S2PFC converters. The additional circuit branch limits the effect of negative current feedback by suppressing the change of output current slope due to change of load. This assists the pulsewidth modulation controller to track the change of load better such that the bus capacitor voltage range is reduced through duty cycle control. The auxiliary circuit branch also reduces reverse-recovery-related losses of the converter under CCM operation. A laboratory prototype using the popular boost PFC converter combined flyback dc/dc converter was built and tested to confirm the analysis and effectiveness of the approach. [ABSTRACT FROM AUTHOR]

In this paper, we introduced an improved transformer-based parallel-resonant converter, suitable for high voltage, high power dc loads. The resonant capacitors are connected in parallel with diodes of the high voltage rectifier, thus restraining dv/dt stress in high voltage circuits. The LC tank resonant frequency is well beyond the switching frequency, reducing in this way the VA rating of LC components. With rated load, the output current of the IGBT bridge is equal to zero at switching instants, and the switching losses are very low. Proposed subresonant circuit requires lower primary current for the given output power and it has reduced IGBT losses. Experimental setup delivers 79 kW with an efficiency of 96.78%. The paper explains the switching states of the devised topology, and provides the guidelines for designing the power transformer, the LC tank and controls. Analytical prediction of the performance curves is verified both in laboratory and by the field tests with an electrostatic precipitator plant. [ABSTRACT FROM AUTHOR]

In order to solve the neutral-point voltage unbalancing problem for three-level inverters, this paper proposes a method to balance the neutral-point voltage for three-level inverters with variable modulation wave offset sinusoidal pulse-width modulation (SPWM) control. Based on the mathematical expressions of neutral-point voltage unbalancing, the factors are studied, which affect the fluctuation of neutral-point voltage. Theoretically the mathematical expressions of the neutral-point voltage with the proposed method are derived, and the mathematical relationship between the fluctuation of neutral-point voltage and the adjusting offset of modulation wave is studied. This proposed method realizes controlling the neutral-point voltage balance by dynamically calculating the offset superimposed to the modulation wave based on SPWM (DCOSPWM). This DCOSPWM method is very simple, which has good steady-state performance and is easy for digital implementation. The simulation results verify the correctness of the theoretical analysis in this paper, and the feasibility and effectiveness of this method is verified by the experiments in the experimental platform of neutral point clamped three-level inverters based on digital signal processor (DSP)-complex programmable logic device (CPLD). [ABSTRACT FROM AUTHOR]

A single-phase bridgeless Cuk ac/dc power factor correction (PFC) rectifier with positive output voltage is proposed in this paper. For low output voltage product applications, the rectifier is designed to convert high input voltage to low output voltage. Due to no bridge diodes required and thus decreased input conduction losses, the proposed rectifier efficiency can be improved. The proposed rectifier operates in discontinuous conduction mode, and the current-loop circuit is hence not needed. In addition, only a single switch is used in the rectifier to simplify the control circuit design. A simple translation method to have the positive output voltage in the Cuk converter is presented in the rectifier to reduce the component counts and the cost. The operational principles, steady-state analysis, and design procedure of the proposed rectifier are addressed in detail in this paper. Simulation and experimental results obtained from a 150-W rated prototype circuit with input of 90–130 Vrms, 60 Hz, and output of 48 Vdc have verified the validity of the proposed rectifier. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel bidirectional inverter, named series ac-link inverter. This three-phase inverter belongs to a new class of partial resonant ac-link converters in which the link is formed by a series ac inductor/capacitor (LC) pair having low reactive ratings. The input and output of this converter can be either dc, ac, single-phase, or multiphase. Therefore, they can appear as dc–dc, dc–ac, ac–dc, and ac–ac configurations. In all of these configurations, the ac capacitor is the main energy-storage element, and the inductor is merely added to facilitate the zero-current turnoff of the switches and their soft turn-on. Due to the zero-current turnoff of the switches in the proposed converter, the use of SCRs with natural commutation is possible as well. Since the current and voltage of the link are both alternating, no bulky dc-electrolytic capacitors are required in this converter. This paper mainly focuses on bidirectional dc to three-phase ac conversion. This single-stage inverter can step up or step down the voltage in a wide range. If galvanic isolation is required a single-phase high-frequency transformer can be added to the link. In the proposed inverter, the power can flow in both directions, and therefore, it is an excellent candidate for battery-utility interface and electric vehicle applications. In this paper, the principles of the operation of the proposed inverter, along with its design and analysis, are studied. Moreover, the performance of the proposed configuration is evaluated in this paper. Both simulation and experimental results are included. [ABSTRACT FROM AUTHOR]

This paper investigates the applicability of averaged-value models (AVMs) for modular multilevel converters (MMCs) operating in a voltage-sourced converter-based-high-voltage dc (VSC-HVDC) grid. The AVM models are benchmarked by comparison with a detailed electromagnetic transient model of the grid, including a fully detailed MMC model. Analysis results show that the AVM is only effective as long as the capacitors are large enough to maintain nearly constant voltage across each MMC submodule. This paper also shows that previously developed MMC averaged models are not able to accurately simulate the transients under dc fault conditions. This paper introduces topology changes to a previously proposed averaged model that results in much improved simulation for such conditions. This paper also shows that the model can be used effectively to study HVDC grids with significant time savings. [ABSTRACT FROM AUTHOR]

A parallel hybrid modular multilevel converter (PHMMC) belongs to the class of modular multilevel converters, which have become potential candidates for high-voltage direct-current (HVDC) transmission systems. Due to the circuit topology of a PHMMC, the dc bus voltage contains low-order harmonics and cannot be fully regulated at a constant dc voltage. The dc bus voltage, if not properly controlled, leads to improper power transfer and increases the magnitude of dc current ripple on the dc transmission line. This paper proposes a zero-sequence voltage injection (ZSVI)-based model predictive control (MPC) strategy to control the dc current/power flow and simultaneously minimize the dc current ripple. The proposed strategy takes advantage of a cost function minimization technique to determine and inject the optimal zero-sequence voltage components into the dc- bus voltage of a PHMMC system. This paper derives a discrete-time dynamic model of the dc transmission-line current and, correspondingly, develops a predictive model. The predictive model is used to inject the appropriate amount of zero-sequence voltage components to the dc bus reference voltage waveform. Compared with the existing triplen harmonics injection method, the proposed ZSVI-MPC strategy improves the performance of a PHMMC system in terms of minimization of the dc current/voltage ripple. Performance of the proposed strategy for a 21-level PHMMC-based HVDC station system is evaluated based on time-domain simulation studies in the PSCAD/EMTDC software environment. The reported results demonstrate superior performance of the PHMMC-HVDC station operating based on the proposed ZSVI-MPC strategy, under various operating conditions, as opposed to the existing triplen harmonics injection method. [ABSTRACT FROM AUTHOR]

This paper proposes a model predictive control (MPC) method for modular-multilevel-converter (MMC) high-voltage direct current (HVDC). To control the MMC-HVDC system properly, the ac current, circulating current, and submodule (SM) capacitor voltage are taken into consideration. The existing MPC methods for the MMC-HVDC system utilize weighting factors to configure the cost function in combinations of the SM capacitor voltage balancing algorithm, ac current control, and circulating current control. Because all combinations of the switch states are considered in order to minimize the cost function, their possible combinations increase geometrically according to the increase of the level of the MMC, which is a significant disadvantage. This paper proposes a new MPC method with a reduced number of states for ac current control, circulating current control, and the SM capacitor voltage-balancing algorithm. The proposed cost functions are divided into three types according to their control purposes. Each cost function determines the minimum number of states for controlling the ac current, circulating current, and SM capacitor voltage. The efficacy of the proposed controlling method is verified through simulation results using PSCAD/EMTDC. [ABSTRACT FROM AUTHOR]

This paper presents a merged-two-stage circuit topology suitable for either wide-range dc input voltage or ac line voltage at low-to-moderate power levels (e.g., up to 30 W). This two-stage topology is based on a soft-charged switched-capacitor preregulator/transformation stage and a high-frequency magnetic regulator stage. Soft charging of the switched capacitor circuit, zero voltage switching of the high-frequency regulator circuit, and time-based indirect current control are used to maintain high efficiency, high power density, and high power factor. The proposed architecture is applied to an LED driver circuit, and two implementations are demonstrated: a wide input voltage range dc-dc converter and a line interfaced ac-dc converter. The dc-dc converter shows 88%-96% efficiency at 30-W power across 25-200-V input voltage range, and the ac-dc converter achieves 88% efficiency with 0.93 power factor at 8.4-W average power. Contributions of this paper include: 1) demonstrating the value of a merged two-stage architecture to provide substantial design benefits in high-input voltage, low-power step down conversion applications, including both wide-range-input dc-dc and line-input ac-dc systems; 2) introduction of a multimode soft-charged SC stage for the merged architecture that enables compression of an 8:1 input voltage range into a 2:1 intermediate range, along with its implementation, loss considerations, and driving methods; and 3) merging of this topology with an resonant transition discontinuous-mode inverted buck stage and pseudocurrent control to enable step-down power conversion (e.g., for LED lighting) operating at greatly increased frequencies and reduced magnetics size than with more conventional approaches. [ABSTRACT FROM AUTHOR]

This paper proposes a new circuit configuration and a control scheme for a single-phase current-source inverter with a power decoupling circuit which is called as the active buffer. The proposed inverter achieves a low-dc-input voltage ripple and also provides a sinusoidal current that can achieve unity power factor, without large passive components in the dc bus such as smoothing inductors and electrolytic capacitors. These components are conventionally required in order to decouple the power pulsation caused by the single-phase power source. In this paper, the fundamental operations of the proposed inverter are demonstrated experimentally. From the experimental results, the input voltage ripple is 8.87%, and the output current total harmonic distortion is 4.24%. In addition, an output power factor of 99% and a maximum efficiency of 94.9% are obtained. Finally, it is confirmed that the maximum power densities of the conventional circuit and the proposed circuit are 2.75 kW/L at the switching frequency of 70 kHz and 4.86 kW/L at the switching frequency of 80 kHz, respectively. [ABSTRACT FROM AUTHOR]

Multilevel converters are a proven solution for medium-voltage and high-power applications, including renewable energy conversion. Developing 6.6-kV converters is a key goal for the wind turbines industry. Considering the voltage rating of commercially available semiconductors, five-level converters are necessary to reach 6.6 kV. The five-level active neutral-point-clamped converter (5L-ANPC) is one of the most advantageous topologies among five-level multilevel converters. This paper presents a new 5L-ANPC topology that overcomes the features of the previously employed 5L-ANPC topology. Along this paper, the properties and working principle of this new 5L-ANPC are explained. Finally, the validity of the new converter is validated via simulation and experimental results. [ABSTRACT FROM AUTHOR]

Considering the synthetical effects of the ac system and the dc system, this paper proposes two novel indexes, the dynamic redundancy and the utilization ratio of the submodules. On this basis, the nearest level control is applied as the modulation method and an optimized control strategy based on the dynamic redundancy for the modular multilevel converter (MMC) is proposed. One of the main innovations is that the reference value of the capacitor voltage is derived according to the maximum output voltage of each converter arm and the safety margin which can be adjusted artificially. Unlike previous strategies, the redundancy can be adjusted dynamically, and the utilization ratio of the submodules can be effectively improved. In addition, the capacitor voltage and the inner stress are reduced, and the fault ride-through capability of the system can be enhanced. In particular, the strategy under abnormal operating conditions is also detailed in this paper. A model of two-terminal MMC-high-voltage direct current system is built in PSCAD/EMTDC, and the simulation result proves the validity and the feasibility of the proposed strategy. [ABSTRACT FROM AUTHOR]

Filters for switching ripple attenuation are essential at the input, and sometimes at the output for certain applications, for the deployment of matrix converters (MCs). Due to the absence of inertial elements in the MC structure and the consequent tight input–output coupling, the filter parameters significantly affect its dynamic behavior. This paper presents an exhaustive filter design method for synchronous applications of the MC in power systems. Apart from the usual considerations of ripple attenuation, voltage regulation, reactive current loading, and internal losses, this paper also addresses additional constraints which may be imposed by requirements of dynamic performance and reliable commutation. Rigorous analytical justification of each design step is provided and the sequential design process is summarized. Relevant experimental results are presented to validate the proposed design tool. [ABSTRACT FROM PUBLISHER]

In the applications for high-power dc/dc conversion, the power devices usually suffer high voltage and current stress in traditional single-phase dc/dc topologies such as forward, half-bridge, and full-bridge converters, which limits the power level of converter to reach higher. As a superior alternative solution, a three-phase three-level (TPTL) dc/dc converter was investigated in this paper, which has the advantages of lower voltage and current stress on switches, as well as fewer power devices. Adopting a symmetrical control strategy, the input current and output current frequency can be increased by a factor of six compared to the switching frequency, resulting in a reduced filter requirement. However, all the switches are hard-switching, leading to a considerable switching loss. In this paper, an asymmetrical duty cycle control strategy was proposed to the TPTL dc/dc converter. The modified converter remains all the advantages of original control strategy; meanwhile, soft-switching can be achieved using the energy stored in output filter inductance and leakage inductances of transformers (or resonant inductances). The theoretical analysis was presented in details, along with the characteristics and soft-switching condition of the converter. Experimental results from 540 to 600 V input and 48 V/20 A output were presented to verify the theoretical analysis and the performance of the modified converter. [ABSTRACT FROM AUTHOR]

This paper proposes a transformerless dc–dc converter, which features a large voltage ratio, for medium-voltage dc (MVDC) applications. The proposed converter combines a boost converter with a series-parallel resonant converter which enables soft switching of the power switches and diodes. Further, the power switches and diodes of the proposed converter experience lower voltage stresses compared to the other topologies. The proposed converter is modular and, therefore, permits series and/or parallel connection of multiple units for the desired voltage and/or power ratings. This paper discusses the principles of operation, analysis, and design of the proposed converter. Simulation and experimental results are presented to demonstrate the effectiveness of the proposed converter. [ABSTRACT FROM AUTHOR]

Increasing energy demand and growth of wind generation have significantly increased the stress on the electric grid. The low investment in transmission infrastructure necessitates adoption of methods for efficient use of existing resources. Power converter-based FACTS devices, capable of dynamic power-flow control, have been the preferred solution to maximize utilization of existing infrastructure, but implementation of traditional FACTS solutions at transmission level voltages is complex and cost prohibitive. This paper proposes a power router (PR) for dynamic power-flow control in a meshed network. The proposed PR is realized by augmenting a transformer with a fractionally rated back-to-back converter. The main advantages of the proposed converter are the fractional converter rating and reduced low-frequency transformer requirement compared to the traditional FACTS solutions. This paper outlines the proposed PR topology, control range, controller design and demonstrates the functionality through simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper presents an analysis of the Class-E ZVS rectifier using a common-grounded multistep controlled Shunt Capacitor (CSC). The Class-E ZVS rectifier using a common-grounded multistep CSC can regulate the output voltage by changing the shunt capacitance. The voltage over the diode and shunt capacitor in the conventional Class-E ZVS rectifier is shared by the series connected capacitors. In this paper, the Class-E ZVS rectifier using a common-grounded multistep CSC is analyzed, simulated, and experimented. Especially, the power conversion efficiency is discussed in detail. [ABSTRACT FROM AUTHOR]

Due to the relatively low output voltage of photovoltaic (PV) source, a high step-up converter with high efficiency is needed when the PV source is connected to the power grid. A novel high step-up converter based on two switched capacitors and a coupled inductor is proposed in this paper. The operating principle is analyzed and the voltage gain is derived. A 100-W prototype is fabricated in the laboratory to verify the theoretical analysis, and the highest efficiency is 96.4%. [ABSTRACT FROM PUBLISHER]

Model-predictive power control (MPPC) takes the switching nonlinearity of power converters and system constraints into consideration. It is a promising control technique for three-phase four-switch rectifiers (TPFSRs) because capacitor-voltage-balancing control and instantaneous power control can be simultaneously designed for this type of power converters. However, since only one switching vector is allowed in each control interval, conventional MPPC (C-MPPC) may lead to significant output power ripples that can severely degrade system power quality. This is particularly true for TPFSRs due to the limited number of switching states as well as the constraint imposed by the capacitor-voltage-balancing control. To improve the performance of TPFSRs, this paper proposes a multiple-vector MPPC scheme, which can minimize active power and reactive power ripples and achieve capacitor voltage balancing with a constant switching frequency. An equivalent zero-voltage vector model and a capacitor-voltage-balancing model are derived to implement the proposed control scheme. Comparative experimental results are presented to demonstrate the superiority of the proposed control scheme over the C-MPPC. [ABSTRACT FROM PUBLISHER]