Search

In this paper, a highly reliable back-to-back (BTB) power converter is proposed for doubly fed induction generator-based wind turbines (DFIG-WTs). When a power switch open-circuit fault is encountered in either the grid-side converter (GSC) or the rotor-side converter (RSC), a four-switch three-phase (FSTP) topology is formed to avoid using redundant bridge arms, which reduces the power circuit complexity and minimizes the conduction and switching losses. A simplified space vector pulsewidth modulation technique is used to eliminate sector identification and complex trigonometric calculations. In addition, the influence of dc-bus capacitor voltage unbalance on the electromagnetic torque is analyzed in detail. The offset current components are calculated, and they are deducted from the reference values in the modified control strategies to suppress the dc-bus voltage deviation. Moreover, the power loss model of a BTB converter is analyzed in detail, and the efficiency study is performed in various post-fault situations. Simulations in MATLAB/Simulink are carried out to verify the performance of a DFIG-WT based on a FSTP BTB converter. Furthermore, the control hardware-in-the-loop setup with RSC and GSC separately simulated in a digital real-time simulator is applied for experimental verification of the proposed control strategy. [ABSTRACT FROM AUTHOR]

A switching-capacitor-based buck–boost converter (with common ground) for point of load applications is proposed in this paper. It is capable of operating in stand-alone buck or boost mode in addition to its primary operation of performing the buck–boost conversion. The striking feature of the proposed converter is low source current ripple content irrespective of its mode of operation (buck–boost, buck, or boost). First, feasible pulsewidth modulation schemes for the proposed converter are identified and thereafter the corresponding circuit performance analysis, steady-state analysis, and state-space modelling is established. Through steady-state analysis, voltage gain expressions are formulated and equations defining L-C components are derived in terms of their ripple quantities. The state-space models are used to formulate small-signal analysis and to obtain the relevant transfer functions required in the controller design. A voltage-mode/current-mode controller is designed, with a tradeoff in bandwidth, to control the proposed converter and transit it from buck to boost mode or vice versa seamlessly. A 30–55 W, 100 kHz, prototype point of load converter with 36-V input dc source is built to supply power at constant load voltage of either 48 or 28 V. The proposed converters’ effectiveness is demonstrated experimentally in terms of reduced source current ripple along with seamless transition from buck to boost mode and vice versa. [ABSTRACT FROM AUTHOR]

In this paper, three generalized configurations of three-phase pulsewidth modulated (PWM) rectifiers are presented. They are composed of cascaded cells, each formed by a three-phase bridge of switching devices and a three-phase transformer to cascade the cells and isolate the load from the power source. One configuration is bidirectional, whereas the other two are unidirectional alternatives that replace power switches for diodes in some legs. The turns ratios of transformers from each cell are designed in order to provide the required gain and number of levels in the inverted multilevel voltage, enhancing power quality while attending requirements for proper operation in each case. Configurations with two and three cells are compared by means of simulations between themselves and with three conventional three-phase PWM rectifiers: the two-level insulated gate bipolar transistor bridge and the multilevel neutral point clamped (NPC) bridge and NPC H-bridge. Many degrees of asymmetry between the transformers in each cell, determined by the turns ratios, are considered to evaluate their impact on the topologies with relation to performance and cost. It is shown that proposed multilevel rectifiers present lower harmonic distortion, semiconductor losses, and switching stress, and some options with intermediate asymmetry are considered as good alternatives to the most asymmetrical cases. Experimental results are also provided for configurations with two cells, to demonstrate their lower harmonic distortion and power losses compared to the conventional isolated two-level PWM rectifier. [ABSTRACT FROM AUTHOR]

This paper proposes a novel four-leg converter topology and the corresponding SVPWM strategy for a reluctance machine with DC-biased sinusoidal winding current. Compared with the traditional open-winding inverter topology, the number of the power devices and gate driver required for the four-leg converter topology are reduced by one-third, and the power loss is reduced. With the proposed four-leg converter, the cost of the motor drive is reduced and the power density is improved. The vector control and modulation models of the proposed four-leg converter are presented to control the winding current with both AC and DC components. With the proposed four-leg SVPWM strategy, the four-leg converter can achieve the same DC voltage utilization as an open-winding inverter. In addition to the ability to generate αβ-axis voltages, as same with conventional SVPWM, the proposed SVPWM can also generate γ-axis voltages without generating additional zero-sequence alternating voltages on the stator windings. The validity of the proposed converter and the corresponding modulation strategy has been demonstrated by simulation and experiment. The power loss and performance of the four-leg converter are compared with the traditional converter. Contrasting experiments show that the proposed topology can reduce power loss by about 15% at rated operation and achieve the same performance as open-winding inverters. [ABSTRACT FROM AUTHOR]

The highly efficient and reliable inverter concept (HERIC) inverter is a cost-effective topology, which has low leakage currents and a relatively high efficiency. Thus, it is very suitable for transformerless photovoltaic systems. However, with the reported modulation methods, it is difficult to simultaneously maintain the high efficiency, good power quality, and reactive power injection of the HERIC inverter. In this paper, a hybrid unipolar pulsewidth modulation (UP-PWM) scheme is thus proposed to achieve those performances. The hybrid scheme adopts the conventional UP-PWM in the case of generating the positive power. When generating the negative power, a modulation scheme, which only requires the operation of freewheeling switches, is specifically proposed. Additionally, in the region of the output voltage and current zero-crossing points, a UP-PWM with modified deadtime is introduced. In order to validate the effectiveness of the proposed scheme, simulations and experiments are performed on a 4-kW HERIC inverter system with a 20-kHz switching frequency. The results demonstrate that the proposed hybrid UP-PWM method achieves a better performance in terms of reactive power injection than the conventional UP-PWM scheme, and a higher efficiency than the UP-PWM with deadtime. In addition, the proposed UP-PWM scheme also enables a better power quality. [ABSTRACT FROM AUTHOR]

This paper presents new space vector pulsewidth modulation (PWM) strategies for a single-phase three-level buck-boost neutral point clamped inverter coupled with impedance-source (IS) network. These strategies can be implemented for systems with any IS network with neutral point. The case study system is based on the quasi-Z-source inverter with continuous input current. To demonstrate an improved performance, the strategies are compared with a traditional PWM strategy. The advantages lie in reduced switching number, without output voltage quality distortion. The simulation and experimental results confirm the theoretical predictions. [ABSTRACT FROM AUTHOR]

A fast modularized multiwinding transformer balancing topology (MMTBT) for series-connected supercapacitors is proposed in this paper. With the proposed MMTBT, the voltage balancing inside modules and between modules are completely decoupled and the degree of modularization is high. This is different from the existing MMTBT, with the existing MMTBT, different modules share the same PWM drive. While with the proposed MMTBT, different modules can be driven by different PWM, then the variable frequency control strategy can be used to realize a fast balancing speed. With the proposed variable frequency control strategy, the average balancing current will be large and the balancing speed inside modules will be fast. With the proposed MMTBT, the balancing between modules is realized by discharging the higher voltage modules. The MMTBT of the higher voltage modules will act as a fly-back converter and the excitation current is in continuous current mode (CCM) to realize a great discharging power. First, the extra energy from the higher voltage module is transferred to the filter capacitor of the half-bridge converter. Then, the outputs of the half-bridge converters are connected in series to form a multilevel converter to act as the input of a boost converter. At last, the energy is transferred back to the supercapacitor energy storage system by the boost converter. The higher voltage module will be discharged with a great discharging power, then the balancing speed between modules will be fast. The fast balancing speed is realized inside modules and between modules, then the balancing speed of the whole system will be fast. The variable frequency control strategy and the control strategy of boost converter are analyzed in detail and the fast balancing speed of the proposed balancing topology is proved by experimental results. [ABSTRACT FROM AUTHOR]

Discontinuous modulation applied to modular multilevel converters is an effective method for reducing the capacitor voltage ripples. In this paper, the discontinuous modulation is adapted and used in a motor drive application. For proper operation of the converter, a new energy controller is presented, which is suitable for operation with nonsinusoidal reference signals. Experimental results comparing the discontinuous modulation with other techniques operating at low motor speeds are shown. The results demonstrate the effectiveness of the discontinuous modulation on reducing capacitor voltage ripples and power losses. [ABSTRACT FROM AUTHOR]

This paper presents a modified modular multilevel converter with the three-terminal middle-cells inserted between arms and ac-side for medium voltage applications. It is intended to reduce the submodule capacitor voltage ripples by controlling the high-frequency powers flowing among arm branches for low-frequency output operations without common-mode voltage injected in ac-side. Due to the physical connection among the upper arm, the lower arm and ac-side, the middle-cell can be regarded as the excess degree of freedom to modify the dc-side and ac-side characteristics. Therefore, the common-mode voltage in ac-side can be eliminated by the inverse common-mode voltage produced by the middle-cell in ac-side. Moreover, owing to the unique structure of the middle-cell, the middle-cell capacitor voltage also results in a small ripple due to the high-frequency current flowing into it by proper control. The operation principle and control strategy of the middle-cell has been proposed in detail. Simulation and experimental results have verified the effectiveness of the proposed topology. [ABSTRACT FROM AUTHOR]

This paper presents a novel single-stage, isolated, and single-phase dc–ac converter topology, suitable for low-medium power-scale solar photovoltaic and fuel-cell applications. The circuit employs two full-bridge cells with floating dc bus capacitors placed on either side of a high-frequency transformer and works on the dual-active-bridge principle. It has advantages of a single-stage power processing structure, low device count (uses eight switches), and the possibility of achieving zero-voltage-switching operation over the full ac line cycle. Moreover, by dynamic variation of phase-shift between the high-frequency primary and secondary voltages, twice-line-frequency energy buffering can be affected via the high-voltage side dc bus capacitor, which reduces decoupling capacitance requirement, enabling a film capacitor-based implementation. Basic operating principle, control strategy, and detailed design optimization guidelines of the circuit are described followed by simulation results to validate the approach. Practical evaluation of converter performance is done on a 250 W, 20–35 V input, and 110 V rms output prototype. [ABSTRACT FROM AUTHOR]

Modular multilevel converters (MMCs) represent an emerging topology in medium-voltage (MV) and high-voltage applications. But for MV variable-speed motor drives, the MMC faces the challenge of large capacitor voltage ripple at low speeds. Delightfully, a hybrid MMC (HMMC) has proved to be potential in MV motor drives, since this topology has a lower capacitor voltage ripple and does not introduce any common voltage to the motor. This paper proposed a method to decrease the average capacitor voltage of the HMMC, which can effectively drive the motor at very low speeds without significantly increasing the submodule (SM) capacitance. Moreover, the selection of average capacitor voltage and the dimension of the SM capacitance are presented. Simulation and experimental results verify the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

In this paper, in response to the open-circuit fault scenario in the grid-side converter (GSC) of doubly fed induction generator-based wind turbines (DFIG-WTs), a fault-tolerant four-switch three-phase (FSTP) topology-based GSC is studied. Compared with other switch-level fault-tolerant converter topologies, fewer switches, less switching and conduction losses, and simpler converter structure are derived. A simplified space vector pulse width modulation (SVPWM) technique is proposed to improve the output current quality and reduce the computational complexity in the control process. Unified expressions of duty ratios for the two remaining healthy bridge arms are obtained. In addition, the three-phase unbalance phenomenon caused by the capacitive impedance in the faulty phase is analyzed from the ac point of view, and a current distortion compensation scheme is illustrated. Furthermore, a dc-bus voltage deviation suppression strategy is proposed to maximize the dc-bus voltage utilization rate and mitigate the damage to the dc-link capacitors. Simulations are carried out in MATLAB/Simulink2017a to demonstrate the validity of the proposed SVPWM technique and compensation schemes in FSTP GSC for a 1.5-MW grid-connected DFIG-WT when different working conditions are considered. [ABSTRACT FROM AUTHOR]

In this paper, a novel integrated interleaved dual-mode time-sharing inverter (IIDMI) is proposed for grid-tied transformerless photovoltaic (PV) applications. While the dual-mode time-sharing conversion technique ensures minimum losses, the IIDMI also retains the advantages of interleaved topologies, such as low total harmonic distortion of the ac current with reduced filtering requirements, increased power density, and reduced current and thermal stresses of power devices. The leakage current problem, which is a main concern with the transformerless PV inverters, is solved by increasing the frequency of the main side band of the common-mode voltage above the resonance frequency of the common-mode impedance, while avoiding high switching losses. The current control, especially at transitions between the buck and the boost modes of operation, is highly improved by utilizing a fast-response deadbeat control scheme. The working principles of the IIDMI are explained in detail, and a 2.2-kW experimental prototype is implemented to confirm the theoretical achievements. [ABSTRACT FROM AUTHOR]

This paper presents a novel single-phase multicell converter for ac–dc power conversion, which is formed by a series connection of several full-bridge converter stages through passive components. The proposed topology employs a simple control scheme based on the carrier-based sinusoidal pulsewidth modulation technique. Detailed design procedure of the passive filter components are analyzed and discussed. An efficient optimization method based on a differential evolution algorithm is utilized to optimize the filter parameters. Considering the filter structure, active damping is introduced in the control scheme to improve the stability of the overall system, which is later verified by experiments. The systematic design approach of the controller parameter is also highlighted, focusing a specific set of goals. Experimental results for a 1-kW prototype are presented to further validate the concept. [ABSTRACT FROM AUTHOR]

A cascaded H-bridge (CHB) converter-based medium or high-voltage motor drive system, that consists of three single-phase CHB chains, may suffer a severe second-harmonic ripple power issue. Oversizing dc capacitors and using active power decoupling control with additional active or passive components are the two possible ways to address this issue, but this is achieved at the expense of increased system cost and complexity. This paper proposes a power decoupling control to tackle this issue without using any extra components for regenerative CHB-based converters. By introducing a set of negative-sequence decoupling currents to the front-end pulsewidth-modulated rectifier of each submodule, the second-harmonic ripple power can be removed from the submodule dc capacitors, and all the ripple power in the transformer core legs can be counteracted without affecting the magnetic flux and the grid current. The decoupling current is derived from the input and output measurements of the CHB converter. It gives the minimal increase of the modulation index and has no impacts on the input and output power quality. The effectiveness of the proposed control is verified in simulations and a 72-kW experimental prototype. [ABSTRACT FROM AUTHOR]

With the development of insulated gate bipolar transistor (IGBT) and pulsewidth modulation control strategy, the voltage source converter (VSC) is getting more and more popular, which can be used in high-voltage frequency converter, VSC-HVDC, FACTS, and custom power. In high voltage and high power applications, serial connection of IGBTs is a good solution to overcome the voltage limitation of the single IGBT. However, for using IGBTs in this way, a comprehensive range of issues need to be addressed, especially the static and dynamic voltage-sharing of each IGBT module. This paper presents the theoretical and practical study on how to use serial-connected IGBTs in a VSC, including adaptive dynamic voltage-balance strategy, voltage-balance circuit, power supply system, and valve vase electronics. A three-phase two-level VSC consisted of 6 arms multiplied by 12 serial-connected 3300 V IGBT modules is also developed. To test the performance of the VSC, pulse test of the one arm and inverter operation test of the whole VSC are carried out. The experimental results show that the maximum voltage imbalance is about 10%, the voltage shoots are less than 12%; and the VSC works stably, which indicates a solid foundation for industrial application. [ABSTRACT FROM AUTHOR]

A new class of impedance networks is proposed in this paper. The proposed coupled-inductors-based impedance cells, called the series and the tapped switched-coupled-inductors, are employed within the (quasi) switched boost networks. The achieved impedance networks based on the proposed cells offer very high conversion gains with less-than-unity turn ratios (n < 1), which simplifies the realization of the magnetic element and at the same time reduces the number and size of passive components. The high boosting capability is achieved with small shoot-through durations that bring some additional advantages, such as low ratings of switching devices. The circuit analysis and operation concepts as well as a design procedure for the components of the proposed impedance networks are presented. Theoretical achievements are confirmed through experiments on a 220 W dc–dc converter laboratory setup. [ABSTRACT FROM AUTHOR]

An adaptive control of DPWM implementable in clamped-three-level inverters with two strings of photovoltaic (PV) panels in cascaded connection is proposed in this paper. The proposed modulation is developed based on the so-called circuit-level decoupling concept. It is able to provide balance line voltage even under unbalanced dc links. The unequal dc voltages appeared due to asymmetric maximum point of power trackings (MPPTs) are controlled by proper injection of zero-sequence voltage to the common mode voltage, while the total dc voltage is regulated based on the voltage commands generated by the MPPT of each string. Thus, both PV strings are able to be operated based on their MPPTs while there is almost no low-order harmonic distortion at the inverter output current. Compared with the previous methods, the high capability of the proposed method is evaluated by simulation study and experimental tests. [ABSTRACT FROM AUTHOR]

A sawtooth carrier-based sinusoidal pulse width modulation (SC-SPWM) technique for asymmetrical six-phase two-level inverters is proposed in this paper, which could reduce both the peak-to-peak amplitude and the changing frequency of the common-mode voltage (CMV). The intersection-plotting method reveals that the mirror symmetrical sawtooth carriers for two three-phase groups can help optimize the distribution of overlapping areas, which is the CMV reduction mechanism of SC-SPWM. Additionally, the Fourier analysis is employed to quantitatively evaluate the modulation index and harmonic performance of SC-SPWM compared with the conventional SPWM and two phase-shifted SPWM methods. Also, further analysis demonstrates that dead time does not affect the reduction of CMV in a noticeable way. Finally, both simulation and experimental results coincide with the theoretical analysis that the proposed SC-SPWM shows the best performance in reducing the CMV amplitude and changing frequency among these four SPWM methods, though it leads to a higher phase current distortion. [ABSTRACT FROM AUTHOR]

This paper presents a single-inductor multiple-input single-output (SI-MISO) boost converter with a deadbeat-based control method. The proposed deadbeat-based control has the capability to simultaneously conduct the power regulation from multiple inputs and the output voltage regulation for the SI-MISO boost converter. The advantages of the proposed method are less component count, lower system cost, compatibility for arbitrary number of inputs, fast response, and simplicity for implementation. Hence, the SI-MISO boost converter is a promising interface for the regulation of multiple energy sources as a standalone power system, which can be utilized in electric vehicle applications. To verify the performance of the proposed deadbeat-based control method, a laboratorial prototype of the SI-MISO boost converter is built. The steady-state and dynamic operations are investigated based on the prototype. The experimental results demonstrate that input power and output voltage of the SI-MISO boost converter can be effectively regulated by the proposed control method. The comprehensive comparison with the existing methods is conducted to further illustrate the advantages of the proposed deadbeat-based method. [ABSTRACT FROM AUTHOR]

This paper investigates an ac–dc–ac multilevel power converter. The studied configuration is composed of two single-phase ac–dc–ac three-leg modules and series-connected H-bridges in the shared part of system. Because the proposed converter has shared legs between the input and output, it is employed in applications with same input and output frequency. Uninterrupted power supply and unified power quality conditioner are application examples for this converter. Such multilevel topology has lower dc-link voltage rating, which, consequently, presents low switch blocking voltages when compared to conventional topologies. System model, a space-vector pulsewidth modulation (PWM) strategy to symmetrical and asymmetrical dc-link voltages, and an overall control strategy to adjust the system variables are presented. A power flux analysis shows the operation zone in which the individual dc-link voltage balancing is possible. PWM and control strategies are developed to reduce the semiconductor total losses, harmonic distortion, and switching stress. Two ac–dc–ac multilevel conventional structures are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

This paper investigates a multilevel inverter composed of series/parallel-connected H-bridges. The presented structure can be used for applications in which the use of semiconductor switches with low-voltage and low-current ratings is intended. A comprehensive system model, an overall control strategy to adjust the output voltage with constant magnitude and frequency, and a level-shifted PWM (LS-PWM) strategy based on a voltage vectors unidimensional analysis and a plane analysis are presented. The LS-PWM is capable of mitigating the low-frequency circulating current, thus generating multilevel voltage signals with low harmonic distortion, maximum number of levels, and low dv/dt. In addition, considering a wide range of values of voltages and currents and various power levels, the total converter losses are reduced compared with the conventional multilevel converters. Two multilevel conventional inverters with the same number of semiconductor switches are used for comparison. Simulation and experimental results demonstrate the feasibility of the studied converter. [ABSTRACT FROM AUTHOR]

This paper presents a nine-level transformer-based inverter requiring only eight switches. The envisaged structure consists of two standard H-bridges fed from a single dc source. Besides, a single-phase transformer is employed to aid the process of intermediate voltage level generation. An ad-hoc pulsewidth modulation scheme based on boolean logic form equations is developed to derive the gating pulses. An effortless extension of the proposed inverter to a higher number of voltage levels is also achieved by generalizing the switching functions. Furthermore, the superior performance of the proposed topology is demonstrated through a comprehensive cost-based analysis. Finally, the validation of the proposed topology is accomplished through experiments on a down-scale prototype, and the measurement results are included. [ABSTRACT FROM AUTHOR]

Hybrid boost converter (HBC) has been proposed to replace a dc/dc boost converter and a dc/ac converter to reduce conversion stages and switching loss. In this paper, control of a three-phase HBC in a Photovoltaic (PV) charging station is designed and tested. This HBC interfaces a PV system, a dc system with a hybrid plug-in electrical vehicles, and a three-phase ac grid. The control of the HBC is designed to realize maximum power point tracking for PV, dc bus voltage regulation, and ac voltage or reactive power regulation. A testbed with power electronics switching details is built in MATLAB/SimPowersystems for validation. Simulation results demonstrate the feasibility of the designed control architecture. Finally, lab experimental testing is conducted to demonstrate HBC's control performance. [ABSTRACT FROM AUTHOR]

To enhance the redundancy and reliability for a distributed generation system, a grid-tied photovoltaic (PV) generation system based on series-connected module-integrated inverters (SC-MIIs) is presented in this paper. In the grid-tied SC-MII system, each PV panel is interfaced with an MII with independent maximum power point tracking to harvest maximum solar energy. The outputs of MIIs are at ac line frequency and are connected in series to fulfill the voltage requirement in the utility grid. Since the high step-up power conversion stage in the conventional microinverter is avoided, the grid-tied SC-MII system is easier to implement and features high efficiency. Meanwhile, a distributed control strategy for SC-MIIs is proposed, in which the active power sharing among the MIIs depends on the individual maximum power available from PV panels, while the reactive power of the system can be regulated by any of the MIIs according to the utility grid command. Simulation and experimental results verify the feasibility and effectiveness of the proposed system and its corresponding control strategy. [ABSTRACT FROM AUTHOR]

This paper proposes a zero-sequence circulating current (ZSCC) control scheme for the multiparalleled three-level T-type inverters (3LT2Is). Based on the analysis with the proposed generalized model of multiparalleled 3LT2Is, it is seen that the ZSCC is influenced by the circuit parameters, duty cycles, and the circulating currents of the l th and first 3LT2I. To mitigate the circulating currents, a deadbeat control strategy for n-paralleled (n≥3) inverters is proposed, which is realized by adjusting the duty cycle of the small vectors in each PWM sampling period. Compared with the conventional PI control method, the ZSCC spike is mitigated with the proposed scheme, thus improving the quality of the output currents. Also, the reliability of the 3LT2Is system is improved because such a scheme only needs the information about the ZSCC and zero-sequence duty ratio in the l th and the first inverter. The proposed method can also be applied to the neutral-point-clamped converters. Simulation and experimental results verify the effectiveness of the theoretical analysis and the proposed method. [ABSTRACT FROM PUBLISHER]

This paper presents the active capacitor voltage-balancing (ACVB) methods based on the dynamic model for a five-level nested neutral-point piloted (NNPP) converter using hybrid carrier modulation. The traditional hybrid carrier modulation provides natural voltage balancing of floating capacitors and dc-link capacitors. First, the natural voltage-balancing ability under steady-state and ideal conditions is theoretically proved. However, there are accumulated errors and deviations of capacitor voltages in practical applications, especially under dynamic conditions. In order to address the accumulated errors and deviations of capacitor voltages, the dynamic models of floating-capacitor voltages and neutral-point voltage are established. Moreover, the ACVB method based on the dynamic model of the neutral-point voltage is proposed by injecting the zero-sequence voltage. And the ACVB method based on the dynamic model of floating-capacitor voltages is proposed by introducing the adjustment variables. The proposed ACVB methods have the advantages of simple formula, definite physical meaning, and high accuracy. Furthermore, the output voltage quality and current quality are evaluated in term of total harmonic distortion and the effect of model parameter mismatch on the proposed ACVB methods is presented. Finally, the comparative simulation and experimental results verify the correctness of the proposed ACVB methods based on the dynamic model under different conditions. [ABSTRACT FROM AUTHOR]

This paper investigates power shunt filter topologies composed of three standard three-leg converters applied in either three or four-wire system. Compared with the usual three-phase shunt filter, the proposed ones allow us to reduce dc-link voltages, harmonic distortion or/and the semiconductor losses, and fault tolerant operation. Suitable control strategies to adjust filter and circulating currents, as well as the three dc-link voltages are presented. Two pulse-width modulation techniques are developed for the proposed topologies in order to achieve the best voltage-pulse pattern. Comparisons between these techniques are carried out in this paper. Simulation and experimental results are presented to validate the theoretical approach. [ABSTRACT FROM PUBLISHER]

A new pulsewidth modulation (PWM) strategy which is an alternative approach of the discontinuous PWM (DPWM) for a three-level neutral-point-clamped (NPC) inverter is proposed in this paper. A three-level NPC inverter is completely mature and very well-established topology in high-power applications. However, the three-level NPC inverter has an inheritance problem of the neutral-point voltage unbalancing due to the split dc-link capacitors. This structure can cause large neutral-point voltage ripple. Furthermore, output currents of the three-level NPC inverter are distorted by the neutral-point voltage ripple. Therefore, the neutral-point voltage must be controlled. In this paper, a new DPWM method using two different offsets for the neutral-point ripple reduction is proposed and the effectiveness of the proposed DPWM method is verified by using the simulation and the experimental results. [ABSTRACT FROM PUBLISHER]

This paper presents a topology of a single-phase floating full-bridge three-level pulse width modulation (PWM) power inverter suitable for high-voltage/high-power dc–ac conversion. High power efficiency is obtained thanks to the slow (50/60 Hz) biasing of the H-bridge power supply terminals, allowed by a particular arrangement and control of two complementary active neutral point clamped voltage-source converters. As result, the main PWM switching voltage as well as the maximum drain–source voltage $V_{{\rm DSS}} of related transistors are reduced to one-half of the input VDD voltage. This is allowed by the internally generated and accurately balanced middle-node voltage VDD/2. Consequently, advantageous $r_{{\rm DS}({\rm on})}$ of the low-voltage transistors, along with reduced switching PWM voltage result in considerable decreasing of power losses in whole output power range. This paper introduces the main concept of the floating H-bridge topology, and presents in detail the circuit realization. The performances are demonstrated on $450 V_{{\rm DC}}/230 V_{{\rm AC}}$ 2 kW power inverter exhibiting 98.6% peak efficiency and realized in very small $100\times 60\times 30$ mm3 volume. [ABSTRACT FROM AUTHOR]

Modulation schemes can significantly change the performance of a converter in the steady state. They have, thus, been extensively studied, but directed more at three-phase topologies, where triplen offsets are added. Single-phase systems, including ac–dc–ac, are less widely pursued, even though various topologies have since been proposed. The intention of this paper is, thus, to study two promising single-phase ac–dc–ac converters using reduced number of switches, and subsequently proposes modulation schemes for them. The proposed schemes help the converters to achieve better thermal spread among their switches, while keeping their dc-link voltages low. Single points of failure are thus minimized, allowing the converters to have longer lifetimes. Simulation and experimental results have demonstrated the intended performances, hence verifying the analyses presented in this paper. [ABSTRACT FROM PUBLISHER]

This paper presents an improved dc-link voltage balancing algorithm for a three-level neutral-point-clamped inverter by considering phase current direction. Detailed studies on the effects of change in load current direction on the dc-link capacitor voltages are presented. A maximum value of power factor is numerically derived, above which it affects the capacitor voltage balancing capability. Compared with the previously presented research work, the inputs to the space-vector pulsewidth-modulation block are the three phase currents and the difference between the two capacitor voltages. Depending on the states of the two dc-link capacitor voltages and phase current direction, redundant voltage vector sequences are selected. The selected vectors keep the capacitor voltage deviations within 5% of the total dc-link voltage. Two zero switching vectors (i.e., PPP and NNN) are also removed from all subsectors of the earlier proposed strategy, which one used to produce higher common-mode voltages. Detailed simulation and experimental results are presented in this paper for a 6.0-kW surface permanent-magnet synchronous machine. Both the simulation and experimental results show the required performance of the proposed system. [ABSTRACT FROM AUTHOR]

A four-level five-phase open-end winding (OeW) drive topology is introduced in this paper. The drive comprises a five-phase induction machine with open-end stator windings, supplied using two two-level voltage-source inverters with isolated and unequal dc-link voltages, in the ratio 2 : 1. The topology offers the advantages of a modular structure with fewer semiconductor components and has a greater potential for fault tolerance, as compared with an equivalent single-sided four-level drive. Due to the large number of switching states, development of a suitable space vector pulsewidth-modulation (PWM) method can be challenging. Hence, this paper examines the implementation of two-level-shifted carrier-based PWM methods. The effect of dead time on the drive performance is discussed, and it is shown that simultaneous PWM switching of both inverters can lead to degraded output phase voltage waveforms. Detailed analysis of this phenomenon is presented, a solution is proposed, and the modified modulation techniques are incorporated in an experimental setup, at first in conjunction with $V/f$ control. Once the proof of concept has been provided, full field-oriented control is implemented in this OeW drive topology for the first time; detailed experimental testing is conducted, and results are reported. [ABSTRACT FROM AUTHOR]

Multiphase variable-speed drives and generation systems (systems with more than three phases) have become one of the mainstream research areas during the last decade. The main driving forces are the specific applications, predominantly related to the green agenda, such as electric and hybrid electric vehicles (EVs), locomotive traction, ship propulsion, “more-electric” aircraft, remote offshore wind farms for electric energy generation, and general high-power industrial applications. As a result, produced body of significant work is substantial, making it impossible to review all the major developments in a single paper. This paper therefore surveys the recent progress in two specific areas associated with multiphase systems, namely power electronic supply control and innovative ways of using the additional degrees of freedom in multiphase machines for various nontraditional purposes. [ABSTRACT FROM AUTHOR]

Multilevel inverters have created a new wave of interest in industry and research. While the classical topologies have proved to be a viable alternative in a wide range of high-power medium-voltage applications, there has been an active interest in the evolution of newer topologies. Reduction in overall part count as compared to the classical topologies has been an important objective in the recently introduced topologies. In this paper, some of the recently proposed multilevel inverter topologies with reduced power switch count are reviewed and analyzed. The paper will serve as an introduction and an update to these topologies, both in terms of the qualitative and quantitative parameters. Also, it takes into account the challenges which arise when an attempt is made to reduce the device count. Based on a detailed comparison of these topologies as presented in this paper, appropriate multilevel solution can be arrived at for a given application. [ABSTRACT FROM AUTHOR]

This paper proposes a modular isolated dc–dc converter, based on the input-series and output-series association of the full-bridge PWM dc–dc converter with capacitive filter. The main attribute of the proposed architecture is its ability to provide self-balance of the input and output voltages across the individual converters, without voltage loop control scheme, both in the steady-state and transient operations. Circuit operation, theoretical analysis, and modeling are included in this paper, along with experimental results taken from a laboratory prototype with four modules, 1600-Vdc total input voltage, 1600-Vdc total output voltage, 4-kW output power, and 40-kHz switching frequency. Possible applications include high-voltage power supplies, solid-state transformers, dc current distribution systems, and renewable electric energy systems. [ABSTRACT FROM PUBLISHER]

A multilevel inverter topology for a four-pole induction-motor drive is presented in this paper, which is constructed using the induction-motor stator winding arrangement. A single dc source with a less magnitude when compared with conventional five-level inverter topologies is used in this topology. Therefore, power balancing issues (which are major challenges in conventional multilevel inverters) are minimized. As this configuration uses a single dc source, it provides a path for zero-sequence currents because of the zero-sequence voltages present in the output, which will flow through the motor phase winding and power electronic switches. To minimize these zero-sequence currents, sine–triangle pulsewidth modulation (SPWM) is used, which will shift the lower order harmonics near to switching frequency in the linear modulation region. However, in the case of overmodulation, harmonic voltages will be introduced close to the fundamental frequency. In this regard, a modified SPWM technique is proposed in this paper to operate the drive in the overmodulation region up to the modulation index of 2/\!\surd3. The proposed quad two-level inverter topology is experimentally verified with a laboratory prototype on a four-pole 5-hp induction motor. Experimental results show the effectiveness of the proposed topology in the complete linear modulation region and the overmodulation region. [ABSTRACT FROM PUBLISHER]

Multilevel inverters with dodecagonal (12-sided polygon) voltage space vector structure have advantages, such as complete elimination of fifth and seventh harmonics, reduction in electromagnetic interference, reduction in device voltage ratings, reduction of switching frequency, extension of linear modulation range, etc., making it a viable option for high-power medium-voltage drives. This paper proposes two power circuit topologies capable of generating multilevel dodecagonal voltage space vector structure with symmetric triangles (for the first time) with minimum number of dc-link power supplies and floating capacitor H-bridges. The first power topology is composed of two hybrid cascaded five-level inverters connected to either side of an open-end winding induction machine. Each inverter consists of a three-level neutral-point-clamped inverter, which is cascaded with an isolated H-bridge making it a five-level inverter. The second topology is for a normal induction motor. Both of these circuit topologies have inherent capacitor balancing for floating H-bridges for all modulation indexes, including transient operations. The proposed topologies do not require any precharging circuitry for startup. A simple pulsewidth modulation timing calculation method for space vector modulation is also presented in this paper. Due to the symmetric arrangement of congruent triangles within the voltage space vector structure, the timing computation requires only the sampled reference values and does not require any offline computation, lookup tables, or angle computation. Experimental results for steady-state operation and transient operation are also presented to validate the proposed concept. [ABSTRACT FROM PUBLISHER]

This paper presents a voltage-source converter (VSC) topology for high-power applications. This topology combines three three-phase converters with isolated dc buses. The proposed topology can be implemented by using two-level or multilevel three-phase converters. In this paper, three three-level neutral-point-clamped (3L-NPC) converters have been combined. Two zero-sequence blocking transformers (ZSBTs) are used to interconnect the three converters. In order to validate the good performance of the proposed VSC topology, two modulation techniques are implemented: phase-shifted carrier pulsewidth modulation (PSCPWM) and selective harmonic elimination (SHE) modulation. The VSC topology has been simulated in the simulation tool Saber, and the results have been validated experimentally in a test bench of 60 kVA. [ABSTRACT FROM PUBLISHER]

This paper proposes a solution for reducing the ground leakage current in transformerless single-phase grid-connected photovoltaic converters. This is obtained with the introduction of an active common-mode filter able to compensate for variations of the output common-mode voltage of the power converter. The active common-mode filter is applied to a widespread and efficient full-bridge driven by a three-level pulse width modulation, allowing the power converter to operate with low ground leakage current and with an arbitrary power factor. After showing the desired voltage waveform for common-mode voltage compensation, this paper presents the design guidelines for the needed additional magnetic component together with the power loss considerations for all the devices added for the proposed solution. Experimental results show the performance of the proposed solution in terms of ground leakage current reduction, effectiveness of dead-time compensation, total harmonic distortion of the injected grid current, and power losses. [ABSTRACT FROM PUBLISHER]

Microgrid-interactive converters are increasingly expected to provide auxiliary services, particularly during islanded microgrid operation. Unbalanced, non-sinusoidal pulse width modulation (PWM) references may be required when converters provide auxiliary services, such as negative-sequence compensation. Since PWM references cannot exceed dc-bus voltage defined limits without causing overmodulation, the maximum positive-sequence voltage producible by microgrid-interactive converters may be diminished unless reference waveforms are adjusted. In this paper, a technique for maximizing the linear modulation region by injecting a common mode component into PWM references is proposed for microgrid-interactive cascaded H-bridge (CHB) converters. The technique presented can be implemented in real-time without lookup tables, is controller independent, is compatible with any carrier-based PWM method, enabling its use for symmetric and asymmetric CHB, and enables continued operation after internal fault events when utilized with fault tolerant PWM schemes. Experimental data verify the common mode injection technique. [ABSTRACT FROM PUBLISHER]

This paper proposes a switched-capacitor multilevel inverter for high-frequency ac power distribution systems. The proposed topology produces a staircase waveform with higher number of output levels employing fewer components compared to several existing switched-capacitor multilevel inverters in the literature. This topology is beneficial where asymmetric dc voltage sources are available, e.g., in case of renewable energy farms based ac microgrids and modern electric vehicles. Utilizing the available dc sources as inputs for a single inverter solves the major problem of connecting several inverters in parallel. Additionally, the need to stack voltage sources, like batteries or supercapacitors, in series which demand charge equalization algorithms, are eliminated as the voltage sources employed share a common ground. The inverter inherently solves the problem of capacitor voltage balancing as each capacitor is charged to the value equal to one of the input voltage every cycle. State analysis, losses, and the selection of capacitance are examined. Simulation and experimental results at different distribution frequencies, power levels, and output harmonic content are provided to demonstrate the feasibility of the proposed multilevel inverter topology. [ABSTRACT FROM PUBLISHER]

This paper proposes a pulse width modulation plus phase-shift (PPS) control for nonisolated high gain soft-switching bidirectional dc–dc converter (HSBDC). The phase-shift angle is used to control the direction and amount of power flow of the bidirectional dc–dc converter, while the duty cycle is used to balance the voltage between two high voltage side (HVS) capacitors. The HSBDC with PPS control has the advantages of simple control structure and symmetrical switching patterns, ensured soft-switching in both forward and backward modes at all load under wide voltage range, and reduced voltage ratings of the HVS capacitors and switches. The operation principle of the HSBDC with PPS control is analyzed in detail. Based on the analysis the passive component is designed to achieve higher efficiency. A 3-kW prototype is implemented and tested to verify the validity of the proposed method. [ABSTRACT FROM AUTHOR]

The noninverting buck–boost converter has attracted significant attention in the photovoltaic (PV) module integrated application, as it offers high efficiency while maintaining a low cost and a simple topology. When this converter is employed, special care must be taken at the transition between buck and boost operating modes, as a dead-zone in the voltage transfer function can cause abrupt perturbations in the controlled voltage, decreasing the regulation quality and ultimately lowering the power conversion efficiency. In this paper, a new dead-zone compensation technique is proposed with the scope of smoothing the transition between operating modes, eliminating the voltage ripple and improving the regulation performance, while maintaining high efficiency. The converter under analysis is studied together with its gate driving circuit, which is based on a bootstrap capacitor power supply for the high-side switches. The proposed dead-zone compensation technique is deduced by using the principle of maintaining the ideal voltage gain function across the converter operating range. The technique is analyzed, implemented and tested on a purposely built PV module integrated noninverting buck–boost converter. The experiments reveal a sensible improvement of the voltage regulation during mode transition, confirming the effectiveness of the proposed technique and its fitness for the PV application. [ABSTRACT FROM AUTHOR]

Five-level hybrid-clamped (5L-HC) converter is a newly proposed topology which is suitable for high-performance medium-voltage high-power conversions without switches directly connected in series. The critical issue of this converter is that two flying capacitor voltages of each phase and two neutral-point potentials of the dc-link need to be balanced. This paper presents a decoupled voltage balancing method for this 5L-HC converter based on modified phase-shifted pulse width modulation (PS-PWM) and optimal zero-sequence voltage injection. The voltages across the central dc-link capacitor and two flying capacitors are balanced first by adjusting the width of four PWM signals. Second, the relationship between the neutral-point currents and the output phase voltage is studied and the upper and lower dc-link capacitor voltages are balanced by zero-sequence voltage injection. Both steady-state and dynamic-state simulation and experimental results are presented to confirm the validity of this method. [ABSTRACT FROM AUTHOR]

This paper presents two topologies of three-phase semicontrolled rectifiers suitable for open-end ac power sources. The rectifiers are composed of a combination of two-level three-phase bridges (controlled, semicontrolled, or uncontrolled) and three single-phase floating capacitor h-bridges (controlled). These topologies generate two powered dc-links, each one belonging to a three-phase bridge. They present a reduced number of controlled power switches if compared with other open-end configurations of similar complexity found in the literature. It is also proposed a space-vector pulse-width modulation (SV-PWM) approach and a method of floating capacitor voltage control dedicated to the topologies with an equivalent approach based on the level-shifted PWM (LS-PWM). The proposed SV-PWM solving method is based on a redundant state selection (RSS) technique, which allows the floating capacitors voltage regulation. On the other hand, the LS-PWM solving method is based on the neutral voltage selection, which is shown to be equivalent to the SV-PWM RSS technique seen from the control system. Simulation results are shown to validate proposed topologies, as well as the SV-PWM and LS-PWM techniques, and the control strategy. Experimental results are shown to demonstrate proposed configurations feasibility. [ABSTRACT FROM PUBLISHER]

This paper presents the development and performance evaluation of the wavelet modulation technique for single-phase ($1\phi$) cascaded $H$-bridge (CHB) multilevel dc–ac power electronic converters (PECs). The developed technique is based on employing sets of resolution-segmented wavelet basis functions as switching signals, where each set operates one $H$ -bridge. The number of sets of wavelet basis functions is selected to match the number of levels in the output voltage of the $1\phi$ CHB dc–ac PEC. The wavelet modulation for $1\phi$ CHB multilevel dc–ac PECs is implemented for performance evaluation both in simulation and experimentation. The performance of the developed technique is evaluated for linear, nonlinear, and dynamic loads. Simulation and experimental results show significant reduction of output harmonics, along with high magnitude of the fundamental component in the output voltage. The improvements offered by the wavelet modulation technique are further demonstrated through comparisons with the level-shifted and phase-shifted pulse-width modulation techniques under similar loading conditions. [ABSTRACT FROM PUBLISHER]

This paper discusses a variety of four-wire (4W) multilevel shunt compensators to deal with either harmonic or reactive power compensation. The converter configurations are generalized for K-stages and the main benefits of the proposed topologies lie on multilevel waveforms generation, single dc-link unit, and modular characteristic. The configurations are based on cascaded transformers along with three-phase-bridge converters. These converters are directly connected to the transformer primary side. A suitable pulse-width modulation strategy combined with an appropriate transformer turns ratio guarantees the desired multilevel output waveforms. The modularity feature provides simple maintenance and makes the proposed shunt active power filters an attractive solution in comparison with conventional configurations. The configuration model and overall control are addressed as well. Simulation and experimental results are presented for theoretical validation. [ABSTRACT FROM PUBLISHER]

This paper discusses the use of a cascaded multilevel converter for flexible power conditioning in smart-grid applications. The main feature of the proposed scheme is the use of independent dc links with reduced voltages, which makes such a topology an ideal candidate for medium- and high-power applications with increased reliability. The developed control strategy regulates independent dc-link voltages in each H-bridge cell, and allows the selective and flexible compensation of disturbing currents under a variety of voltage conditions without requiring any reference frame transformation. The selective control strategies are based on the decompositions proposed in the conservative power theory, which result in several current-related terms associated with specific load characteristics. These current components are independent of each other and may be used to define different compensation strategies, which can be selective in minimizing particular effects of disturbing loads. Experimental results are provided to validate the possibilities and performance of the proposed control strategies, considering ideal and deteriorated voltage conditions. [ABSTRACT FROM PUBLISHER]

High-voltage direct current (HVdc) grid which incorporates multiple dc transmission lines will have extensive application since it has better operating flexibility and enhances the power trade. DC/DC converters are important components in the HVdc grid. The buck/boost modular multilevel dc/dc converter (MMDCC), which uses half-bridge submodules to reduce the voltage stresses across the power switches, is a good choice for the nonisolated applications in the HVdc grid. This paper proposes a pulse width modulation (PWM) control scheme for the buck/boost MMDCC, which uses much smaller submodule capacitors than those in the existing phase-shifted (PS) control scheme, thus reducing the converter volume and weight significantly. The operating principle of the proposed PWM control scheme is elaborated, along with the submodule capacitor voltage balancing strategy and the closed-loop control flowchart. Besides, the capacitance requirement of the buck/boost MMDCC in the PWM control scheme is calculated and compared to that in the PS control scheme, showing a dramatic reduction. The reason for the capacitance requirement difference of the two schemes is also explained. Simulation and experimental results validate the effectiveness of the proposed PWM control scheme and its ability to reduce the submodule capacitance. [ABSTRACT FROM AUTHOR]