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An integrated reconfigurable CMOS quasi-circulator operating at 2.4 GHz is presented. A passive structure delivers transmit power amplifier (PA) output signal to the differential low-noise amplifier (LNA) input as a common-mode signal and simultaneously delivers received signal as a differential-mode signal at the LNA input. The leakage of the PA output signal at the LNA input is reduced in two steps. First, the use of a reconfigurable impedance matching circuit, instead of a fixed 50- $\Omega $ resistance reduces the leakage by compensating the antenna impedance mismatch, and improves transmitter–receiver isolation. Second, a reconfigurable summing stage adds amplitude and phase adjusted PA output signal to LNA output to cancel the residual PA output leakage. Measurement results show that the receiver achieves a reduction of 90 dB for a single tone and more than 50 dB for a QPSK modulated 40-MHz bandwidth transmit signal. The receiver gain is more than 10 dB and the noise figure in the receiver path is 4.5 dB. The reconfigurable quasi-circulator along with the receiver LNA is designed and fabricated on a 130-nm CMOS technology. The cancellation circuitry occupies 0.27 mm2 and consumes 30-mW quiescent power, while the total active area of the chip is 1 mm2, and it consumes 65-mW power. [ABSTRACT FROM PUBLISHER]

A low-power transceiver for medical implant communication service is presented. The device consists of three subsystems, which perform wake-up signal reception, data-link binary frequency-shift keying (BFSK) reception, and transmission, respectively. A common antenna interface is reused in the three subsystems, reducing circuit complexity and number of external components. Super-regenerative architecture is used for wake-up reception, and gm-boosted common-gate stages are used to optimize receiver (RX) performance with low power consumption. The transmitter employs an all-digital frequency-locked loop to directly drive a class AB power amplifier. The transmitter can alternatively use an injection-locked power oscillator for lower bit rates and power consumption. The integrated circuit is designed and fabricated on a 0.18-\mu\m CMOS process. The wake-up RX achieves a -80-dBm sensitivity for a 50-kb/s signal and a 280-\mu\W dissipation. The BFSK RX achieves a -97-dBm sensitivity for a 75-kb/s signal and a 2-mW power consumption. Finally, the transmitter achieves an output power of -5 dBm for a power consumption of 2.9 mW. [ABSTRACT FROM AUTHOR]

Several wireless biomedical transceivers, including medical implants communication systems (MICSs), require ultra-low-power low-complexity frequency synthesizers. This paper presents an all-digital frequency-locked loop (ADFLL)-based frequency synthesizer with a built-in frequency-shift keying modulator for MICS and industrial–scientific–medical band applications. Unlike all-digital phase-locked loops that rely on a power-hungry time to digital converter, the proposed ADFLL employs a high-resolution single-bit \Sigma \Delta frequency discriminator in the feedback path and a noise-cancelling \Sigma \Delta phase-accumulator-based frequency controller in the reference path, achieving fractional resolution with low power consumption. The loop compensation is implemented digitally using an infinite impulse response filter followed by a digital-intensive current-steering DAC driving a ring-oscillator-based voltage-controlled oscillator. The ADFLL achieves 9.5-Hz frequency resolution, spanning the ISM 400–410-MHz band. A worst case near-integer spur of -\62 dBc and a phase noise of -\83 dBc/Hz at 300-kHz offset are measured. The ADFLL is fabricated on a \0.18-\mu\ m CMOS process, occupying a \ 0.14-mm^2 die area, with a quiescent current consumption of \700~\mu\ A. [ABSTRACT FROM AUTHOR]

Abstract: This paper describes the state-of-the-art design approaches to delta-sigma (ΔΣ) frequency synthesizers for wireless transceiver applications. Various synthesizer architectures, including the integer and fractional-N synthesizers, and frequency-to-digital converters (FDC) based digital frequency synthesizers are described. Design specifications for several loop parameters such as noise shaper order in the feedback modulator, loop filter bandwidth, VCO phase noise are based on modulation accuracy and frequency resolution specifications. Advantages of digital loop filter based ΔΣ frequency synthesizers are analyzed. [Copyright &y& Elsevier]