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We developed an optical input module consisting of built-in metal-semiconductor-metal photodiodes (MSM-PDs) and co-planar waveguide transmission lines fabricated on an InP substrate, which is flip-chip bonded with a single-flux-quantum (SFQ) circuit fabricated on a Si substrate. To improve photosensitivity of the MSM-PD for a wavelength above 1530 nm at 4 K, we tested the MSM-PDs made of lattice mismatched In1-xGa_xAs films on InP substrates. By employing In1-xGa_xAs with x=0.44, an apparent reduction of photosensitivity for a wavelength above 1530 nm was suppressed. We also tested newly designed DC/SFQ converters with higher input current sensitivities. The observed current sensitivity was improved to 41 \muA, while that in the conventional DC/SFQ converter was 140 \muA. [ABSTRACT FROM AUTHOR]

A pipelined 8-bit-serial single-flux-quantum (SFQ) microprocessor, called CORE1β, was designed and tested. The CORE1β has two cascaded arithmetic logic units (ALUs) based on forwarding architecture, which can perform two register operations from one instruction. Pipelining is also extensively adopted to enhance the performance. A new design method, known as one-hot encoding, has been introduced into the design of the control circuit. The 4-stage-pipelined SFQ microprocessors, CORE1β8, have been implemented using the CONNECT cell library and the SRL 2.5 kA/cm2 Nb process. The frequency for the instruction fetch is 25 GHz, and 20 GHz for the bit-serial data operation. The peak performance and the power consumption of the CORE1β8 are estimated to be 1400 MOPS (million instructions per second) and 3.4 mW, respectively. We have experimentally demonstrated 4-stage pipelining and all functionalities of the CORE1β8 microprocessors by on-chip high-speed tests. [ABSTRACT FROM AUTHOR]

With regard to sustaining future capacity of network traffic, the current hardware technology has a big bottleneck in terms of power consumption and insufficient operation speed. To overcome this bottleneck, we have developed a single flux quantum (SFQ) packet-switching circuit. We report recent progress in developing the SFQ packet-switching application. First, we demonstrate a 40 GHz, 160 Gb/s, 4 × 4 packet switching circuit, which is currently the fastest clock frequency reported packet switch. Then, we describe a currently possible switching module using SFQ technology. Finally, we consider how SFQ technology can be used to scale the packet-switching capacity up to 100 Tbps. [ABSTRACT FROM AUTHOR]

We have been investigating a design methodology of SFQ logic circuits based on the binary decision diagram (BDD). In the previously proposed BDD SFQ logic circuits, we have used one-to-two binary switches as a node cell in a BDD tree. In this study we will propose a new implementation method of SFQ BDD circuits, in which two nodes are implemented by using a 2-input 2-output switch gate. By employing the new approach, we have designed and implemented a one-bit full adder using the NEC 2.5 kA/cm² Nb standard process and the CONNECT cell library. The maximum operating frequency of the full adder was found to be 40 GHz by circuit simulations and 32.8 GHz by on-chip high- speed tests. [ABSTRACT FROM AUTHOR]

Abstract: We have demonstrated the components of datapath toward single-flux-quantum microprocessors based on our new architecture called the forwarding architecture. In the forwarding architecture, we improve the performance by utilizing multiple ALUs to conceal the inefficiency of bit-serial processing. The key components of the datapath are a register file and cascaded ALUs. We have designed the register file to hold four bit-serial data with two read ports and one write port. In each ALU, we have implemented six functionalities: addition, subtraction, logical AND, OR and Exclusive OR operations, and comparison with zero. We have tested the register file and the ALU using high-speed on-chip testing, and confirmed the correct operations up to 18GHz and 23GHz, respectively. [Copyright &y& Elsevier]

Abstract: We have designed, fabricated and tested a time-to-digital converter (TDC) using SFQ logic circuits. The proposed TDC consists of two sets of ring oscillators and binary counters, and a coincidence detector (CD), which detects the coincidence of the arrival of two SFQ pulses from two ring oscillators. The advantage of the proposed TDC is its simple circuit structure with wide measurement range. The time resolution of the proposed TDC is limited by the resolution of the CD, which is about 10ps because it is made by an NDRO cell in this study. The circuits are implemented using NEC 2.5kA/cm2 Nb standard process and the CONNECT cell library. We have demonstrated the measurement of the propagation delay of a Josephson transmission line by the TDC with the time resolution of about 10ps. [Copyright &y& Elsevier]

Abstract: In this paper we have considered how to perform logic synthesis of the single-flux-quantum (SFQ) logic circuits by using logic synthesis tools for semiconductor logic circuits. Fundamental difference of the SFQ logic gates from the semiconductor logic gates in terms of logic synthesis is that typical SFQ gates are clocked gate, where gates have to be clocked by SFQ pulses. In our approach, we divided the procedure into two steps; logic synthesis and clock distribution. In the logic synthesis step, the logic function is optimized using a logic synthesis tool without considering the clock network. The Design Analyzer provided from Synopsys is used in this study. We have developed an SFQ cell library for the logic synthesis. In the clock distribution step, clock networks for every clocked SFQ gates are designed taking account of timing. We used a clock-followed-data clocking scheme in this study. We have classified every clocked gate into stages, where the clocked gates in the same stage are clocked simultaneously. To demonstrate the validity of our approach, we have designed a controller of an 8-bit SFQ microprocessor. [Copyright &y& Elsevier]