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We developed an optical input module consisting of built-in metal-semiconductor-metal photodiodes (MSM-PDs) and co-planar waveguide transmission lines fabricated on an InP substrate, which is flip-chip bonded with a single-flux-quantum (SFQ) circuit fabricated on a Si substrate. To improve photosensitivity of the MSM-PD for a wavelength above 1530 nm at 4 K, we tested the MSM-PDs made of lattice mismatched In1-xGa_xAs films on InP substrates. By employing In1-xGa_xAs with x=0.44, an apparent reduction of photosensitivity for a wavelength above 1530 nm was suppressed. We also tested newly designed DC/SFQ converters with higher input current sensitivities. The observed current sensitivity was improved to 41 \muA, while that in the conventional DC/SFQ converter was 140 \muA. [ABSTRACT FROM AUTHOR]

We have successfully demonstrated an 8-bit microprocessor using passive transmission lines based on single-flux-quantum LSI technology, in the microprocessor designed here, called CORE1α6, a simple bit-serial architecture with seven instructions was employed. In the CORE1α6, the floor plan was designed with consideration toward integration of a memory, and superconductive passive transmission lines (PTLs) were used to connect circuit blocks. Utilization of PTLs helped us reduce the propagation delay in long interconnections The design flexibility of the floor plan was enhanced and the performance of the microprocessor was improved by 20% compared with our previous design. The CORE1α6 was composed of 6319 Josephson junctions and 15 PTLs with power consumption of 2.1 mW. We have confirmed the complete operations of the CORE1Ξ6 by on-chip high-speed tests. The maximum clock frequencies for bit operation and instruction execution have been found to be 18 GHz and 1.2 GHz, respectively, where the performance corresponds to 240 million instructions per second (MIPS). [ABSTRACT FROM AUTHOR]

We have been developing an SFQ shift register memory, which is one candidate to realize high-throughput and high-density superconductive memories. We have modified our memory architecture in order to adapt it to our SFQ microprocessor, CORE1. The new version of the shift register memory is composed of shift registers with non-destructive readout operation, which have an internal feedback. We have also studied the availability of passive transmission line (PTL) wiring in the memory system at high speed. The tested circuit is a 4-byte shift register file, where four kinds of wiring circuits are used between a decoder and shift registers. We have measured the dependences of the DC bias margin on the operating frequency for all wiring methods, and obtained almost the same dependences, which shows the availability of the PTL wiring in the memory system. We have used the NEC 2.5 kA/cm2 Nb standard process and the CONNECT cell library. [Copyright &y& Elsevier]

We have designed and implemented an SFQ programmable clock generator (PCG), which can generate the variable number of SFQ pulses according to its internal state. The PCG is composed of an SFQ ring oscillator, a control circuit which counts up the number of SFQ pulses and stops the operation of the ring oscillator, and a decoder which defines the initial state of the control circuit. The PCG can generate the variable number of SFQ pulses ranging from 2 to 2N, where N is the number of T flip-flops in the control circuit. The oscillation frequency of the PCG is designed to be ranging from 6.2 to 18.8 GHz. In this study, we have implemented a PCG generating SFQ pulses ranging from 2 to 24 using a cell-based design methodology and confirmed its correct functionality. [Copyright &y& Elsevier]

The performance of high-end routers will soon reach the limits of conventional technology. Single flux quantum (SFQ) digital technology is a key technology for achieving a breakthrough. We have already proposed a high-end router using SFQ technology. In this paper, we report on the latest innovation of SFQ router technology. First we describe a design methodology development. We have developed a new SFQ logic cell library for cell-based top-down circuit design. To expand the circuit scale further, a novel pseudo-automatic Josephson transmission line (JTL) routing technique has also been developed. And then, we discuss issues of passive interconnection, and show the operation of a passive transmission line interconnected circuit up to 40-Gbps throughput. Second we describe a packet switch circuit demonstration. We designed a 2 × 2 crossbar packet switch circuit, which is a key element in the packet switch. We successfully tested the circuit up to a clock frequency of 35 GHz. Finally we discuss an SFQ circuit application in the optical router as an alternative application strategy. [Copyright &y& Elsevier]