38 results on '"Adamu-Lema, Fikru"'
Search Results
2. Scaling and intrinsic parameter fluctuations in nano-CMOS devices
- Author
-
Adamu-Lema, Fikru
- Subjects
621.381 ,TK Electrical engineering. Electronics Nuclear engineering - Abstract
The core of this thesis is a thorough investigation of the scaling properties of conventional nano-CMOS MOSFETs, their physical and operational limitations and intrinsic parameter fluctuations. To support this investigation a well calibrated 35 nm physical gate length real MOSFET fabricated by Toshiba was used as a reference transistor. Prior to the start of scaling to shorter channel lengths, the simulators were calibrated against the experimentally measured characteristics of the reference device. Comprehensive numerical simulators were then used for designing the next five generations of transistors that correspond to the technology nodes of the latest International Technology Roadmap for Semiconductors (lTRS). The scaling of field effect transistors is one of the most widely studied concepts in semiconductor technology. The emphases of such studies have varied over the years, being dictated by the dominant issues faced by the microelectronics industry. The research presented in this thesis is focused on the present state of the scaling of conventional MOSFETs and its projections during the next 15 years. The electrical properties of conventional MOSFETs; threshold voltage (VT), subthreshold slope (S) and on-off currents (lon, Ioffi ), which are scaled to channel lengths of 35, 25, 18, 13, and 9 nm have been investigated. In addition, the channel doping profile and the corresponding carrier mobility in each generation of transistors have also been studied and compared. The concern of limited solid solubility of dopants in silicon is also addressed along with the problem of high channel doping concentrations in scaled devices. The other important issue associated with the scaling of conventional MOSFETs are the intrinsic parameter fluctuations (IPF) due to discrete random dopants in the inversion layer and the effects of gate Line Edge Roughness (LER). The variations of the three important MOSFET parameters (loff, VT and Ion), induced by random discrete dopants and LER have been comprehensively studied in the thesis. Finally, one of the promising emerging CMOS transistor architectures, the Ultra Thin Body (UTB) SOl MOSFET, which is expected to replace the conventional MOSFET, has been investigated from the scaling point of view.
- Published
- 2005
3. Impact of quantum confinement on transport and the electrostatic driven performance of silicon nanowire transistors at the scaling limit
- Author
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Al-Ameri, Talib, Georgiev, Vihar P., Sadi, Toufik, Wang, Yijiao, Adamu-Lema, Fikru, Wang, Xingsheng, Amoroso, Salvatore M., Towie, Ewan, Brown, Andrew, and Asenov, Asen
- Published
- 2017
- Full Text
- View/download PDF
4. RTN and BTI in nanoscale MOSFETs: A comprehensive statistical simulation study
- Author
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Amoroso, Salvatore Maria, Gerrer, Louis, Markov, Stanislav, Adamu-Lema, Fikru, and Asenov, Asen
- Published
- 2013
- Full Text
- View/download PDF
5. Nano-electronic simulation software (NESS): a novel open-source TCAD simulation environment
- Author
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Medina-Bailon, Cristina, Dutta, Tapas, Adamu-Lema, Fikru, Rezaei, Ali, Nagy, Daniel, Georgiev, Vihar P., and Asenov, Asen
- Subjects
quantum correction ,lcsh:T58.7-58.8 ,non-equilibrium green’s function ,variability ,lcsh:Electric apparatus and materials. Electric circuits. Electric networks ,integrated simulation environment ,drift-diffusion ,lcsh:TK452-454.4 ,lcsh:Production capacity. Manufacturing capacity ,kubo-greenwood - Abstract
This paper presents the latest status of the open source advanced TCAD simulator called Nano-Electronic Simulation Software (NESS) which is currently under development at the Device Modeling Group of the University of Glasgow. NESS is designed with the main aim to provide an open, flexible, and easy to use simulation environment where users are able not only to perform numerical simulations but also to develop and implement new simulation methods and models. Currently, NESS is organized into two main components: the structure generator and a collection of different numerical solvers; which are linked to supporting components such as an effective mass extractor and materials database. This paper gives a brief overview of each of the components by describing their main capabilities, structure, and theory behind each one of them. Moreover, to illustrate the capabilities of each component, here we have given examples considering various device structures, architectures, materials, etc. at multiple simulation conditions. We expect that NESS will prove to be a great tool for both conventional as well as exploratory device research programs and projects.
- Published
- 2020
6. A Kinetic Monte Carlo study of retention time in a POM molecule-based flash memory
- Author
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Badami, Oves, Sadi, Toufik, Adamu-Lema, Fikru, Lapham, Paul, Mu, Dejiang, Nagy, Daniel, Georgiev, Vihar, Ding, Jie, and Asenov, Asen
- Abstract
The modelling of conventional and novel memory devices has gained significant traction in recent years. This is primarily because the need to store increasingly larger amount of data demands a better understanding of the working of the novel memory devices, to enable faster development of the future technology generations. Furthermore, in-memory computing is also of great interest from the computational perspectives, to overcome the data transfer bottleneck that is prevalent in the von-Neumann architecture. These important factors necessitates the development of comprehensive TCAD simulation tools that can be used for modeling carrier dynamics in the gate oxides of the Flash type memory cells. In this work, we introduce the kinetic Monte Carlo module that we have developed and integrated within the Nano Electronic Simulation Software (NESS) - to model electronic charge transport in Flash memory type structures. Using the developed module, we perform retention time analysis for a polyoxometalate (POM) molecule-based charge trap flash memory. Our simulation study highlights that retention characteristics for the POM molecules has a unique features that depends on the properties of the tunneling oxide.
- Published
- 2020
7. Simulation study of individual and combined sources of intrinsic parameter fluctuations in conventional nano-MOSFETs
- Author
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Roy, Gareth, Brown, Andrew R., Adamu-Lema, Fikru, Roy, Scott, and Asenov, Asen
- Subjects
Metal oxide semiconductor field effect transistors -- Design and construction ,Numerical analysis ,Business ,Electronics ,Electronics and electrical industries - Abstract
The intrinsic parameter fluctuations introduced by random discrete dopants, line edge roughness (LER), and oxide-thickness variation in realistic bulk MOSFETs scaled to 25, 18, 13, and 9 nm are studied using three-dimensional statistical numerical simulations. The scaling is based on a 35 nm MOSFET developed by Toshiba, which is also used for the calibration of the atomistic device simulator.
- Published
- 2006
8. Intrinsic Parameter Fluctuations in Conventional MOSFETs at the Scaling Limit: A Statistical Study
- Author
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Adamu-Lema, Fikru, Roy, Gareth, Brown, Andrew R., Asenov, Asen, and Roy, Scott
- Published
- 2004
- Full Text
- View/download PDF
9. Variability predictions for the next technology generations of n-type \ud SixGe1-x nanowire MOSFETs
- Author
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Lee, Jaehyun, Badami, Oves, Carrillo-Nunez, Hamilton, Berrada, Salim, Medina-Bailon, Cristina, Dutta, Tapas, Adamu-Lema, Fikru, Georgiev, Vihar P., and Asenov, Asen
- Abstract
Using a state-of-the-art quantum transport simulator based on the effective mass approximation, we have thoroughly studied the impact of variability on SixGe1−x channel gate-all-around nanowire metal-oxide-semiconductor field-effect transistors (NWFETs) associated with random discrete dopants, line edge roughness, and metal gate granularity. Performance predictions of NWFETs with different cross-sectional shapes such as square, circle, and ellipse are also investigated. For each NWFETs, the effective masses have carefully been extracted from sp3d5s∗ tight-binding band structures. In total, we have generated 7200 transistor samples and performed approximately 10,000 quantum transport simulations. Our statistical analysis reveals that metal gate granularity is dominant among the variability sources considered in this work. Assuming the parameters of the variability sources are the same, we have found that there is no significant difference of variability between SiGe and Si channel NWFETs.
- Published
- 2018
10. Intrinsic parameter fluctuations in nanometre scale thin-body SOI devices introduced by interface roughness
- Author
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Brown, Andrew R, Adamu-Lema, Fikru, and Asenov, Asen
- Published
- 2003
- Full Text
- View/download PDF
11. Understanding electromigration in Cu-CNT composite interconnects: a multiscale electrothermal simulation study
- Author
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Lee, Jaehyun, Berrada, Salim, Adamu-Lema, Fikru, Carrillo-Nunez, Hamilton, Nagy, Nicole, Georgiev, Vihar, Sadi, Toufik, Liang, Jie, Ramos, Raphael, Kalita, Dipankar, Lilienthal, Katharina, Wislicenus, Marcus, Pandey, Reeturaj, Chen, Bingan, Teo, Kenneth B.K., Goncalves, Goncalo, Okuno, Hanako, Uhlig, Benjamin, Todri-Sanial, Aida, Dijon, Jean, and Asenov, Asen
- Abstract
In this paper, we report a hierarchical simulation\ud study of the electromigration problem in Cu-CNT composite\ud interconnects. Our work is based on the investigation of the\ud activation energy and self-heating temperature using a multiscale\ud electro-thermal simulation framework. We first investigate the\ud electrical and thermal properties of Cu-CNT composites, including\ud contact resistances, using the Density Functional Theory and\ud Reactive Force Field approaches, respectively. The corresponding\ud results are employed in macroscopic electro-thermal simulations\ud taking into account the self-heating phenomenon. Our simulations\ud show that although Cu atoms have similar activation\ud energies in both bulk Cu and Cu-CNT composites, Cu-CNT\ud composite interconnects are more resistant to electromigration\ud thanks to the large Lorenz number of the CNTs. Moreover,\ud we found that a large and homogenous conductivity along the\ud transport direction in interconnects is one of the most important\ud design rules to minimize the electromigration.
- Published
- 2018
12. Understanding Electromigration in Cu-CNT Composite Interconnects
- Author
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Lee, Jaehyun, Berrada, Salim, Adamu-Lema, Fikru, Nagy, Nicole, Georgiev, Vihar P., Sadi, Toufik, Liang, Jie, Ramos, Raphael, Carrillo-Nunez, Hamilton, Kalita, Dipankar, Lilienthal, Katharina, Wislicenus, Marcus, Pandey, Reeturaj, Chen, Bingan, Teo, Kenneth B.K., Goncalves, Goncalo, Okuno, Hanako, Uhlig, Benjamin, Todri-Sanial, Aida, Dijon, Jean, Asenov, Asen, Publica, University of Glasgow, Fraunhofer Center for Nanoelectronic Technologies, Department of Neuroscience and Biomedical Engineering, Laboratoire d'informatique, de robotique et de microélectronique de Montpellier, Institut national de physique nucléaire et de physique des particules, Aixtron Ltd, Aalto-yliopisto, and Aalto University
- Subjects
Conductivity ,Cu-carbon nanotubes (CNT) composites ,Electromigration ,interconnects ,Contacts ,Resistance ,electrothermal ,electromigration (EM) ,Lattices ,Discrete Fourier transforms ,multiscale simulation ,density functional theory (DFT) ,self-heating ,Thermal conductivity - Abstract
In this paper, we report a hierarchical simulation study of the electromigration (EM) problem in Cu-carbon nanotube (CNT) composite interconnects. This paper is based on the investigation of the activation energy and self-heating temperature using a multiscale electrothermal simulation framework. We first investigate the electrical and thermal properties of Cu-CNT composites, including contact resistances, using the density functional theory and reactive force field approaches, respectively. The corresponding results are employed in macroscopic electrothermal simulations taking into account the self-heating phenomenon. Our simulations show that although Cu atoms have similar activation energies in both bulk Cu and Cu-CNT composites, Cu-CNT composite interconnects are more resistant to EM thanks to the large Lorenz number of the CNTs. Moreover, we found that a large and homogenous conductivity along the transport direction in interconnects is one of the most important design rules to minimize the EM.
- Published
- 2018
13. Z²-FET as capacitor-less eDRAM cell for high-density integration
- Author
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Navarro, Carlos, Duan, Meng, Parihar, Mukta Sing, Adamu-Lema, Fikru, Coseman, Stefan, Lacord, Joris, Lee, Kyunghwa, Sampedro, Carlos, Cheng, Binjie, El Dirani, Hassan, Barbe, Jean-Charles, Fonteneau, Pascal, Kim, Seong-Il, Cristoloveanu, Sorin, Bawedin, Maryline, Millar, Campbell, Galy, Philippe, Le Royer, Cyrille, Karg, Siegfried, Riel, Heike, Wells, Paul, Kim, Yong-Tae, Asenov, Asen, and Gamiz, Francisco
- Subjects
Hardware_INTEGRATEDCIRCUITS - Abstract
2-D numerical simulations are used to demonstrate the Z²-FET as a competitive embedded capacitor-less dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depleted-silicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature.
- Published
- 2017
14. Extended analysis of the Z²-FET: operation as capacitorless eDRAM
- Author
-
Navarro, Carlos, Lacord, Joris, Parihar, Mukta Singh, Adamu-Lema, Fikru, Duan, Meng, Rodriguez, Noel, Cheng, Binjie, El Dirani, Hassan, Barbe, Jean-Charles, Fonteneau, Pascal, Bawedin, Maryline, Millar, Campbell, Galy, Philippe, Le Royer, Cyrille, Karg, Siegfried, Wells, Paul, Kim, Yong-Tae, Asenov, Asen, Cristoloveanu, Sorin, and Gamiz, Francisco
- Subjects
Hardware_MEMORYSTRUCTURES ,Hardware_INTEGRATEDCIRCUITS ,Hardware_PERFORMANCEANDRELIABILITY - Abstract
The Z²-FET operation as capacitorless DRAM\ud is analyzed using advanced 2-D TCAD simulations for IoT\ud applications. The simulated architecture is built based on\ud actual 28-nm fully depleted silicon-on-insulatordevices. It is\ud found that the triggering mechanism is dominated by the\ud front-gate bias and the carrier’s diffusion length. As in other\ud FB-DRAMs, the memory window is defined by the ON voltage\ud shift with the stored body charge. However, the Z²-FET’s\ud memory state is not exclusively defined by the inner charge\ud but also by the reading conditions.
- Published
- 2017
15. Modelling and simulation of advanced semiconductor devices
- Author
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Adamu-Lema, Fikru, Duan, Meng, Berrada, Salim, Lee, Jaehyun, Al-Ameri, T., Georgiev, Vihar, and Asenov, Asen
- Abstract
This paper presents a modelling and simulation study of advanced semiconductor devices. Different Technology Computer Aided Design approaches and models, used in nowadays research are described here. Our discussions are based on numerous theoretical approaches starting from first principle methods and continuing with discussions based on more well stablished methods such as Drift-Diffusion, Monte Carlo and Non-Equilibrium Green’s Function formalism.
- Published
- 2017
16. Nano-electronic Simulation Software (NESS): a flexible nano-device simulation platform.
- Author
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Berrada, Salim, Carrillo-Nunez, Hamilton, Lee, Jaehyun, Medina-Bailon, Cristina, Dutta, Tapas, Badami, Oves, Adamu-Lema, Fikru, Thirunavukkarasu, Vasanthan, Georgiev, Vihar, and Asenov, Asen
- Abstract
The aim of this paper is to present a flexible and open-source multi-scale simulation software which has been developed by the Device Modelling Group at the University of Glasgow to study the charge transport in contemporary ultra-scaled Nano-CMOS devices. The name of this new simulation environment is Nano-electronic Simulation Software (NESS). Overall NESS is designed to be flexible, easy to use and extendable. Its main two modules are the structure generator and the numerical solvers module. The structure generator creates the geometry of the devices, defines the materials in each region of the simulation domain and includes eventually sources of statistical variability. The charge transport models and corresponding equations are implemented within the numerical solvers module and solved self-consistently with Poisson equation. Currently, NESS contains a drift–diffusion, Kubo–Greenwood, and non-equilibrium Green's function (NEGF) solvers. The NEGF solver is the most important transport solver in the current version of NESS. Therefore, this paper is primarily focused on the description of the NEGF methodology and theory. It also provides comparison with the rest of the transport solvers implemented in NESS. The NEGF module in NESS can solve transport problems in the ballistic limit or including electron–phonon scattering. It also contains the Flietner model to compute the band-to-band tunneling current in heterostructures with a direct band gap. Both the structure generator and solvers are linked in NESS to supporting modules such as effective mass extractor and materials database. Simulation results are outputted in text or vtk format in order to be easily visualized and analyzed using 2D and 3D plots. The ultimate goal is for NESS to become open-source, flexible and easy to use TCAD simulation environment which can be used by researchers in both academia and industry and will facilitate collaborative software development. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
17. Interplay between quantum mechanical effects and a discrete trap position in ultrascaled FinFETs
- Author
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Georgiev, Vihar P., Amoroso, Salvatore M., Gerrer, Louis, Adamu-Lema, Fikru, and Asenov, Asen
- Subjects
QC - Abstract
In this work we establish a link between positions of a single discrete charge trapped in an oxide interface and between the performance of ultra-scaled FinFET transistors. The charge trapped in the oxide induces gate voltage shift (∆VG). This ∆VG is presented as a function of the device geometry for two regimes of\ud conduction – from a sub-threshold to an ON-state. For specific trap positions in the oxide, we show that the trap impact decreases with scaling down of the FinFET size and of the applied gate voltage. We also compare the Drift-Diffusion (DD) calculations with the Non Equilibrium Green Functions (NEGF) simulations in order to investigate the importance of quantum charge confinement in transport and of reliability resilience in\ud ultra-scaled non-planar transistors, such as FinFETs.
- Published
- 2015
18. Random Dopant-Induced Variability in Si-InAs Nanowire Tunnel FETs: A Quantum Transport Simulation Study.
- Author
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Carrillo-Nunez, Hamilton, Lee, Jaehyun, Berrada, Salim, Medina-Bailon, Cristina, Adamu-Lema, Fikru, Luisier, Mathieu, Asenov, Asen, and Georgiev, Vihar P.
- Subjects
RESONANT tunneling ,ELECTRICAL engineering ,SIMULATION methods & models - Abstract
In this letter, we report a quantum transport simulation study of the impact of random discrete dopants (RDDs) on Si-InAs nanowire p-type Tunnel FETs. The band-to-band tunneling is simulated using the non-equilibrium Green’s function formalism in effective mass approximation, implementing a two-band model of the imaginary dispersion. We have found that RDDs induce strong variability not only in the OFF-state but also in the ON-state current of the TFETs. Contrary to the nearly normal distribution of the RDD-induced ON-current variations in conventional CMOS transistors, the TFET’s ON-currents variations are described by a logarithmic distribution. The distributions of other figures of merit (FoM) such as threshold voltage and subthreshold swing are also reported. The variability in the FoM is analyzed by studying the correlation between the number and the position of the dopants. [ABSTRACT FROM AUTHOR]
- Published
- 2018
- Full Text
- View/download PDF
19. Z^\textsf 2 -FET as Capacitor-Less eDRAM Cell For High-Density Integration.
- Author
-
Navarro, Carlos, Meng Duan, Singh Parihar, Mukta, Adamu-Lema, Fikru, Coseman, Stefan, Lacord, Joris, Kyunghwa Lee, Sampedro, Carlos, Binjie Cheng, El Dirani, Hassan, Barbe, Jean-Charles, Fonteneau, Pascal, Seong-Il Kim, Cristoloveanu, Sorin, Bawedin, Maryline, Millar, Campbell, Galy, Philippe, Le Royer, Cyrille, Karg, Siegfried, and Riel, Heike
- Subjects
CAPACITORS ,CIRCUIT elements ,FIELD-effect transistors ,COMPUTER simulation ,ELECTROMECHANICAL analogies - Abstract
2-D numerical simulations are used to demonstrate the Z2-FET as a competitive embedded capacitor-less dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depleted-silicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature. [ABSTRACT FROM AUTHOR]
- Published
- 2017
- Full Text
- View/download PDF
20. Experimental and Simulation Study of Silicon Nanowire Transistors Using Heavily Doped Channels.
- Author
-
Georgiev, Vihar P., Mirza, Muhammad M., Dochioiu, Alexandru-Iustin, Adamu-Lema, Fikru, Amoroso, Salvatore M., Towie, Ewan, Riddet, Craig, MacLaren, Donald A., Asenov, Asen, and Paul, Douglas J.
- Abstract
The experimental results from 8 nm diameter silicon nanowire junctionless field-effect transistors with gate lengths of 150 nm are presented that demonstrate on-currents up to 1.15 mA/ $\mu$m for 1.0 V and 2.52 mA/ \mu$m for 1.8 V gate overdrive with an off-current set at 100 nA/\mu$m. On- to off-current ratios above 10^8C. Simulations using drift-diffusion which include density-gradient quantum corrections provide excellent agreement with the experimental results. The simulations demonstrate that the present silicon-dioxide gate dielectric only allows the gate to be scaled to 25 nm length before short-channel effects significantly reduce the performance. If high-K dielectrics replace some parts of the silicon dioxide then the technology can be scaled to at least 10 nm gatelength. [ABSTRACT FROM PUBLISHER]
- Published
- 2017
- Full Text
- View/download PDF
21. Scaling and intrinsic parameter fluctuations in nanoCMOS devices
- Author
-
Adamu-Lema, Fikru
- Subjects
TK Electrical engineering. Electronics Nuclear engineering - Abstract
The core of this thesis is a thorough investigation of the scaling properties of conventional nano-CMOS MOSFETs, their physical and operational limitations and intrinsic parameter fluctuations. To support this investigation a well calibrated 35 nm physical gate length real MOSFET fabricated by Toshiba was used as a reference transistor. Prior to the start of scaling to shorter channel lengths, the simulators were calibrated against the experimentally measured characteristics of the reference device. Comprehensive numerical simulators were then used for designing the next five generations of transistors that correspond to the technology nodes of the latest International Technology Roadmap for Semiconductors (lTRS). The scaling of field effect transistors is one of the most widely studied concepts in semiconductor technology. The emphases of such studies have varied over the years, being dictated by the dominant issues faced by the microelectronics industry. The research presented in this thesis is focused on the present state of the scaling of conventional MOSFETs and its projections during the next 15 years. The electrical properties of conventional MOSFETs; threshold voltage (VT), subthreshold slope (S) and on-off currents (lon, Ioffi ), which are scaled to channel lengths of 35, 25, 18, 13, and 9 nm have been investigated. In addition, the channel doping profile and the corresponding carrier mobility in each generation of transistors have also been studied and compared. The concern of limited solid solubility of dopants in silicon is also addressed along with the problem of high channel doping concentrations in scaled devices. The other important issue associated with the scaling of conventional MOSFETs are the intrinsic parameter fluctuations (IPF) due to discrete random dopants in the inversion layer and the effects of gate Line Edge Roughness (LER). The variations of the three important MOSFET parameters (loff, VT and Ion), induced by random discrete dopants and LER have been comprehensively studied in the thesis. Finally, one of the promising emerging CMOS transistor architectures, the Ultra Thin Body (UTB) SOl MOSFET, which is expected to replace the conventional MOSFET, has been investigated from the scaling point of view.
- Published
- 2005
22. Interplay between quantum mechanical effects and a discrete trap position in ultra-scaled FinFETs.
- Author
-
Georgiev, Vihar P., Amoroso, Salvatore M., Gerrer, Louis, Adamu-Lema, Fikru, and Asenov, Asen
- Published
- 2015
- Full Text
- View/download PDF
23. Statistical Study of Bias Temperature Instabilities by Means of 3D ˵Atomistic″ Simulation.
- Author
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Amoroso, Salvatore Maria, Gerrer, Louis, Adamu-Lema, Fikru, Markov, Stanislav, and Asenov, Asen
- Published
- 2014
- Full Text
- View/download PDF
24. A Mobility Correction Approach for Overcoming Artifacts in Atomistic Drift-Diffusion Simulation of Nano-MOSFETs.
- Author
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Amoroso, Salvatore Maria, Adamu-Lema, Fikru, Brown, Andrew R., and Asenov, Asen
- Subjects
- *
METAL oxide semiconductor field-effect transistors , *COMPLEMENTARY metal oxide semiconductors , *SEMICONDUCTOR doping , *ELECTRON mobility , *DOPED semiconductors , *ELECTRON transport - Abstract
A comprehensive statistical investigation of the increase in resistance associated with charge trapping in atomistic simulations is presented. A wide range of doping densities and mesh spacing are considered for both classical and quantum formalisms. A doping-dependent correction factor to modify the mobility model for the atomistic simulations is proposed to suppress the error related to the fictitious charge trapping. The validity of the new mobility model is tested in the statistical simulations of the transistors corresponding to 20-nm bulk CMOS and 14-nm FinFET transistors. [ABSTRACT FROM AUTHOR]
- Published
- 2015
- Full Text
- View/download PDF
25. Performance and Variability of Doped Multithreshold FinFETs for 10-nm CMOS.
- Author
-
Adamu-Lema, Fikru, Wang, Xingsheng, Amoroso, Salvatore Maria, Riddet, Craig, Cheng, Binjie, Shifren, Lucian, Aitken, Robert, Sinha, Saurahb, Yeric, Greg, and Asenov, Asen
- Subjects
- *
COMPLEMENTARY metal oxide semiconductors , *SIMULATION methods & models , *PERFORMANCE evaluation , *THRESHOLD voltage , *STRAY currents , *SILICON - Abstract
In this paper, by means of simulation, we have studied the implications of using channel doping to control the threshold voltage and the leakage current in bulk silicon FinFETs suitable for the 10-nm CMOS technology generation. The channel doping level of high-performance FinFETs designed for 100-nA/ \(\mu \) m leakage current has been increased to achieve 10 and 1-nA/ \(\mu \) m leakage currents. Ensemble Monte Carlo (EMC) simulations are used to estimate the impact of the increased doping on the transistor performance. Atomistic drift-diffusion simulations calibrated to the results of the EMC simulations are used to evaluate the impact of random discrete dopants, line edge roughness, and metal gate granularity on the statistical variability. The results of the statistical variability simulations are also used to highlight errors resulting from the use of continuous doping in the TCAD simulation of advanced CMOS technology generation FinFETs. [ABSTRACT FROM PUBLISHER]
- Published
- 2014
- Full Text
- View/download PDF
26. Modelling of reliability of nanoscale MOSFETs within the discrete charge trapping paradigm.
- Author
-
Adamu-Lema, Fikru, Amoroso, Salvatore M., Gerrer, Louis, and Asenov, Asen
- Published
- 2013
- Full Text
- View/download PDF
27. Comprehensive statistical comparison of RTN and BTI in deeply scaled MOSFETs by means of 3D ‘atomistic’ simulation.
- Author
-
Amoroso, Salvatore M., Gerrer, Louis, Markov, Stanislav, Adamu-Lema, Fikru, and Asenov, Asen
- Abstract
We present a thorough statistical investigation of random telegraph noise (RTN) and bias temperature instabilities (BTI) in nanoscale MOSFETs. By means of 3D TCAD ‘atomistic’ simulations, we evaluate the statistical distribution in capture/emission time constants and in threshold voltage shift (ΔVT) amplitudes due to single trapped charge, comparing its impact on RTN and BTI. Our analysis shows that, neglecting any impact of charge trapping on trans-characteristic degradation, the individual BTI ΔVT steps are distributed identically as the RTN ΔVT steps. However, the individual traps in a device cannot be considered as uncorrelated sources of noise because their mutual interaction is fundamental in determining the dispersion of capture/emission time constants in BTI simulation. These results are of utmost importance for profoundly understanding the differences and similarities in the statistical behavior of RTN and BTI phenomena. [ABSTRACT FROM PUBLISHER]
- Published
- 2012
- Full Text
- View/download PDF
28. 3D dynamic RTN simulation of a 25nm MOSFET: The importance of variability in reliability evaluation of decananometer devices.
- Author
-
Amoroso, Salvatore Maria, Adamu-Lema, Fikru, Markov, Stanislav, Gerrer, Louis, and Asenov, Asen
- Abstract
In this work we present a 3D dynamic simulation analysis for the reliability evaluation of a decananometer MOSFET device. We have focused our attention on the Random Telegraph Noise (RTN) phenomenon, showing that the statistical variability induced by the discrete nature of matter and charge has a fundamental impact on the reliability performance of nanoscale devices, in both transient and steady-state operating regimes. [ABSTRACT FROM PUBLISHER]
- Published
- 2012
- Full Text
- View/download PDF
29. Problems With the Continuous Doping TCAD Simulations of Decananometer CMOS Transistors.
- Author
-
Asenov, Asen, Adamu-Lema, Fikru, Wang, Xingsheng, and Amoroso, Salvatore Maria
- Subjects
- *
SEMICONDUCTOR doping , *COMPLEMENTARY metal oxide semiconductors , *TRANSISTORS , *THRESHOLD voltage , *STRAY currents - Abstract
In this paper, we compare results from atomistic and continuous simulation of decananometer scale CMOS transistors. We study the behavior of important figures of merit, including threshold voltage, subthreshold slope, OFF-current, and ON-current. We provide physical explanation for the origin of the discrepancies between the averaged values obtained from the statistical simulations and the results from the continuous doping simulation. Based on our analysis, we clearly demonstrate that there are increasing errors in the doping distributions when device TCAD simulations are calibrated using continuous doping profiles. This questions the use of continuous doping profiles in the routine calibration and TCAD-based optimization of decananometer scale CMOS transistors. [ABSTRACT FROM AUTHOR]
- Published
- 2014
- Full Text
- View/download PDF
30. Time-Dependent 3-D Statistical KMC Simulation of Reliability in Nanoscale MOSFETs.
- Author
-
Amoroso, Salvatore Maria, Gerrer, Louis, Hussin, Razaidi, Adamu-Lema, Fikru, and Asenov, Asen
- Subjects
PERFORMANCE of electronics ,METAL oxide semiconductor field-effect transistors ,MONTE Carlo method ,ELECTRON traps ,NANOPARTICLES ,CHARGE injection - Abstract
This paper presents a thorough numerical investigation of statistical effects associated with charge trapping dynamics and their impact on the reliability projection in decananometer MOSFETs. By means of a novel 3-D kinetic Monte Carlo TCAD reliability simulation technology, we track the time-dependent variability associated with granular charge injection and trapping into the oxide traps. We consider the interactions between the statistical variability of the virgin transistors, introduced by the discreteness of charge and granularity of matter, and the stochastic nature of the trap distribution and the trapping process itself. As a result, the path to device failure (PtDF), defined as the stochastic succession of trapping events that bring the device parameters to a predefined failure criteria, is analyzed in detail. In particular, we show that the two stochastic components determining the PtDF, namely the traps' capture time constants and threshold voltage shifts, are uncorrelated. The charge injection variability is shown to play a dominant role in determining the statistical dispersion of the reliability behavior. Furthermore, we show that the short- and long-term reliability behaviors are uncorrelated. Finally, 3-D fringing and percolative effects are shown to play an important role in determining the statistical degradation of nanoscale MOSFETs. [ABSTRACT FROM AUTHOR]
- Published
- 2014
- Full Text
- View/download PDF
31. 3-D Statistical Simulation Comparison of Oxide Reliability of Planar MOSFETs and FinFET.
- Author
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Gerrer, Louis, Amoroso, Salvatore Maria, Markov, Stanislav, Adamu-Lema, Fikru, and Asenov, Asen
- Subjects
METAL oxide semiconductor field-effect transistors ,TRANSISTORS ,COMPLEMENTARY metal oxide semiconductors ,THRESHOLD voltage ,SUSPENSIONS (Chemistry) - Abstract
New transistor architectures such as fully depleted silicon on insulator (FDSoI) MOSFETs and FinFETs have been introduced in advanced CMOS technology generations to boost performance and to reduce statistical variability (SV). In this paper, the robustness of these architectures to random telegraph noise and bias temperature instability issues is investigated using comprehensive 3-D numerical simulations, and results are compared with those obtained from conventional bulk MOSFETs. Not only the impact of static trapped charges is investigated, but also the charge trapping dynamics are studied to allow device lifetime and failure rate predictions. Our results show that device-to-device variability is barely increased by progressive oxide charge trapping in bulk devices. On the contrary, oxide degradation determines the SV of SoI and FinFET devices. However, the SoI and multigate transistor architectures are shown to be significantly more robust in terms of immunity to time-dependent SV when compared with the conventional bulk device. The comparative study here presented could be of significant importance for reliability resistant CMOS circuits and systems design. [ABSTRACT FROM PUBLISHER]
- Published
- 2013
- Full Text
- View/download PDF
32. Geometry, Temperature, and Body Bias Dependence of Statistical Variability in 20-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis.
- Author
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Xingsheng Wang, Adamu-Lema, Fikru, Binjie Cheng, and Asenov, Asen
- Subjects
- *
METAL oxide semiconductor field-effect transistors , *COMPUTER simulation , *COMPLEMENTARY metal oxide semiconductors , *THRESHOLD voltage , *QUANTITATIVE research , *SILICON-on-insulator technology - Abstract
Conventional bulk CMOS, which is arguably most vulnerable to statistical variability (SV), is the workhorse of the electronic industry for more than three decades. In this paper, the dependence of the SV of key figures of merit on gate geometry, temperature, and body bias in 25-nm gate-length MOSFETs, representative for the 20-nm CMOS technology generation, is systematically investigated using 3-D statistical simulations. The impact of all relevant sources of SV is taken into account. The geometry dependence of the threshold-voltage dispersion (and indeed the dispersion of other key transistor figures of merit) does not necessarily follow the Pelgrom's law due to the complex nonuniform channel doping and the interplay of different SV sources. The DIBL variation, for example, follows a log-normal distribution. The temperature significantly affects the magnitudes of threshold voltage, subthreshold slope, ON/OFF currents, and the corresponding statistical distributions. Reverse body bias increases the threshold voltage and its fluctuation, while forward body bias reduces both of them. [ABSTRACT FROM AUTHOR]
- Published
- 2013
- Full Text
- View/download PDF
33. Accuracy and Issues of the Spectroscopic Analysis of RTN Traps in Nanoscale MOSFETs.
- Author
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Adamu-Lema, Fikru, Monzio Compagnoni, Christian, Amoroso, Salvatore M., Castellani, Niccolò, Gerrer, Louis, Markov, Stanislav, Spinelli, Alessandro S., Lacaita, Andrea L., and Asenov, Asen
- Subjects
- *
METAL oxide semiconductor field-effect transistors , *SEMICONDUCTOR doping , *ELECTROSTATICS , *RANDOM noise theory , *SPECTRUM analysis , *LOGIC circuits , *SURFACE potential - Abstract
This paper investigates the limitations to the accuracy and the main issues of the spectroscopic analyses of random telegraph noise (RTN) traps in nanoscale MOSFETs. First, the impact of the major variability sources affecting decananometer MOSFET performance on both the RTN time constants and the trap depth estimation is studied as a function of the gate overdrive. Results reveal that atomistic doping and metal gate granularity broaden the statistical distribution of the RTN time constants far more than what comes from the random position of the RTN trap in the 3-D device electrostatics, contributing, in turn, to a significant reduction of the accuracy of trap spectroscopy. The accuracy is shown to improve the higher is the gate overdrive, owing to a more uniform and gate-bias-independent surface potential in the channel, with, however, the possible drawback of triggering the simultaneous trap interaction with both the channel and the gate. This simultaneous interaction is, finally, shown to critically compromise trap spectroscopy in thin-oxide devices. [ABSTRACT FROM PUBLISHER]
- Published
- 2013
- Full Text
- View/download PDF
34. Simulation and Modeling of Novel Electronic Device Architectures with NESS (Nano-Electronic Simulation Software): A Modular Nano TCAD Simulation Framework.
- Author
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Medina-Bailon, Cristina, Dutta, Tapas, Rezaei, Ali, Nagy, Daniel, Adamu-Lema, Fikru, Georgiev, Vihar P., and Asenov, Asen
- Subjects
SIMULATION software ,GREEN'S functions ,SEMICONDUCTOR devices ,RESONANT tunneling ,PROGRAMMING languages ,ELECTRONIC equipment ,TUNNEL diodes - Abstract
The modeling of nano-electronic devices is a cost-effective approach for optimizing the semiconductor device performance and for guiding the fabrication technology. In this paper, we present the capabilities of the new flexible multi-scale nano TCAD simulation software called Nano-Electronic Simulation Software (NESS). NESS is designed to study the charge transport in contemporary and novel ultra-scaled semiconductor devices. In order to simulate the charge transport in such ultra-scaled devices with complex architectures and design, we have developed numerous simulation modules based on various simulation approaches. Currently, NESS contains a drift-diffusion, Kubo–Greenwood, and non-equilibrium Green's function (NEGF) modules. All modules are numerical solvers which are implemented in the C++ programming language, and all of them are linked and solved self-consistently with the Poisson equation. Here, we have deployed some of those modules to showcase the capabilities of NESS to simulate advanced nano-scale semiconductor devices. The devices simulated in this paper are chosen to represent the current state-of-the-art and future technologies where quantum mechanical effects play an important role. Our examples include ultra-scaled nanowire transistors, tunnel transistors, resonant tunneling diodes, and negative capacitance transistors. Our results show that NESS is a robust, fast, and reliable simulation platform which can accurately predict and describe the underlying physics in novel ultra-scaled electronic devices. [ABSTRACT FROM AUTHOR]
- Published
- 2021
- Full Text
- View/download PDF
35. Statistical Interactions of Multiple Oxide Traps Under BTI Stress of Nanoscale MOSFETs.
- Author
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Markov, Stanislav, Amoroso, Salvatore Maria, Gerrer, Louis, Adamu-Lema, Fikru, and Asenov, Asen
- Subjects
OXIDES ,SIMULATION methods & models ,STATISTICAL correlation ,NANOCHEMISTRY ,TEMPERATURE effect ,ELECTROSTATIC interaction ,THRESHOLD voltage ,ELECTRONIC circuits - Abstract
We report a thorough 3-D simulation study of the correlation between multiple, trapped charges in the gate oxide of nanoscale bulk MOSFETs under bias and temperature instability (BTI). The role of complex electrostatic interactions between the trapped charges in the presence of random dopant fluctuations is evaluated, and their impact on the distribution of the threshold voltage shift and on the distribution of the number of trapped charges is analyzed. The results justify the assumptions of a Poisson distribution of the BTI-induced trapped charges and of the lack of correlation between them, when accounting for time-dependent variability in circuits. [ABSTRACT FROM PUBLISHER]
- Published
- 2013
- Full Text
- View/download PDF
36. Variability Predictions for the Next Technology Generations of n-type SixGe1−x Nanowire MOSFETs.
- Author
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Lee, Jaehyun, Badami, Oves, Carrillo-Nuñez, Hamilton, Berrada, Salim, Medina-Bailon, Cristina, Dutta, Tapas, Adamu-Lema, Fikru, Georgiev, Vihar P., and Asenov, Asen
- Subjects
SILICON germanium integrated circuits ,METAL oxide semiconductor field-effect transistors ,NANOWIRES - Abstract
Using a state-of-the-art quantum transport simulator based on the effective mass approximation, we have thoroughly studied the impact of variability on Si x Ge 1 − x channel gate-all-around nanowire metal-oxide-semiconductor field-effect transistors (NWFETs) associated with random discrete dopants, line edge roughness, and metal gate granularity. Performance predictions of NWFETs with different cross-sectional shapes such as square, circle, and ellipse are also investigated. For each NWFETs, the effective masses have carefully been extracted from s p 3 d 5 s ∗ tight-binding band structures. In total, we have generated 7200 transistor samples and performed approximately 10,000 quantum transport simulations. Our statistical analysis reveals that metal gate granularity is dominant among the variability sources considered in this work. Assuming the parameters of the variability sources are the same, we have found that there is no significant difference of variability between SiGe and Si channel NWFETs. [ABSTRACT FROM AUTHOR]
- Published
- 2018
- Full Text
- View/download PDF
37. Impact of statistical variability and 3D electrostatics on post-cycling anomalous charge loss in nanoscale Flash memories.
- Author
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Amoroso, Salvatore Maria, Gerrer, Louis, Adamu-Lema, Fikru, Markov, Stanislav, and Asenov, Asen
- Published
- 2013
- Full Text
- View/download PDF
38. Variability Predictions for the Next Technology Generations of n -type Si x Ge 1- x Nanowire MOSFETs.
- Author
-
Lee J, Badami O, Carrillo-Nuñez H, Berrada S, Medina-Bailon C, Dutta T, Adamu-Lema F, Georgiev VP, and Asenov A
- Abstract
Using a state-of-the-art quantum transport simulator based on the effective mass approximation, we have thoroughly studied the impact of variability on Si x Ge 1 - x channel gate-all-around nanowire metal-oxide-semiconductor field-effect transistors (NWFETs) associated with random discrete dopants, line edge roughness, and metal gate granularity. Performance predictions of NWFETs with different cross-sectional shapes such as square, circle, and ellipse are also investigated. For each NWFETs, the effective masses have carefully been extracted from s p 3 d 5 s ∗ tight-binding band structures. In total, we have generated 7200 transistor samples and performed approximately 10,000 quantum transport simulations. Our statistical analysis reveals that metal gate granularity is dominant among the variability sources considered in this work. Assuming the parameters of the variability sources are the same, we have found that there is no significant difference of variability between SiGe and Si channel NWFETs.
- Published
- 2018
- Full Text
- View/download PDF
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