89 results on '"Alizadeh, Bijan"'
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2. Automatic correction of RTL designs using a lightweight partial high level synthesis
3. A comparative study of machine learning classifiers for secure RF-PUF-based authentication in internet of things
4. PODEM: A low-cost property-based design modification for detecting Hardware Trojans in resource-constraint IoT devices
5. Data-path aware high-level ECO synthesis
6. Systematic Trojan Detection in Crypto-Systems Using the Model Checker.
7. A dynamic specification to automatically debug and correct various divider circuits
8. Analytical performance model for FPGA-based reconfigurable computing
9. Groebner basis based formal verification of large arithmetic circuits using Gaussian elimination and cone-based polynomial extraction
10. Formal equivalence verification and debugging techniques with auto-correction mechanism for RTL designs
11. FPGA-based Implementation of a New Data
12. Mutual Lightweight PUF-Based Authentication Scheme Using Random Key Management Mechanism for Resource-Constrained IoT Devices.
13. Hardware Patching Methodology for Neutralizing Timing Hardware Trojans Using Vulnerability Analysis and Time Borrowing Scheme.
14. A formal approach for debugging arithmetic circuits
15. SAT-Based Integrated Hardware Trojan Detection and Localization Approach Through Path-Delay Analysis.
16. Automated Formal Equivalence Verification of Pipelined Nested Loops in Datapath Designs
17. Incremental SAT-Based Correction of Gate Level Circuits by Reusing Partially Corrected Circuits.
18. FPGA-Based Implementation of a Real-Time Object Recognition System Using Convolutional Neural Network.
19. PMTP: A MAX-SAT-Based Approach to Detect Hardware Trojan Using Propagation of Maximum Transition Probability.
20. Combinational Hybrid Signal Selection With Updated Reachability Lists for Post-Silicon Debug.
21. FPGA-Based Implementation of an Artificial Neural Network for Measurement Acceleration in BOTDA Sensors.
22. A Dynamic Timing Error Avoidance Technique Using Prediction Logic in High-Performance Designs.
23. Incremental SAT-Based Accurate Auto-Correction of Sequential Circuits Through Automatic Test Pattern Generation.
24. Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors.
25. FPGA-Based Implementation of a Novel Method for Estimating the Brillouin Frequency Shift in BOTDA and BOTDR Sensors.
26. Automatic Correction of Dynamic Power Management Architecture in Modern Processors.
27. Improved Range Analysis in Fixed-Point Polynomial Data-Path.
28. A Resource-Limited Hardware Accelerator for Convolutional Neural Networks in Embedded Vision Applications.
29. QBF-Based Post-Silicon Debug of Speed-Paths Under Timing Variations.
30. Combinational trace signal selection with improved state restoration for post-silicon debug.
31. Formally analyzing fault tolerance in datapath designs using equivalence checking.
32. Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors.
33. Systematic Design Space Exploration of Floating-Point Expressions on FPGA.
34. OptiFEX: A Framework for Exploring Area-Efficient Floating Point Expressions on FPGAs With Optimized Exponent/Mantissa Widths.
35. UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications.
36. UPF-based formal verification of low power techniques in modern processors.
37. Signature oriented model pruning to facilitate multi-threaded processors debugging.
38. In-Circuit Mutation-Based Automatic Correction of Certain Design Errors Using SAT Mechanisms.
39. Low power scheduling in high-level synthesis using dual-Vth library.
40. Dynamic Flip-Flop Conversion: A Time-Borrowing Method for Performance Improvement of Low-Power Digital Circuits Prone to Variations.
41. RTL datapath optimization using system-level transformations.
42. Dynamic Flip-Flop conversion to tolerate process variation in low power circuits.
43. Improving polynomial datapath debugging with HEDs.
44. Automated formal approach for debugging dividers using dynamic specification.
45. Effective Combination of Algebraic Techniques and Decision Diagrams to Formally Verify Large Arithmetic Circuits.
46. A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression.
47. Highly scalable, shared-memory, Monte-Carlo tree search based Blokus Duo Solver on FPGA.
48. An analytical dynamic and leakage power model for FPGAs.
49. A Hybrid Time Borrowing Technique to Improve the Performance of Digital Circuits in the Presence of Variations.
50. A Scalable Formal Debugging Approach with Auto-Correction Capability Based on Static Slicing and Dynamic Ranking for RTL Datapath Designs.
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