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This paper presents a novel bidirectional electrostatic discharge protection device based on a dual silicon-controlled rectifier with a symmetrical trigger circuit. The proposed device has been realized and verified in a 40-nm CMOS process, which can pass a 3.75-kV HBM and a 250-V MM with a very low standby leakage current of ∼27 nA at 25 °C and a bias voltage of 0.9 V with a silicon footprint of only \text13\ \mu\textm \times \text100\ \mu\textm. [ABSTRACT FROM PUBLISHER]

A new electrostatic discharge (ESD) protection device, called quad-silicon controlled rectifier (QSCR), is proposed and verified in a 0.25- \mu \textm CMOS process. The QSCR is designed to be used as ESD protection between separated power domains. Since the QSCR embeds four SCRs between its four terminals, no extra ESD clamps are needed to protect the interface circuits between two separated power domains. Implementations with different circuit topologies were also analyzed to achieve a comprehensive ESD protection design for different applications. From the experimental results, the QSCR can withstand 8-kV HBM and 600-V MM ESD stresses with a silicon area of 75 \mu \text m \times 100~\mu \textm . [ABSTRACT FROM PUBLISHER]

This paper presents a new RC-based power-rail electrostatic discharge (ESD) clamp circuit, which achieves ultra-low leakage current while maintaining low silicon utilization. A capacitance-boosting technique is used in conjunction with mathematical analysis of area utilization to determine the best set of parameters to achieve the smallest implementation area in silicon. The proposed power-rail ESD clamp circuit has been verified in a 65-nm general-purpose CMOS process, which achieves an ultra-low standby leakage current of 80 nA at 25 °C under 1-V bias, as well as ESD robustness of a 4-kV human body model and a 250-V machine model with a silicon area of only \mbox45\ \mu\mboxm\times \mbox17\ \mu\mboxm. [ABSTRACT FROM PUBLISHER]

A new silicon controlled rectifier-based power-rail electrostatic discharge (ESD) clamp circuit was proposed with a novel trigger circuit that has very low leakage current in a small layout area for implementation. This circuit was successfully verified in a 40-nm CMOS process by using only low-voltage devices. The novel trigger circuit uses a diode-string based level-sensing ESD detection circuit, but not using MOS capacitor, which has very large leakage current. Moreover, the leakage current on the ESD detection circuit is further reduced, adding a diode in series with the trigger transistor. By combining these two techniques, the total silicon area of the power-rail ESD clamp circuit can be reduced three times, whereas the leakage current is three orders of magnitude smaller than that of the traditional design. [ABSTRACT FROM AUTHOR]