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The article studies the channel-hot-carrier (CHC) degradation and bias temperature instabilities (BTIs) of NMOS and PMOS transistors within CMOS inverters. Findings reveal BTI as the mechanism that controls the device degradation when a dc signal is applied at the input.

Climate change has affected the geographical distributions of most species worldwide; in particular, insects of economic importance inhabiting tropical regions have been impacted. Current and future predictions of change in geographic distribution are frequently included in species distribution models (SDMs). The potential spatial distributions of the fruit fly Anastrepha striata Schiner, the main species of agricultural importance in guava crops, under current and possible future scenarios in Colombia were modeled, and the establishment risk was assessed for each guava-producing municipality in the country. SDMs were developed using 221 geographical records in conjunction with nine scenopoetic variables. The model for current climate conditions indicated an extensive suitable area for the establishment of A. striata in the Andean region, smaller areas in the Caribbean and Pacific, and almost no areas in the Orinoquia and Amazonian regions. A brief discussion regarding the area's suitability for the fly is offered. According to the results, altitude is one of the main factors that direct the distribution of A. striata in the tropics. The Colombian guava-producing municipalities were classified according to the degree of vulnerability to fly establishment as follows: 42 were high risk, 16 were intermediate risk, and 17 were low risk. The implementation of future integrated management plans must include optimal spatial data and must consider environmental aspects, such as those suggested by the models presented here. Control decisions should aim to mitigate the positive relationship between global warming and the increase in the dispersal area of the fruit fly. [ABSTRACT FROM AUTHOR]

Quantum dots (QDs) can be used as conductive islands to build-up single-electron transistors (SETs). The characteristics of the QDs define the functional performance of the SETs. In consequence, analyzing the influence of the variations of QD dimensions on the performance of hybrid SET-FET circuits is of high relevance. We employ a self-developed SET compact model which is calibrated to 3-D quantum-mechanics-based simulations in order to obtain realistic model parameters. A method to improve the circuit behavior, i.e., to increase the output current, is proposed. It is concluded that the variation of the QD size presents the largest influence on the overall circuit behavior. [ABSTRACT FROM AUTHOR]

The performance of the 3T1D-DRAM cell beyond 10-nm technology node is investigated when the memory cell is based on nonplanar multigate devices, i.e., FinFETs. Moreover, for completeness, the cell is analyzed in both SOI and bulk-based FinFETs. While relevant process variation robustness is observed in SOI-based FinFETs, 10× lower impact than for bulk-based ones. In order to improve the variability robustness of bulk-based FinFET cell, we propose a dual-VT strategy to enhance the dynamic cell behavior. [ABSTRACT FROM PUBLISHER]

In this paper, we assess the performance of a ring oscillator and a DRAM cell when they are implemented with different technologies (planar CMOS, FinFETs, and III–V MOSFETs), and subjected to different reliability scenarios (variability and soft errors). FinFET-based circuits show the highest robustness against variability and soft error environments. [ABSTRACT FROM PUBLISHER]

The channel hot-carrier (CHC) degradation in metal-oxide semiconductor field-effect transistors based on a high-k dielectric with strained-Si/relaxed Si1-xGex structures has been little studied so far. However, due to the high mobility enhancement observed in these samples, a deeper study of the CHC impact on them is necessary. In this article, the effects of the Ge content, overgrowth, channel length, and operating temperature on the CHC degradation have been analyzed. The results show that devices with higher mobility suffer larger CHC aging both at room temperature and in the elevated temperature range. [ABSTRACT FROM AUTHOR]

The degradation produced by channel hot-carrier (CHC) on short channel transistors with high-k dielectric has been analyzed. For short channel transistors (L<0.15 µm), the most damaging stress condition has been found to be VG=VD instead of the ‘classical’ VG=VD/2 determined for long channel transistors. In this work, experimentally validated simulations have been performed to demonstrate that this shift is not caused by the presence of the high-k layer but due to short channel effects. Furthermore, the CHC degradation lifetime has been evaluated, revealing larger operating voltages for high-k than for SiO2-based transistors. Copyright © 2010 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]