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The digital compensation method for path delay mismatches in the time-to-digital converter (TDC) based on gated-ring oscillator (GRO) is proposed and demonstrated. The output of the GRO is digitized by the combination of a counter and a phase-to-digital converter (PDC) producing an integer and a fractional digital value, respectively. Due to the delay mismatches between two paths, the integer and fractional digital values are not synchronized thereby causing calculation errors. In order to reduce the errors, a correction bit (CB) is generated and then the erroneous output is fixed by the additional but simple digital circuits. Measurement results show that calculation errors due to the delay mismatches are corrected by the proposed compensation method and it reduces the quantization noise power by 10dB at high frequency offset. [ABSTRACT FROM AUTHOR]

This paper presents a fully-integrated D-band frequency synthesizer (FS) in 0.13-m SiGe BiCMOS technology. The proposed FS consists of a 20-GHz phase-locked loop (PLL) and a frequency multiplier including a doubler (2) and a quadrupler (4). The FS generates the D-band output signals from 164.08 to 166.19GHz. At 166.19GHz, the measured phase noises (PN) at 100-kHz and 1-MHz offset frequencies are 54.07dBc/Hz and 72.29dBc/Hz, respectively. The proposed FS achieves the low power dissipation of around 110mW and the chip area is including all testing pads. The FS has great potential to be used for low-power D-band applications. [ABSTRACT FROM AUTHOR]

High-sensitivity super-regenerative receivers (SRXs) are demonstrated at 96 and 135 GHz, respectively, in this paper. They are based on high-Q quench-controlled metamaterial resonators with a differential transmission line loaded with a split-ring resonator (DTL-SRR) and a differential transmission line loaded with a complementary split-ring resonator (DTL-CSRR) in 65-nm CMOS. High-Q oscillatory amplifications are established by the sharp stopband introduced by metamaterial resonators. As such, high detection sensitivity is achieved for SRXs at millimeter-wave regions. The fabricated 96-GHz DTL-CSRR-based SRX has a compact core chip area of 0.014 mm2 with measured power consumption of 2.8 mW, sensitivity of -79 dBm, noise figure (NF) of 8.5 dB, and noise equivalent power (NEP) of 0.67 fW/√(Hz). The fabricated 135-GHz DTL-SRR-based SRX has a compact core chip area of 0.0085 mm2 with measured power consumption of 6.2 mW, sensitivity of -76.8 dBm, NF of 9.7 dB, and NEP of 0.9 fW/√(Hz). Compared to the conventional SRX with an LC-tank-based resonator at similar frequencies, the proposed SRXs have 2.8~4 dB sensitivity improvement and 60% smaller area. The integrated SRXs are also demonstrated for the imaging applications. [ABSTRACT FROM AUTHOR]

In this paper, a six-port distributed model of on-chip single-turn transformers in silicon that can predict the features of the transformers up to 200 GHz is presented. Moreover, the proposed model is scalable with the diameter of the transformer. Based on the developed model, a transformer balun with improved differential-port balance is deployed in a D-band up-conversion mixer design in \ 0.13- \mu\ m SiGe BiCMOS technology. The mixer achieves a measured conversion gain (CG) of \4 \sim \ 7~\ dB and local-oscillator-to-RF isolation over 30 dB from 110 to 140 GHz. The results have one of the best CGs in the millimeter-wave range. A D-band two-stage transformer-coupled power amplifier (PA) integrated with a mixer is also reported here. Using the six-port transformer model, the performance of the PA can be conveniently optimized. At a 2-V supply, the gain and saturated output power of 20 dB and 8 dBm, respectively, are both experimentally achieved at 127 GHz. At 3 V, the measured output power rose to 11 dBm and this is the best power performance among the reported D-band silicon-based amplifiers to date. [ABSTRACT FROM AUTHOR]

This brief presents a high-voltage (HV) transducer driver to fulfill the requirement of the proposed high-data-rate down-hole acoustic telemetry system. The driver is targeted to drive a stack of piezoelectric disks modeled as a capacitive load of 0.3 \mu\F and across a broadband from 600 Hz to 1.2 kHz. To ensure stability, the driver is designed as an open-loop system, comprising a dead-time controller, level shifters, gate drivers, and power MOSFETs. The driver is fabricated using the 1.0- \mu\m silicon-on-insulator CMOS process and its performance is investigated up to 260 ^\circ\C, far beyond the specified process limit of 225 ^\circ\C. The experimental results also validated the functionality of the HV Class-D-type driver for voltages up to 60 V. [ABSTRACT FROM AUTHOR]

In this letter, a high-gain and selectivity W-band LNA using 0.13 \mum SiGe BiCMOS is proposed. A Q-enhanced cascode approach with a filter synthesis passband-forming technique was employed to achieve gain and selectivity improvement simultaneously. The amplifier achieved a gain of above 45 dB and a noise figure of 6–8.3 dB at 77–101 GHz with a power consumption of 19.2 mW. The LNA has high selectivity with a 3 dB-to-35 dB shape factor of 2.1, which is comparable with silicon-based passive millimeter-wave filters. [ABSTRACT FROM PUBLISHER]