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The design of a Ternary Logic Processor using CNTFETs (Carbon-Nanotube-Field-Effect-Transistor) is a challenging task, but it also has the potential to offer significant advantages over the traditional binary logic processors based on CMOS (Complementary-Metal-Oxide-Semiconductor) technology. This paper presents the design and implementation of a Ternary Logic Processor (TLP) using CNTFETs. The TLP is a single-cycle processor that operates on three-trit data. An Instruction Set Architecture (ISA) is defined, at first, for this TLP that consists of instructions of the Register type, Load-store type, Immediate type, and branch type. Based on the ISA, the architecture of the CNTFET-based TLP is proposed and the transistor level designs of the TLPs' fundamental blocks like the Ternary Instruction Fetch (TIF), Ternary Register File (TRF), Ternary Arithmetic and Logic Unit (TALU) and Ternary Data Memory (TDM) are presented. HSPICE simulations using a standard CNTFET model, are performed for the TLP and the TLPs' individual blocks and the performance parameters like the power consumption, propagation delay, and the number of CNTFETs required are calculated. In addition to this, the functionality of the processor is verified using a few of the standard programs. [ABSTRACT FROM AUTHOR]

Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compared to other transistor technologies regarding energy efficiency and circuit speed. To the best of our knowledge, this is the first time that a ternary design has been applied inside the CPU of an SDN controller. Earlier studies focused on Ternary Content-Addressable Memory (TCAM) in SDN. This paper proposes a new 1-trit Ternary Full Adder (TFA) to decrease the propagation delay and the Power–Delay Product (PDP). The proposed design is compared to the latest 17 designs, including 15 designs that are 1-trit TFA CNTFET-based, 2-bit binary FA FinFET-based, and 2-bit binary FA CMOS-based, using the HSPICE simulator, to optimize the CPU utilization in SDN environments, thereby enhancing programmability. The results show the success of the proposed design in reducing the propagation delays by over 99% compared to the 2-bit binary FA CMOS-based design, over 78% compared to the 2-bit binary FA FinFET-based design, over 91% compared to the worst-case TFA, and over 49% compared to the best-case TFAs. [ABSTRACT FROM AUTHOR]

In this paper, we design and simulate a Single-Ended Colpitts Oscillator (CO) in integer and fractional order domains. The oscillators are realized in 32nm node conventional MOSFET and carbon nanotube field effect transistor (CNTFET) technologies. Therefore, four COs have been designed, simulated and rigorously compared. These include integer order conventional MOSFET-based CO, fractional order MOSFET-based CO, CNTFET-based integer order CO and CNTFET-based fractional order CO, all based on 32-nm technology nodes. The fractional order approach has been used as it results in better control over the phase and frequency of the oscillator. Herein, fractional order capacitors of various orders, used in realizing the fractional order COs, are realized and their frequency responses are studied. This is being done to ensure whether the designed pseudo-capacitances have fractional behavior or not in the desired frequency and phase spectrum. It has been observed that the variation of fractional order (α) from 0.4 to 0.81 has resulted in a slight reduction of oscillation frequency from 1.68GHz (α = 0.4) to 1.351GHz (α = 0.81) keeping the pseudo-capacitance same at 0.3nF in MOS-based topology. Since the fractional order realization increases the circuit complexity and power consumption, therefore, CNTFET-based integer order as well as fractional order COs have been designed. The CNTFET-based fractional order CO retains the advantages of the fractional order domain as well as the power efficiency of CNTFETs. Further, it has been observed that integrating fractional-order capacitor (FOC) with the CNTFET CO results in a much larger constant phase zone (CPZ), an important performance measuring parameter. A rigorous comparative analysis of the four COs designed in this work has been performed. [ABSTRACT FROM AUTHOR]

A low-power and compact carbon nanotube field-effect transistor (CNTFET)-based K -band electronically tunable band-pass filter (BPF) is presented. The filter is designed using second-generation multiple-output current-controlled current conveyor (MOCCCII). The presented active only current-mode BPF employs three MOCCCIIs and two CNTFETs as capacitors. This BPF can be tuned by varying the parasitic resistance of MOCCCIIs via the control current. The designed current-mode tunable BPF is simulated in an advanced design system (ADS) using the Stanford CNTFET model with the extension of noise and manufacturing process variation. The filter achieves a 21–23 GHz tuning frequency range, with a minimum noise figure of about 11.09 dB. The 1-dB compression point and input-referenced third-order intercept point are −19.28 and −8.4 dBm, respectively. This compact filter consumes only 145.7 μ W power at ± 0.5 V supply voltage at room temperature. The temperature analysis shows good thermal stability. The Monte Carlo analysis demonstrates the good process variation stability of the filter. The suggested BPF can be thought of as the first fully active BPF that is a candidate for K -band communication applications with future advances in the fabrication process for CNTFET. [ABSTRACT FROM AUTHOR]

Ternary logic has received substantial attention over binary logic due to diminished delay, reduced power consumption, and minimized area requirements. Carbon Nanotube Field Effect Transistors (CNTFETs) are mostly preferred for the implementation of ternary logic because of their ability to achieve multi-threshold transistors. This paper presents an energy-efficient CNTFET-based 3-trit Wallace tree multiplier design using a novel 4-input ternary adder (called 4-ITA), full-adder, and half-adder. We have proposed half-adder, full-adder, and 1-trit multipliers using a new 3:1 multiplexer module (called MUX-2) that significantly enhances energy efficiency within our ternary multiplier design. This multiplexer, leveraging high and standard threshold voltage devices, greatly optimizes our ternary multiplier's power consumption and computational speed. Furthermore, we reduced power dissipation by minimizing switching transitions within the signal generation circuits of both MUX-2 and the arithmetic modules. All the arithmetic designs were designed using the 45 nm CNTFET technology. Results prove that the 3-trit multiplier achieved 40% lesser power consumption and a 51% power delay product improvement compared to the best literature design. [ABSTRACT FROM AUTHOR]

As the traditional silicon-based CMOS technology advances into the nanoscale stage, approaching its physical limits, the Carbon Nanotube Field-effect Transistor (CNTFET) is considered to be the most significant transistor technology beyond Moore's era. The CNTFET has a quasi-one-dimensional structure so that the carrier can realize ballistic transport and has very high mobility. At the same time, a single CNTFET can integrate hundreds of nanowires as the conductive channels, enabling significant current transport capabilities even in low supply voltage, thereby providing a foundational basis for achieving nanoscale ultra-large-scale analog/logic circuits. This paper summarizes the development status of the CNTFET compact model and digital/analog/RF integrated circuits. The challenges faced by SPICE modeling and circuit design are analyzed. Meanwhile, solutions to these challenges and development trends of carbon-based transistors are discussed. Finally, the future application prospects of carbon-based integrated circuits are presented. [ABSTRACT FROM AUTHOR]

With the reduction of CMOS technology to nanometric dimensions, it is thought that the end of atomic limits in integrated circuit applications is almost approached and some problems are encountered in production. Carbon nanotube field effect transistors (CNTFETs) are considered a proper option to replace CMOS near term owing to their superior properties such as scalability and better channel electrostatics. For this purpose, a low-voltage, low-power Voltage Differencing Inverting Buffered Amplifier (VDIBA) structure is propose with a 32 nm CNTFET, in this article. The proposed CNTFET VDIBA structure operates with a bias current of 1 µA and consumes 14.32 µW of power with a supply voltage of ± 0.3 V. Compared to the traditional CMOS VDIBA structure, the power consumption is reduced by 733 times. Besides, proposed VDIBA structure has a bandwidth of 43.788 GHz. [ABSTRACT FROM AUTHOR]

In this paper, a simple carbon nanotube field effect transistor (CNTFET)-based inverter has been simulated and the impacts of changing various design and process parameters on its characteristics and performance have been analysed using HSPICE. The 32 nm CNTFET model of Stanford University has been used here for the simulation of the inverter. The simulation results and the voltage transfer characteristics (VTC) curve of the inverter have been extracted for (i) different channel lengths, (ii) top gate di-electric material thickness (tox), (iii) pitch value (iv) the number of tubes in CNTFET channel region and (v) chirality of the CNT. It has been observed that the VTC curve changes significantly with different values of these parameters. Some important output parameters like maximum dc current, power, rise time, fall time, average propagation delay, etc. have been measured in each case. Changes in maximum power consumption value due to the change in different parameter values are observed through plotted graphs. Output dc current vs. input voltage graphs have been plotted for different chirality of the tubes, the number of the tubes, and pitch values between n-type CNTFET and p-type CNTFET of the inverter. [ABSTRACT FROM AUTHOR]

This paper presents novel power-efficient designs of quaternary logic gates like Quaternary Minimum (QMIN) and Quaternary Maximum (QMAX), Standard Quaternary Inverter (SQI), Standard Quaternary NAND (SQNAND), Standard Quaternary NOR (SQNOR) and Standard Quaternary XOR (SQXOR) using Carbon Nanotube Field Effect Transistor (CNTFET). The designs are based on Pass Transistor Logic (PTL) and use only three types of Carbon Nanotube (CNT) diameters 0.626 nm, 1.018 nm, and 2.27 nm, which lead to lower fabrication costs and enhanced manufacturability when compared to the state-of-the-art designs. The designs are simulated in HSPICE with a 32 nm CNTFET model provided by Stanford University, and the average power and maximum propagation delay obtained from the simulation results are compared with other existing designs. It shows that the proposed designs require 75% to 90% less power and they achieve 73% to 91% less Power Delay Product (PDP) than the latest designs. [ABSTRACT FROM AUTHOR]

In the course of this study, an efficient implementation of a high gain and low power two-stage operational amplifier using indirect feedback frequency compensation based on CNTFETs. HSPICE software was used to develop and simulate CNTFETs. The op-amps were designed using 0.9 V input supply voltage. The proposed structures were formed either using CNTFETs only known as pure CNTFET-IFFC-2SOA or hybrid structures consisting a mix of both CNTFETs and conventional CMOS named as PCNTFET-NMOS-IFFC-2SOA and NCNTFET-PMOS-2SOA. The comparative investigation revealed that CNT-based structures performed significantly better than the traditional CMOS-based devices. In the instance of CNTFET-IFFC-2SOA, there was a considerable improvement in DC gain, power dissipation, phase margin, and CMRR. The DC Gain increased by 140.92%, the CMRR increased by 32.94%, and the phase margin increased by 4.9%. Furthermore, at the 32 nm technology node, a GNRFET-based structure was designed and compared to conventional CMOS and pure CNTFET-based IFFC-2SOA. It was discovered that the DC gain, phase margin, and power dissipation obtained by the CNTFET-based structure were superior to both. The DC Gain of CNTFET-IFFC-2SOA was 156.79% more than that of GNRFET-IFFC-2SOA. To confirm the workability of the proposed circuits, an integrator was designed and simulated as its application. The CNTFET-based IFFC-2SOA integrators showed better integration action than the traditional CMOS-IFFC-2SOA. [ABSTRACT FROM AUTHOR]

Recent developments in multiplication circuits with fewer transistors, higher speed, and reduced energy consumption are lowering hardware costs. Approximate multiplication is used for fault-tolerant applications, such as image and signal processing. These applications offer considerable improvement at the cost of reduced accuracy. Compressors are the main component of any multiplier structure. In this work, the design of an approximate multiplier based on current mode, using 4:2 and 5:2 approximate compressors and current over scaling technique is suggested to reduce power consumption, delay, and hardware components compared to existing architectures. In the proposed approach for the design of compressor circuits, current mode binary converters with 32 nm CNTFET technology are used. This work is done in three steps: (1) converting input currents into voltage and creating multi-level voltages. (2) Implementing voltage level detector. (3) Generation of output current based on threshold voltage. The proposed technique uses less number of transistors. The simulation was done under HSPICE software and the efficiency of the compressors was compared in terms of delay, power, and power delay product (PDP). Based on the simulation results, the PDP value for 4:2 and 5:2 compressor circuits is calculated as 0.0097 and 0.0131 fJ, respectively. Then, an approximate multiplication of 8 × 8 using these compressors is designed for multiplying images under MATLAB software. This multiplier has achieved a good improvement in terms of PSNR and MSSIM (respectively 9.14 and 2.85%) compared to advanced approximate multipliers. Also, the proposed approach performs better in terms of accuracy, power consumption, and delay. [ABSTRACT FROM AUTHOR]

Ternary circuits are promising due to their lower interconnect complexity, storage requirement, and lesser pin count than binary circuits. The adder is one of the most important building blocks of a digital processor. This paper proposes carbon nanotube field effect transistor (CNTFET)-based 'exact' and 'approximate' ternary full adders (TFA). The CNTFET is attractive for realizing multi-valued logic (MVL)/ternary circuits because its threshold voltage can be changed by altering the diameter of its carbon nanotube (CNT). The exact ternary adders are realized using unary functions and multiplexers. The circuit size of only the 'Sum' block of a TFA is pruned in approximate ternary full adders by varying degrees for achieving superior performance in terms of transistor count, delay, and power consumption compared to the 'exact' TFAs. This performance gain in approximate TFAs is obtained at the cost of accuracy in some of the 'Sum' outputs. Circuits are simulated with HSPICE using a 32 nm CNTFET technology node at various supply voltages and temperatures. The proposed exact adders exhibit lower power consumption and transistor count, higher robustness, and lower power delay product (PDP) and energy delay product (EDP) than existing ternary adders. The improvement in PDP of the proposed exact TFAs varies from 20 to 96% compared to existing TFAs. The performance of the exact TFAs is then further improved by approximating its 'Sum' block in approximate TFAs. Image blending is used to demonstrate the effectiveness of approximate ternary adders in error-tolerant applications. [ABSTRACT FROM AUTHOR]

The scaling limitations of Complementary Metal-Oxide-Semiconductor (CMOS) transistors to achieve better performance have led to the attention of other structures to improve circuit performance. One of these structures is multi-valued circuits. In this paper, we will first study Carbon Nanotube Transistors (CNT). CNT transistors offer a viable means to implement multi-valued logic due to their variable and controllable threshold voltage. Subsequently, we delve into the realm of three-valued flip-flop circuits, which find extensive utility in digital electronics. Leveraging the insights gained from our analysis, we propose a novel D-type flip-flop structure. The presented structure boasts a remarkably low power consumption, showcasing a reduction exceeding 61% compared to other existing structures. Furthermore, the proposed circuit incorporates a reduced number of transistors, resulting in a reduced footprint. Importantly, this circuit exhibits negligible static power consumption in generating intermediate values, rendering it robust against process variations. Overall, the proposed circuits demonstrate a 29.7% increase in delay compared to the compared structures. However, they showcase a 96.1% reduction in power-delay product (PDP) compared to the other structures. The number of transistors is also 8.3% less than other structures. Additionally, their figure of merits (FOM) are 19.7% better than the best-compared circuit, underscoring its advantages in power efficiency, chip area, and performance.

Static random access memory (SRAM) cell design has undergone extensive development to achieve good performance and low power consumption. This paper introduces an SRAM cell with ten carbon nanotube field effect transistors (CNTFETs) named 10 T CNTFET SRAM cell to help with that and to address the drawback of most SRAM cells caused by their poor stability during read operation. The Schmitt-trigger (ST)-based inverter and PPN-inverter are coupled back to back to create the novel SRAM cell structure. Additionally, single-ended writing, feed-back cutting, and single-ended reading are used in this novel SRAM cell. The single-ended writing technique and feed-back cutting method are used to their full potential to increase the write static noise margin (WSNM) of this 10 T CNTFET SRAM cell. The single-ended read mode of this 10 T CNTFET SRAM cell increases the read static noise margin (RSNM) as the storage nodes are not disturbed. The hold power, read power, WSNM, hold static noise margin (HSNM), RSNM, read delay, leakage power, and VDDmin of this 10 T CNTFET SRAM cell are 0.5527 nW, 1.8087 nW, 432.4 mV, 360 mV, 360 mV, 5.0651 pS, 0.276 nW, and 32.1 mV, respectively. To understand the performance of this introduced SRAM cell and several existing SRAM cells are simulated and the parameters are compared. A comparative study shows that the introduced cell is more stable than the other cells while consuming less power during reading and holding. Furthermore, the new cell reads much faster and has less VDDmin than the other bit cells. This research also documents how SRAM cell performance changes when the CNTFET parameters change. Using the 32 nm CNTFET model from Stanford University using the Hewlett simulation program with integrated circuit emphasis (HSPICE) simulation tool, the simulation is carried out. [ABSTRACT FROM AUTHOR]

In order to connect two binary and quaternary systems, it is necessary to use binary-to-quaternary (B2Q) and quaternary-to-binary (Q2B) converters. These converters convert numbers from logic 2 to 4 and vice versa. In this paper, we designed a new binary-to-quaternary converter circuit using CNT transistors. In this circuit, the Power Delay Product (PDP) has been reduced to14.59% and 15.39% compared to best previous works (Ref [22] and Ref [23]). Also, this circuit has better driving ability and temperature stability than best previous works. The simulation results using Stanford's 32 nm CNTFET model in HSPICE software are at a voltage of 0.9 V. [ABSTRACT FROM AUTHOR]

The scaling limitations of Complementary Metal-Oxide-Semiconductor (CMOS) transistors to achieve better performance have led to the attention of other structures to improve circuit performance. One of these structures is multi-valued circuits. In this paper, we will first study Carbon Nanotube Transistors (CNT). CNT transistors offer a viable means to implement multi-valued logic due to their variable and controllable threshold voltage. Subsequently, we delve into the realm of three-valued flip-flop circuits, which find extensive utility in digital electronics. Leveraging the insights gained from our analysis, we propose a novel D-type flip-flop structure. The presented structure boasts a remarkably low power consumption, showcasing a reduction exceeding 61% compared to other existing structures. Furthermore, the proposed circuit incorporates a reduced number of transistors, resulting in a reduced footprint. Importantly, this circuit exhibits negligible static power consumption in generating intermediate values, rendering it robust against process variations. Overall, the proposed circuits demonstrate a 29.7% increase in delay compared to the compared structures. However, they showcase a 96.1% reduction in power-delay product (PDP) compared to the other structures. The number of transistors is also 8.3% less than other structures. Additionally, their figure of merits (FOM) are 19.7% better than the best-compared circuit, underscoring its advantages in power efficiency, chip area, and performance. [ABSTRACT FROM AUTHOR]

In this review, we present some designs of CNTFET-based circuits, already proposed by us, and critically examine them here. For some of these, we compare the performance of proposed circuits both in CNTFET and CMOS technology. For the CNTFET model, we use a compact, semi-empirical model, already proposed by us and briefly recalled, while, for the MOSFET model, we use the BSIM4 one of the ADS library. Moreover in some design examples, we compare our results with those obtained using the Stanford model. All simulations are carried out using the software advanced design system (ADS), which is compatible with the Verilog-A programming language. [ABSTRACT FROM AUTHOR]

Compared to single-gate CNTFET, dual-gate structures have better electrostatic control over nanowire conductive channels. However, currently, there is insufficient research on the back-gate effect in a compact model of dual-gate CNTFET. This paper presents an improved dual-gate carbon nanotube field effect transistor (CNTFET) compact model. The functional relationship between the back-gate voltage (Vbg) and threshold voltage (Vth) is derived. And a voltage reference regulation mechanism is adopted so that the back-gate effect can be accurately reflected in the DC transfer characteristics. The influence of gate voltage and drain voltage on transmission probability is analyzed. Meanwhile, the drain current is optimized by modifying the mobility equation. This compact model is built based on Verilog-A hardware language and supports the Hspice simulation tool. Within the supply voltage of 2 V, the simulation results of the proposed compact model are in good agreement with the measurement results. Finally, based on the compact model, an operational amplifier is designed to verify its correctness and feasibility in analog integrated circuits. When the power supply voltage is 1.8 V, and the load capacitance is 2 pF, the gain is 11.8 dB, and the unit-gain-bandwidth (UGB) is 214 kHz, which proves the efficiency of our compact model. [ABSTRACT FROM AUTHOR]

Electronic devices are persisting as the integral part in various medical devices. These devices require SRAMs (Static Random Access Memory) with power efficient capability to handle the data, as they occupy most of the die area. Especially, wearable devices are bringing new challenges in the design of an IC, where high stability and low static power dissipation are very much required. In this paper, two new Carbon Nanotube Field Effect Transistor (CNTFET) based 9T SRAM cell topologies are presented to improve the leakage power dissipation at standby mode while maintaining the stability of the cell. Differential bitlines with decoupled read port are used to assist the read disturbance and the subthreshold lowering as well as stack of transistors are employed to curtail the leakage power. The circuits are implemented at 900 mv in Cadence using CNTFET technology. The Architecture with a 4 × 4 array matrix of the proposed 9T cells is designed. These are found to be the better ones yielding good results compared to the existing designs. [ABSTRACT FROM AUTHOR]

As the semiconductor industry continues to decrease in size, it faces many issues, such as scalability, leakage, short-channel effects, and reliability. carbon nanotubes (CNT) has become a potential new technology that can address the shortcomings of CMOS without compromising both performance and reliability. The research presents the design, simulation, and comparison of an improved full-swing 11 Transistor (11T) adder based on CNT with a CMOS implementation in the 32 nm technological node. The CNT-based adder demonstrated superior performance compared to CMOS-based equivalents in terms of power consumption and delay, along with the power-delay product (PDP). The CNTFET adder demonstrates a minimum power consumption reduction of 73 %, a minimum decrease in delay of 29 %, and a minimum reduction in the power-delay product (PDP) of 81 % when compared to the CMOS version of the adder with supply voltage ranging from 0.8 V to 1.2 V. The CNTFET adder demonstrates a minimum power consumption reduction of 64 %, a minimum decrease in delay of 19 %, and a minimum reduction in the power-delay product (PDP) of 71 % when compared to the CMOS version of the adder with temperature ranging from -25 °C to 75 °C.

In this letter we present a current mode gate based on differential pair as an application of carbon nanotube field effect transistors (CNTFETs). The proposed circuit has two output logic gates: one is NAND, and the other is AND. To simplify the circuit realization we use all CNTFETs of the same type, all with the same lengths and carbon nanotube symmetry indices (n, m). Complex circuits could be obtained in current mode replicating the differential pair CNTFET along the current path. The proposed procedure allows simulation of transfer characteristics from voltage input to current output but also from voltage input to voltage output. Moreover, we can measure simulated power dissipation and delay times.

Software-Defined Networking (SDN) revolutionizes network management by decoupling control plane functionality from data plane devices, enabling the centralized control and programmability of network behavior. This paper uses the ternary system to improve the Central Processing Unit (CPU) inside the SDN controller to enhance network management. The Multiple-Valued Logic (MVL) circuit shows remarkable improvement compared to the binary circuit regarding the chip area, propagation delay, and energy consumption. Moreover, the Carbon Nanotube Field-Effect Transistor (CNTFET) shows improvement compared to other transistor technologies regarding energy efficiency and circuit speed. To the best of our knowledge, this is the first time that a ternary design has been applied inside the CPU of an SDN controller. Earlier studies focused on Ternary Content-Addressable Memory (TCAM) in SDN. This paper proposes a new 1-trit Ternary Full Adder (TFA) to decrease the propagation delay and the Power–Delay Product (PDP). The proposed design is compared to the latest 17 designs, including 15 designs that are 1-trit TFA CNTFET-based, 2-bit binary FA FinFET-based, and 2-bit binary FA CMOS-based, using the HSPICE simulator, to optimize the CPU utilization in SDN environments, thereby enhancing programmability. The results show the success of the proposed design in reducing the propagation delays by over 99% compared to the 2-bit binary FA CMOS-based design, over 78% compared to the 2-bit binary FA FinFET-based design, over 91% compared to the worst-case TFA, and over 49% compared to the best-case TFAs.

Static random-access memory (SRAM) is the most prevalent type of memory used in current system-on-chips (SOC). SRAMs built using Complementary metal oxide semiconductor (CMOS) transistors, suffer from low stability and significant power dissipation at nano scale regime [1]. Studies show that the Carbon nanotube field effect transistor (CNTFET) are prominent to use at nano scale region. This article proposes a 12T CNTFET SRAM cell and its performance metrics like power, stability and delay are compared with various other recent SRAM cells by simulating them using CNTFETs. Two Schmitt trigger (ST) based cross coupled inverter arrangement make up the storage cell in the suggested 12T CNTFET SRAM bit cell. ST-based inverter has stacked N-type transistors, which reduces the circuit's leakage and the voltage transfer characteristics (VTC) of ST inverter is also sharper than the other conventional inverters, thereby enhancing the stability performance of the proposed bit cell. The cell also uses feedback cutting transistor and a separate read and write path to further improve the stability performances during read and write modes. The suggested 12T CNTFET SRAM cell shows higher write SNM, hold SNM and read SNM when compared to other state of the art SRAM cells. The read and write delay of the proposed 12T CNTFET SRAM cell is also seen to improve in contrast to the other SRAM designs. The proposed 12T CNTFET SRAM cell when simulated using 32 nm CNTFET at 0.9 V, shows write power, hold power, read power, write delay, read delay, write static noise margin (WSNM), HSNM and read static noise margin (RSNM), as 0.19 nW, 1.61 nW, 3.13 µW, 119 pS, 7.33 pS, 444 mV, 420 mV, 420 mV respectively. The suggested cell is also tested for parametric variations and its performance is also recorded. The proposed cell surpasses all other cells considered as far as power and stability are concerned making it suitable for usage in smart devices like smart bands, smart watches etc. A 32 nm Stanford University model is used to simulate the proposed 12T CNTFET SRAM cell using the HSPICE tool.

As the size of the transistor decreases in the nanoscale regime, certain parameters, such as, cell stability, power dissipation, and delay, have changed. This poses a significant challenge when attempting to scale down metal oxide semiconductor field effect transistor (MOSFET). The carbon nanotube field effect transistor (CNTFET) has exhibited remarkable advantages compared to MOSFETs in circuit designs within the nanoscale range, owing to its extraordinary characteristics. In this work, a CNTFET-based six-transistor (6T) static random access memory (SRAM) cell is designed using the low power input-dependent (INDEP) technique. The suggested circuits' performance and efficiency is enhanced using CNTFET technology. The suggested design undergoes circuit simulations using the 32 nm CNTFET Stanford model. The results obtained from the simulations indicate that the suggested INDEP 6T SRAM cell surpasses both the conventional 6T SRAM cell and the previous designs in terms of power dissipation, delay, and energy efficiency. The hold, read, and write operations use less power, and the hold and write operations take less time to complete. The suggested design also demonstrates improved energy efficiency for hold and read operations compared to the conventional design. Furthermore, a stability analysis is conducted on the suggested INDEP 6T SRAM cell using the static noise margin (SNM) metric. The suggested INDEP approach in comparison to the other schemes has greater SNMs for hold, write, and read operations, indicating improved SRAM cell stability.

Ternary logics are more desirable than the binary logic because it offers high speed operations and large density of information in digital logic systems. The carbon nanotube field-effect transistors (CNTFETs) are considered as better option for designing the ternary circuits because it provides the multiple threshold voltages by changing nanotube diameter. The complex arithmetic schematics such as adders and multipliers are important circuits in many VLSI applications. The ternary half-adder (THA) and multiplier (TMUL) designed using the Stanford 32 nm CNTFET are proposed in this study. The proposed THA and TMUL uses 41 and 33 CNTFETs and that resulting in a 54.44 % and 45 % reduction in transistor count, which plays major role for delay and power optimization. As a result, the proposed THA shows 37.01 %, 14.07 %, and 45.87 % improvement in delay, power, and energy, whereas TMUL shows 30.48 %, 6.64 %, and 36.74 % improvement in delay, power and energy, respectively, compared to existing circuits. The proposed THA and TMUL are developed using HSPICE with 0.9 V as a supply voltage.

A possible way for the very large scale integration (VLSI) industry to keep up with the pace of high density, computational capability, and energy efficiency is to look into some technologies ahead of binary logic. In recent years, multiple-valued logic (MVL) has caught the notable attention of digital system designers. The carbon nanotube field effect transistor (CNTFET) has been exclusively used for the implementation of MVL circuits. Resistive random-access memory (RRAM) offers a very durable option for executing the MVL due to its capability of storing various resistance states in one cell. In this paper, a ternary 9:2 encoder and a ternary 2:9 decoder have been designed and simulated using the proposed RRAM-based ternary logic gates with standard 32nm CNTFETs. In comparison to other ternary circuits in the literature, the proposed CNTFET RRAM-based ternary logic circuits show less power consumption, delay, and power delay product (PDP). The power of the CNTFET RRAM-based proposed ternary inverter (TI), ternary NAND (TNAND), and ternary NOR (TNOR) is 32.78%, 51.48%, and 24.14% less than the lowest power of the other designs under consideration. The PVT variations and reliability of the proposed encoder and decoder circuits have also been studied.

In this paper, the new structure N×M (N-Ternary inputs and M-Binary outputs) Ternary to Binary Converter based on the Carbone Nanao Tube Field Effect Transistor is presented. The Carbone Nanao Tube Field Effect Transistor (CNTFET) has special properties such as controlled threshold voltage. The aforementioned advantages related to the multi-level (more specifically Ternary) circuits and systems based on CNTFET technology have encouraged researchers to put more effort into on their design and realization in recent years. The Encoder (one input- five outputs), 3×1 multiplexer (one input – one selector-three outputs), and special Adder blocks (Full Adder and Half Adder) are base blocks that are implemented by transistor level using special properties of CNTFET transistor. In general, to implement a N-input ternary-to-binary converter, the number of inputs can be divided into two small converters, and also a ternary-to-binary converter can be designed for each input. In this paper, 2×4, 3×5, 4×7 and 5×8 Ternary to Binary converters are designed and simulated by Hospice and 32 nanometer technology. The result of the simulation is shown that the 5×8 Ternary to Binary converter has 1.89 µW DC-Power and 52 ps propagation delay. The proposed 5×8 TTBC converter is implemented by 365 CNTFET transistors and divided into two ternary to binary converters. [ABSTRACT FROM AUTHOR]

Many researchers are actively working on developing a fast-performing static random-access memory (SRAM) cell with low-power consumption and high stability. This study also introduces one such new and all-round excellent SRAM cell. In this paper, an SRAM cell with eleven transistors (11T) developed using carbon nanotube field effect transistor (CNTFET) is introduced. This new 11T CNTFET SRAM cell is another variant of the Schmitt-trigger (ST)-based SRAM cell. This new SRAM cell structure is achieved by incorporating a single-ended write mode, a feed-back cutting technique and a single-ended read approach into a Schmitt-trigger (ST)-based SRAM cell. The WSNM of the proposed 11T CNTFET SRAM cell is increased by using single-ended writing scheme and feed-back cutting method in the cell. The single ended read approach of 11T CNTFET SRAM cell increases the RSNM as the storage nodes are not disturbed. The write power, hold power, read power, WSNM, HSNM, RSNM, write delay and read delay of this 11T CNTFET SRAM cell are 2.1538e-10 W, 1.7077e-09 W, 1.4524e-08 W, 423.61 mV, 402.20 mV, 425.56 mV, 1.2932e-10s and 5.5225e-12s, respectively. The parameters of the proposed cell are compared with 6T SRAM [M. Elangovan and K. Gunavathi, Stability analysis of 6T CNTFET SRAM cell for single and multiple CNTs, 2018 4th Int. Conf. Devices, Circuits Syst., Coimbatore, India, 16–17 March 2018, vol. 2, pp. 63–67], 8T SRAM [M. Elangovan, A novel Darlington based 8T CNTFET SRAM cell for low, J. Circuits Syst. Comput.30 (2021) 2150213], 12T SRAM [S. Pal, S. Bose, W. H. Ki and A. Islam, Half-select-free low-power dynamic loop-cutting write assist SRAM cell for space applications, IEEE Trans. Electron Dev. 67 (2020) 80–89, doi:10.1109/TED.2019.2952397], 12T SRAM [N. Yadav, A. P. Shah and S. K. Vishvakarma, Stable, reliable, and bit-interleaving 12T SRAM for space applications: A device circuit co-design, IEEE Trans. Semicond. Manuf. 30 (2017) 276–284, doi:10.1109/TSM.2017.2718029], 12T SRA-M [P. Sharma, S. Gupta, K. Gupta and N. Pandey, A low power subthreshold Schmitt Trigger-based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectron. J. 97 (2020) 104703, doi:10.1016/j.mejo.2020.104703] and 12T SRAM [P. Sharma, S. Gupta, K. Gupta and N. Pandey, A low power subthreshold Schmitt Trigger based 12T SRAM bit cell with process-variation-tolerant write-ability, Microelectron. J. 97 (2020) 104703, doi:10.1016/j.mejo.2020.104703] cells to understand the performance of the proposed SRAM cell. From the comparative study, it is observed that the proposed cell is more stable than the other cells considered for the comparison and consumes less power in all write, read and hold modes. Also, the read time of the introduced cell is much less than the others. This study also recorded the information on how the performance of an SRAM cell varies as the CNTFET parameters change. The simulation is done with the HSPICE simulation tool using the Stanford University 32 nm CNTFET model. [ABSTRACT FROM AUTHOR]

Internet-of-things-based embedded systems depend on batteries as an energy resource, and thus, require energy-efficient circuits for prolonged operation. To achieve energy-efficient designs, multiple-valued logic circuits and carbon nanotube field-effect transistors (CNTFETs) are used instead of binary logic circuits and complementary metal–oxide–semiconductor, respectively. This paper presents a novel high-performance and energy-efficient ternary multiplier (TMUL) circuit in CNTFET technology. The proposed TMUL is designed by modifying its truth table by including two ternary unary operator circuits, negative ternary inverter and positive ternary inverter, and finding relations between these operators and outputs to dump ternary decoders/encoders and basic logic gates. Moreover, two power supplies, VDD and VDD/2, are employed to eliminate the direct path from high to low voltage levels in each possible combination of inputs. Using ternary unary operator circuits and applying two power supply components reduce the number of transistors used, delay, and power/energy. The delay, power, and power-delay-product (PDP) of the proposed design at 0.9 V supply voltage are 0.048 ns, 0.172 µW, and 0.008 pJ, respectively. The proposed TMUL offers an improvement between 8.70 and 71% in transistors count, between 11.11 and 81.54% in delay, between 6.52 and 72.74% in power consumption, and between 27.27 and 94.07% in PDP compared to the latest TMUL circuits. [ABSTRACT FROM AUTHOR]

In this letter we present a current mode gate based on differential pair as an application of carbon nanotube field effect transistors (CNTFETs). The proposed circuit has two output logic gates: one is NAND, and the other is AND. To simplify the circuit realization we use all CNTFETs of the same type, all with the same lengths and carbon nanotube symmetry indices (n,m). Complex circuits could be obtained in current mode replicating the differential pair CNTFET along the current path. The proposed procedure allows simulation of transfer characteristics from voltage input to current output but also from voltage input to voltage output. Moreover, we can measure simulated power dissipation and delay times. [ABSTRACT FROM AUTHOR]

In this paper, a new carbon nanotube field effect transistor (CNTFET)-based second-order fully differential all-pass filter circuit is presented. The realized filter uses CNTFET-based transconductors and grounded capacitors. An active-only second-order fully differential all-pass filter circuit topology is also presented by replacing the grounded capacitance with a CNTFET-based varactor to achieve filter tunability. By controlling the varactor capacitance, active-only second-order fully differential all-pass filter tunability in the range of 15 GHz to 27.5 GHz is achieved. The proposed active-only circuit works on -oltage, low-power dissipation and high tunable pole frequency. The realized circuit operations are verified through the HPSPICE simulation tool. Deng's CNTFET model is utilized to verify the filter performances at the 16 nm technology node. It is seen that the proposed filter simulation justifies the theoretical predictions and works efficiently in the deep-submicron technology. [ABSTRACT FROM AUTHOR]

As the traditional silicon-based CMOS technology advances into the nanoscale stage, approaching its physical limits, the Carbon Nanotube Field-effect Transistor (CNTFET) is considered to be the most significant transistor technology beyond Moore’s era. The CNTFET has a quasi-one-dimensional structure so that the carrier can realize ballistic transport and has very high mobility. At the same time, a single CNTFET can integrate hundreds of nanowires as the conductive channels, enabling significant current transport capabilities even in low supply voltage, thereby providing a foundational basis for achieving nanoscale ultra-large-scale analog/logic circuits. This paper summarizes the development status of the CNTFET compact model and digital/analog/RF integrated circuits. The challenges faced by SPICE modeling and circuit design are analyzed. Meanwhile, solutions to these challenges and development trends of carbon-based transistors are discussed. Finally, the future application prospects of carbon-based integrated circuits are presented.

In this paper, a novel method is presented for the accurate extraction of key parameters of carbon nanotube field-effect transistors (CNTFETs) using S-parameter measurements. An equivalent circuit model, which utilizes lumped components based on the physical characteristics of the device, is employed to model the AC behavior (S-parameters) of the CNTFETs. The proposed method extracts the bias-dependent contact resistance, channel resistance, and gate-channel capacitance from the model at each gate voltage, thereby facilitating the extraction of the effective mobility of the CNT channel. At the last part of this paper, this method is used to quantitatively investigate the impact of electrostatic doping on CNTFETs. This new methodology offers an effective approach for characterizing CNTFETs, which is an important indicator for device optimization. Additionally, the proposed method can be easily applied to other types of FETs.

This paper presents a novel power and energy-efficient carbon nanotube field-effect transistor (CNTFET)-based design of a quaternary magnitude comparator for single and double digits. It also proposes an improved circuit of the ternary single-digit comparator and a novel design of the double-digit ternary comparator. The designs make use of the pass transistor logic and transmission gates, resulting in a more power and energy-efficient design with a lower number of CNTFETs when compared with existing designs. Besides, this paper also proposes a generalized circuit of magnitude comparator for multiple digits. The proposed circuits are simulated in HSPICE using the 32 nm CNTFET model presented by Stanford University. Average power and propagation delays are observed and the power-delay-product (PDP) is calculated in each case. The impact of process parameter variations has been analyzed through Monte Carlo simulation and has been presented in the form of two-dimensional graphs. [ABSTRACT FROM AUTHOR]

In this work, we propose, design and simulate a new configuration of Class AB dual output (DO) second‐generation current conveyor (DO‐CCII). Two versions of this new DO‐CCII configuration are proposed: one employing 32 nm technology‐based carbon nanotube field effect transistor (CNTFET) and the other employing the conventional complementary MOS (CMOS). The HSPICE simulation studies have been performed to evaluate key performance parameters like current and voltage gains, voltage and current bandwidths (BW), the port X and Y resistances, total harmonic distortion of both proposed DO‐CCII configurations. It has been seen that ~388× and ~215× improvement in current and voltage BWs respectively have been achieved in the proposed CNTFET based DO‐CCII (CNTFET‐DO‐CCII) configuration in comparison to its CMOS counterpart (CMOS‐DO‐CCII). Similarly, desired port X and Y resistances have resulted substantially in the CNTFET based DO‐CCII configuration. Further, to evaluate the performance of proposed DO‐CCIIs, some applications such as sinusoidal oscillator, integrator and differentiator have been simulated and compared. In the designed oscillators, the effect of temperature on oscillating frequency has also been studied. A temperature insensitive behavior has been seen in the CNTFET‐DO‐CCII for a wide frequency range. Furthermore, it has been found that the optimization of number of CNTs, CNT diameter and inter‐CNT pitch of CNTFETs improve the performance of the proposed DO‐CCII. [ABSTRACT FROM AUTHOR]

An ultra-low power 8-Transistor Modified Gate Diffusion Input (MGDI) Carbon Nano Tube Field Effect Transistor (CNTFET) Full Adder (FA) has been presented in this paper. The proposed 8-T MGDI CNTFET Full Adder outperforms other adders in terms of Power Consumption, Propagation Delay and the PDP at different levels of Power Supply and Temperatures. The power consumption of the proposed 10 nm CNTFET 8-T MGDI Full Adder at 27°C is 1.96 nW. The proposed CNTFET FA exhibits 60.32% improvement in Power Consumption when compared to the existing 10 nm FINFET 8-T MGDI Full Adder. The propagation Delay of the proposed FA is 42.16 ps and an improvement of 57.68% is noticed over the existing FA. The Power Delay Product of the proposed 10 nm CNTFET 8-T MGDI FA is 82.63 × 10−21 Jules, whereas the PDP of the 10 nm FINFET 8-T MGDI FA is 492.07 × 10−21 Jules. The PDP of the proposed 10 nm CNTFET 8-T MGDI Full Adder exhibits 83.21% improvement when compared to the 10 nm FINFET 8-T MGDI FA. [ABSTRACT FROM AUTHOR]

Summary: Static random‐access memory (SRAM) is a cornerstone in modern microprocessors architecture, as it has high power consumption, large area, and high complexity. Also, the stability of the data in the SRAM against the noise and the performance under the radian exposure are main concern issues. To overcome these limitations in the quest for higher information density by memory element, the ternary logic system has been investigated, showing promising potential compared with the conventional binary base. Moreover, carbon nanotube field effect transistor (CNTFET) is a new alternative device with proper features like low power consumption and threshold voltage dependency on diameter. This paper proposes a new design for ternary SRAM using CNTFET and its evaluation by comparing it against two other designs in many aspects. Moreover, we investigated the static noise margin for the three designs to discuss their stability. Furthermore, we studied the reliability of the designs by evaluating the soft errors effect. [ABSTRACT FROM AUTHOR]

Full adder was also known as basic component in any digital circuitry for microprocessors, digital signal processors and for every processing chip used in nowadays technology. The main purpose of full adder is to do basic logic along with operations of arithmetic's. Thus it allows designer for further advancement of the circuits with improvement in characteristic such as robust, compact, efficient, including scalabilities. Carbon Nanotube Field Effect Transistor (CNTFET) are came into use as substitute of CMOS innovation for planning circuits in the arising innovation. Main moto for this model is to design a advanced and high performable full adder circuit using CNTFET transistor admired by new CMOS full adder plan with cutting edge execution boundaries. To a voltage supply of 0.7V, the quantity of semiconductors was diminished to 10 and furthermore the force was generally separated in two differentiated to the top accessible adder that is based on CNTFET. This plan furnishes checked improvement when contrasted and the current plans like C-CMOS, TFA, TGA, HPSC, 18T-FA adder and so on. Similar information examination show that is 37%, 50%, and 49% improvement as far as territory, delay, and power delay contrasted and both CNTFET and CMOS based adders in existing plans. The circuit was planned in 20nm innovation and reenacted with CADENCE apparatuses. [ABSTRACT FROM AUTHOR]

Abstract A new low‐power and high‐speed multiplier is presented based on the voltage over scaling (VOS) technique and new 5:3 and 7:3 counter cells. The VOS reduces power consumption in digital circuits, but different voltage levels of the VOS increase the delay in different stages of a multiplier. Hence, the proposed counters are implemented by the gate‐diffusion input technique to solve the speed limitation of the VOS‐based circuits. The proposed GDI‐based 5:3 and 7:3 counters save power and reduce the area by 2x and 2.5x, respectively. To prevent the threshold voltage (Vth) drop in the suggested GDI‐based circuits, carbon nanotube field‐effect transistor (CNTFET) technology is used. In the counters, the chirality vector and tubes of the CNTFETs are properly adjusted to attain full‐swing outputs with high driving capability. Also, their validation against heat distribution under different time intervals, as a major issue in the CNTFET technology is investigated, and their very low sensitivity is confirmed. The low complexity, high stability and efficient performance of the presented counter cells introduce the proposed VOS‐CNTFET‐GDI‐based multiplier as an alternative to the previous designs.

This study presents a novel CMOS self-gated flip flop for low power and area efficient applications. The low power operations are achieved by deactivating the clock signal when not required in the circuit. The study explores the proposed design in emergingdevices like Carbon Nanotube Field Effect Transistor (CNTFET), Graphene Nano-Ribbon FET (GNRFET) and FinFET devices. The simulations are carried out at 16nm technology node in HSPICE with nominal conditions of 0.9 V supply voltage, 25% data activity at temperature of 25 °C and frequency of 400 MHz. Results obtained shows that the proposed design consumed the least power with a reduction of minimum 53.68% and maximum 81.39% at variations in voltages ranging from 0.9 V to 1.2 V. The overall power delayproduct (PDP) at nominal conditions is reduced by minimum 61.45% and maximum 80.81%. The proposed flip flop is also an area efficient design having least number of transistors and minimum sum of width with average reduced area of 29.55%. The proposed design, when implemented and simulated with emerging devices, showed significant improvements in power consumptions and speed of operations. The simulations confirmed that the FinFET counterpart of the proposed design is most power efficient device whereas GNRFET the least. But the GNRFET is the fastest of all the devices followed by CNTFET at second and FinFET as third fastest whereas CMOS is the slowest among all these devices.

Carbon nanotubes (CNTs) are nominated to be the successor of several semiconductors and metals due to their unique physical and chemical properties. It has been concerning that the anisotropic and low controllability of CNTs impedes their adoption in commercial applications. Dielectrophoresis (DEP) is known as the electrokinetics motion of polarizable nanoparticles under the influence of nonuniform electric fields. The uniqueness of this phenomenon allows DEP to be employed as a novel method to align, assemble, separate, and manipulate CNTs suspended in liquid mediums. This article begins with a brief overview of CNT structure and production, with the emphasize on their electrical properties and response to electric fields. The DEP phenomenon as a CNT alignment method is demonstrated and graphically discussed, along with its theory, procedure, and parameters. We also discussed the side forces that arise in DEP systems and how they negatively or positively affect the CNT alignment. The article concludes with a brief review of CNT-based devices fabricated using DEP, as well as the method's limitations and future prospects. [ABSTRACT FROM AUTHOR]

In this paper, a multi-digit ternary (multi-trit) Wallace tree-based multiplier in CNTFET technology is presented. In this work, a modified 1-trit multiplier is applied to reduce the number of the CNTFETs where it uses unary operators to estimate the product and the carry. An optimised architecture of a multi-digit ternary adder is also presented. It is applied at the last stage of the multiplier to reduce the overall propagation delay. Hence, higher speed is achieved spending a few more number of CNTFETs. The proposed design is simulated in HSPICE using Stanford University's 32 nm CNFET technology model. Simulation results show significant improvements in power delay products and hardware utilisation. The proposed 3-trit multiplier applies 750 number of CNTFETs where the PDP is 75 fJ. This represents an approximately 20% improvement in the PDP while more than 100 CNTFETs are saved. For further evaluation, the proposed structure is also extended to 6, 9 and 12-trit multipliers. [ABSTRACT FROM AUTHOR]

In this paper, Astable Multivibrator (AMV) circuits are designed and simulated using pure Carbon Nanotube Field Effect Transistors (CNTFETs) as well as hybrid CNT-CMOS technology, and simulation results are compared with conventional CMOS technology by varying the value of resistor- 'R', capacitor- 'C', supply voltage- 'Vdd' and temperature- 'T'. It has been found that novel CNT-based AMV outperforms conventional CMOS-based AMV and the performance of hybrid circuits exists between PURE-CNT-AMV and CMOS-AMV. The rise time and fall time of PURE-CNT-AMV are improved by 97.2% and 96.5% respectively as compared to CMOS-AMV, which increases the speed of operation of the circuit. A significant improvement of approximately 3515% is observed in the slew rate of PURE-CNT-AMV and also, the amplitude of the output square wave is increased by 0.91%. In addition, the maximum usable frequency for PURE-CNT-AMV is increased by 656.96% as compared to CMOS-AMV. Furthermore, the behavior of CNT-based AMV circuits is also analyzed by varying the number of CNTs- 'N', inter CNT pitch- 'S' and CNT diameter- 'DCNT' at R = 50kΩ, C = 1 pf and Vdd = 0.9 V. However, the power dissipation of PURE-CNT-AMV is 3.7% higher than CMOS-AMV which can be improved by adjusting the value of 'R–C' delay network, operating the circuit at lower supply voltage, and choosing the optimum value of N, S and DCNT. [ABSTRACT FROM AUTHOR]

Since 1993, Devices based on CNTs have applicationsranging from nanoelectronics to optoelectronics. Thechallenging issue in designing these devices is that thenonequilibrium Green's function (NEGF) method has tobe employed to solve the Schrödinger and Poissonequations, which is complex and time consuming. In thepresent study, a novel smart and optimal algorithm ispresented for fast and accurate modeling of CNT fieldeffecttransistors (CNTFETs) based on an artificial neuralnetwork. A new and efficient way is presented forincrementally constructing radial basis function (RBF)networks with optimized neuron radii to obtain theestimator network. An incremental extreme learningmachine (I-ELM) algorithm is used to train the RBFnetwork. To ensure the optimal radii for incrementalneurons, this algorithm utilizes a modified version of anoptimization algorithm known as the Nelder-Meadsimplex algorithm. Results confirm that the proposedapproach reduces the network size for faster errorconvergence while preserving the estimation accuracy.