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Object detection plays a crucial role in various cutting-edge applications, such as autonomous vehicles and advanced robotics systems, primarily relying on conventional frame-based RGB sensors. However, these sensors face challenges such as motion blur and poor performance under extreme lighting conditions. Novel event-based cameras, inspired by biological vision systems, offer a promising solution with superior performance in fast-motion and challenging lighting environments while consuming less power. This work explores the integration of event-based cameras with advanced object detection frameworks, introducing Recurrent YOLOv8 (ReYOLOV8), a refined object detection framework that enhances a leading frame-based YOLO detection system with spatiotemporal modeling capabilities by adding recurrency. ReYOLOv8 incorporates a low-latency, memory-efficient method for encoding event data called Volume of Ternary Event Images (VTEI) and introduces a novel data augmentation technique based on Random Polarity Suppression (RPS) optimized for event-based sensors and tailored to leverage the unique attributes of event data. The framework was evaluated using two comprehensive event-based datasets Prophesee's Generation 1 (GEN1) and Person Detection for Robotics (PEDRo). On the GEN1 dataset, ReYOLOv8 achieved mAP improvements of 5%, 2.8%, and 2.5% across nano, small, and medium scales, respectively, while reducing trainable parameters by 4.43% on average and maintaining real-time processing speeds between 9.2 ms and 15.5 ms. For the PEDRo dataset, ReYOLOv8 demonstrated mAP improvements ranging from 9% to 18%, with models reduced in size by factors of 14.5 × and 3.8 × and an average speed improvement of 1.67 ×. The results demonstrate the significant potential of bio-inspired event-based vision sensors when combined with advanced object detection frameworks. In particular, the ReYOLOv8 system effectively bridges the gap between biological principles of vision and artificial intelligence, enabling robust and efficient visual processing in dynamic and complex environments. The codes are available on GitHub at the following link https://github.com/silvada95/ReYOLOv8. [ABSTRACT FROM AUTHOR]

DNA pattern matching is essential for many widely used bioinformatics applications. Disease diagnosis is one of these applications since analyzing changes in DNA sequences can increase our understanding of possible genetic diseases. The remarkable growth in the size of DNA datasets has resulted in challenges in discovering DNA patterns efficiently in terms of run time and power consumption. In this paper, we propose an efficient pipelined hardware accelerator that determines the chance of the occurrence of repeatexpansion diseases using DNA pattern matching. The proposed design parallelizes the DNA pattern matching task using associative memory realized with analog content-addressable memory and implements an algorithm that returns the maximum number of consecutive occurrences of a specific pattern within a DNA sequence. We fully implement all the required hardware circuits with PTM 45-nm technology, and we evaluate the proposed architecture on a practical human DNA dataset. The results show that our design is energy-efficient and accelerates the DNA pattern matching task by more than 100× compared to the approaches described in the literature. [ABSTRACT FROM AUTHOR]

Recent works demonstrated that imperceptible perturbations to input data, known as adversarial examples, can mislead neural networks' output. Moreover, the same adversarial sample can be transferable and used to fool different neural models. Such vulnerabilities impede the use of neural networks in mission-critical tasks. To the best of our knowledge, this is the first paper that evaluates the robustness of emerging CNN- and transformer-inspired image classifier models such as SpinalNet and Compact Convolutional Transformer (CCT) against popular white- and black-box adversarial attacks imported from the Adversarial Robustness Toolbox (ART). In addition, the adversarial transferability of the generated samples across given models was studied. The tests were carried out on the CIFAR-10 dataset, and the obtained results show that the level of susceptibility of SpinalNet against the same attacks is similar to that of the traditional VGG model, whereas CCT demonstrates better generalization and robustness. The results of this work can be used as a reference for further studies, such as the development of new attacks and defense mechanisms. [ABSTRACT FROM AUTHOR]

Local learning schemes have shown promising performance in spiking neural networks (SNNs) training and are considered a step toward more biologically plausible learning. Despite many efforts to design high-performance neuromorphic systems, a fast and efficient on-chip training algorithm is still missing, which limits the deployment of neuromorphic systems in many real-time applications. This work proposes a scalable, fast, and efficient spiking neuromorphic hardware system with on-chip local learning capability. We introduce an effective hardware-friendly local training algorithm compatible with sparse temporal input coding and binary random classification weights. The algorithm is demonstrated to deliver competitive accuracy in different tasks. The proposed digital system explores spike sparsity in communication, parallelism in vector–matrix operations and process-level dataflow, and locality of training errors, which leads to low cost and fast training speed. The system is optimized under various performance metrics. Taking into consideration energy, speed, resources, and accuracy, the proposed method shows around $10\times $ efficiency over a recent work with a direct feedback alignment (DFA) method and $4.5\times $ efficiency over the spike-timing-dependent plasticity (STDP) method. Moreover, our hardware architecture can easily scale up with the network size at a linear rate. Thus, our method has demonstrated great potential for use in various applications, especially those demanding low latency. [ABSTRACT FROM AUTHOR]

The design and development of optimized multiple-input-multiple-output (MIMO) amplify-and-forward relaying strategies based on commonly used equalization criteria is presented.

The design and implementation of a baseband wide-band code-division multiple access (WCDMA) dual-antenna mobile terminal system-on-a-chip (SoC) is presented in this paper. Spatial diversity processing mitigates wireless channel impairments and is a key enabling technology for WCDMA to support high quality of service at high data rates and capacity. The SoC integrates the baseband transceiver, coding and decoding functions, microcontrollers to implement the radio access protocols, and external interfaces to communicate with the application layer. The receiver design, which takes advantage of diversity benefits in several blocks, is described in detail. The SoC was fabricated in a 0.18-[micro]m 1.8-V CMOS technology and requires a total area of 72 [mm.sup.2] consuming 532 mW at the maximum data rates. The application-specific integrated circuit was used in lab testing where a gain of up to 9 dB was observed for the dual-antenna receiver, which demonstrates the tremendous improvement provided by spatial diversity. The results presented in this paper provide a base architecture and a performance benchmark for commercial implementations of WCDMA mobile terminals. Index Terms--Baseband modem, diversity, smart antenna processing, system-on-a-chip (SOC), wide-band code-division multiple access (WCDMA).

The third generation (3G) of cellular communications standards is based on wideband CDMA. The wideband signal experiences frequency selective fading clue to multipath propagation. To mitigate this effect, a RAKE receiver is typically used to coherently combine the signal energy received on different multipaths. An effective multipath searcher is, therefore, required to identify the delayed versions of the transmitted signal with low probability of false alarm and misdetection. This paper presents an efficient and novel WCDMA multipath searcher design and VLSI architecture that provides a good compromise between complexity, performance, and power consumption. Novel multipath searcher algorithms such as time domain interleaving and peak detection are also presented. The proposed searcher was implemented in 0.18 [micro]m CMOS technology and requires only 150 k gates for a total area of 1.5 [mm.sup.2] consuming 6.6 mw at 100 MHz. The functionality and performance of the searcher was verified under realistic conditions using a channel emulator. Index Terms--Direct-sequence CDMA, interleaving, multipath searcher, RAKE receiver, VLSI architecture, WCDMA.

Accelerometers in smart devices have been used to successfully provide valuable information such as early warnings of earthquake activity and health monitoring of buildings. The next important step of using the acceleration measurements from smart devices is to assess building seismic damage, which is a more challenging application. A main challenge is related to the sliding motions of smart devices, which prevents acceleration measurements from directly representing the movement of underlying building floors. To detect and remove sliding motions in acceleration measurements, this paper presents an accurate and robust accelerometer-based stick-slip motion classification framework based on machine learning techniques. Three types of machine learning algorithms are introduced, and their classification performance are compared; support vector machine (SVM), multilayer perception (MLP), and recurrent neural networks (RNN). For the SVM and MLP, three classification conditions are considered: feature selection, non-linear discriminating analysis and classifier comparison. For the RNN, three hyperparameters are considered to find the best performing classification algorithm. Each algorithm is trained and validated with experimental acceleration data from a shaking table test. [ABSTRACT FROM AUTHOR]

In-memory computing is an emerging computing paradigm that overcomes the limitations of exiting Von-Neumann computing architectures such as the memory-wall bottleneck. In such paradigm, the computations are performed directly on the data stored in the memory, which highly reduces the memory-processor communications during computation. Hence, significant speedup and energy savings could be achieved especially with data-intensive applications. Associative processors (APs) were proposed in the seventies and recently were revived thanks to the high-density memories. In this tutorial brief, we overview the functionalities and recent trends of APs in addition to the implementation of each content-addressable memory with different technologies. The AP operations and runtime complexity are also summarized. We also explain and explore the possible applications that can benefit from APs. Finally, the AP limitations, challenges, and future directions are discussed. [ABSTRACT FROM AUTHOR]

Millimeter wave (mmWave) massive multiple-input multiple-output (MIMO) systems typically employ hybrid mixed signal processing to avoid expensive hardware and high training overheads. However, the lack of fully digital beamforming at mmWave bands imposes additional challenges in channel estimation. Prior art on hybrid architectures has mainly focused on greedy optimization algorithms to estimate frequency-flat narrowband mmWave channels, despite the fact that in practice, the large bandwidth associated with mmWave channels results in frequency-selective channels. In this paper, we consider a frequency-selective wideband mmWave system and propose two deep learning (DL) compressive sensing (CS) based algorithms for channel estimation. The proposed algorithms learn critical apriori information from training data to provide highly accurate channel estimates with low training overhead. In the first approach, a DL-CS based algorithm simultaneously estimates the channel supports in the frequency domain, which are then used for channel reconstruction. The second approach exploits the estimated supports to apply a low-complexity multi-resolution fine-tuning method to further enhance the estimation performance. Simulation results demonstrate that the proposed DL-based schemes significantly outperform conventional orthogonal matching pursuit (OMP) techniques in terms of the normalized mean-squared error (NMSE), computational complexity, and spectral efficiency, particularly in the low signal-to-noise ratio regime. When compared to OMP approaches that achieve an NMSE gap of $\mathrm {\{4-10\}\,\,dB}$ with respect to the Cramer Rao Lower Bound (CRLB), the proposed algorithms reduce the CRLB gap to only $\mathrm {\{1-1.5\}\,\,dB}$ , while reducing complexity by two orders of magnitude. [ABSTRACT FROM AUTHOR]

The bottleneck between the processor and memory is the most significant barrier to the ongoing development of efficient processing systems. Therefore, a research effort begun to shift from processor-centric architectures to memory-centric architectures. Various in-memory processor architectures have been proposed to break this barrier to pave the way for ever-demanding memory-bound applications. Associative in-memory processing is a successful candidate for truly in-memory computing, in which processor and memory are combined in the same location to eliminate the expensive data access costs. The architecture exhibits an unmatched advantage for data-intensive applications due to its memory-centric design principles. On the other hand, this advantage can be revealed fully by an efficient design methodology. This study puts further progressive effort by proposing a hardware/software design methodology for associative in-memory processors. The methodology aims to decrease energy consumption and area requirement of the processor architecture specifically programmed to perform a given task. According to the evaluation of nine different benchmarks, such as fast Fourier transform and multiply-accumulate, the proposed design flow accomplishes an average ∼7% reduction in memory area and ∼18% savings in total energy consumption. • A hardware/software co-design flow specific to associative in-memory processors. • Programming language, scheduler, and power optimizer for associative processors. • An improved depth-first search (DFS)-based scheduler for energy and area optimization. • A multi − V DD design technique by multi-banking and dynamic voltage scaling. [ABSTRACT FROM AUTHOR]

The automatic fitting of spiking neuron models to experimental data is a challenging problem. The integrate and fire model and Hodgkin–Huxley (HH) models represent the two complexity extremes of spiking neural models. Between these two extremes lies two and three differential-equation-based models. In this work, we investigate the problem of parameter estimation of two simple neuron models with a sharp reset in order to fit the spike timing of electro-physiological recordings based on two problem formulations. Five optimization algorithms are investigated; three of them have not been used to tackle this problem before. The new algorithms show improved fitting when compared with the old ones in both problems under investigation. The improvement in fitness function is between 5 and 8%, which is achieved by using the new algorithms while also being more consistent between independent trials. Furthermore, a new problem formulation is investigated that uses a lower number of search space variables when compared to the ones reported in related literature. [ABSTRACT FROM AUTHOR]

Accelerometers in smart devices have been used to successfully detect the occurrence of seismic activity. Taking the next step of using the measured acceleration response to compute floor displacements for the purpose of assessing building seismic damage is a more challenging application. In particular, sliding of smart devices or their underlying support hinders their use for this purpose because that means that the floor drifts cannot be directly measured using the onboard sensors. This paper discusses the dynamic behavior of a free-standing smart device and presents a method for estimating the kinetic coefficient of friction between the smart device and the underlying surface based on wavelet transforms. A methodology is then presented by which a smart device can decide if its motion is representative of the motion of the floor underneath or whether it is tainted by excessive sliding action. The noise associated with a smart device's measurement of acceleration is established and noise reduction methods to overcome them are compared. Computational simulation results and experimental data are used to demonstrate the concepts discussed in this paper. [ABSTRACT FROM AUTHOR]

Assessing the structural integrity of buildings after an earthquake is necessary for citizens to be able to use these facilities safely after the event. The currently available structural health monitoring (SHM) systems use a dense network of sensors installed in buildings to monitor their behavior during earthquakes. Such a network is impractical with respect to cost and deployment time for the vast majority of buildings; therefore, most structures remain uninstrumented. However, a massive network of citizen-owned smart devices, such as tablets and smartphones that contain cameras and vibration sensors, has already been deployed. This paper develops a framework that can crowdsource readings from distributed citizen-owned smart devices and convert these readings into actionable information. Although prior community-based seismic research focused on using smartphones to provide early disaster warnings, the proposed system focuses specifically on using video captured on a smartphone to directly assess the structural health of buildings post-earthquake, thus providing citizens and emergency personnel with immediate relevant information regarding the health state of buildings. This paper presents a novel self-calibration technique for a smartphone camera using its internal accelerometer readings. Shake table experiments show that the proposed technique can achieve sub-millimeter accuracy, demonstrating its suitability for SHM applications. [ABSTRACT FROM AUTHOR]

Various hypotheses of information representation in brain, referred to as neural codes, have been proposed to explain the information transmission between neurons. Neural coding plays an essential role in enabling the brain-inspired spiking neural networks (SNNs) to perform different tasks. To search for the best coding scheme, we performed an extensive comparative study on the impact and performance of four important neural coding schemes, namely, rate coding, time-to-first spike (TTFS) coding, phase coding, and burst coding. The comparative study was carried out using a biological 2-layer SNN trained with an unsupervised spike-timing-dependent plasticity (STDP) algorithm. Various aspects of network performance were considered, including classification accuracy, processing latency, synaptic operations (SOPs), hardware implementation, network compression efficacy, input and synaptic noise resilience, and synaptic fault tolerance. The classification tasks on Modified National Institute of Standards and Technology (MNIST) and Fashion-MNIST datasets were applied in our study. For hardware implementation, area and power consumption were estimated for these coding schemes, and the network compression efficacy was analyzed using pruning and quantization techniques. Different types of input noise and noise variations in the datasets were considered and applied. Furthermore, the robustness of each coding scheme to the non-ideality-induced synaptic noise and fault in analog neuromorphic systems was studied and compared. Our results show that TTFS coding is the best choice in achieving the highest computational performance with very low hardware implementation overhead. TTFS coding requires 4x/7.5x lower processing latency and 3.5x/6.5x fewer SOPs than rate coding during the training/inference process. Phase coding is the most resilient scheme to input noise. Burst coding offers the highest network compression efficacy and the best overall robustness to hardware non-idealities for both training and inference processes. The study presented in this paper reveals the design space created by the choice of each coding scheme, allowing designers to frame each scheme in terms of its strength and weakness given a designs' constraints and considerations in neuromorphic systems. [ABSTRACT FROM AUTHOR]

Traditional convolutional neural network (CNN) architectures suffer from two bottlenecks: computational complexity and memory access cost. In this study, an efficient in-memory convolution accelerator (IMCA) is proposed based on associative in-memory processing to alleviate these two problems directly. In the IMCA, the convolution operations are directly performed inside the memory as in-place operations. The proposed memory computational structure allows for a significant improvement in computational metrics, namely, TOPS/W. Furthermore, due to its unconventional computation style, the IMCA can take advantage of many potential opportunities, such as constant multiplication, bit-level sparsity, and dynamic approximate computing, which, while supported by traditional architectures, require extra overhead to exploit, thus reducing any potential gains. The proposed accelerator architecture exhibits a significant efficiency in terms of area and performance, achieving around 0.65 GOPS and 1.64 TOPS/W at 16-bit fixed-point precision with an area less than 0.25 mm2. [ABSTRACT FROM AUTHOR]

To tackle real-world challenges, deep and complex neural networks are generally used with a massive number of parameters, which require large memory size, extensive computational operations, and high energy consumption in neuromorphic hardware systems. In this work, we propose an unsupervised online adaptive weight pruning method that dynamically removes non-critical weights from a spiking neural network (SNN) to reduce network complexity and improve energy efficiency. The adaptive pruning method explores neural dynamics and firing activity of SNNs and adapts the pruning threshold over time and neurons during training. The proposed adaptation scheme allows the network to effectively identify critical weights associated with each neuron by changing the pruning threshold dynamically over time and neurons. It balances the connection strength of neurons with the previous layer with adaptive thresholds and prevents weak neurons from failure after pruning. We also evaluated improvement in the energy efficiency of SNNs with our method by computing synaptic operations (SOPs). Simulation results and detailed analyses have revealed that applying adaptation in the pruning threshold can significantly improve network performance and reduce the number of SOPs. The pruned SNN with 800 excitatory neurons can achieve a 30% reduction in SOPs during training and a 55% reduction during inference, with only 0.44% accuracy loss on MNIST dataset. Compared with a previously reported online soft pruning method, the proposed adaptive pruning method shows 3.33% higher classification accuracy and 67% more reduction in SOPs. The effectiveness of our method was confirmed on different datasets and for different network sizes. Our evaluation showed that the implementation overhead of the adaptive method regarding speed, area, and energy is negligible in the network. Therefore, this work offers a promising solution for effective network compression and building highly energy-efficient neuromorphic systems in real-time applications. [ABSTRACT FROM AUTHOR]

Aims: Worsening of renal function (WRF) is a common complication in patients with acute decompensated heart failure (ADHF). We aimed to evaluate the role of intrarenal Doppler ultrasound (IRD) in the early prediction of WRF in this patient group. Methods and results: Among 90 patients (age: 57.5 ± 11.1 years; 62% male) hospitalized with ADHF, resistivity index (RI), acceleration time (AT), and pulsatility index (PI) were measured on admission and at 24 and 72 h. WRF was defined as increased serum creatinine ≥0.3 mg/dL from baseline. Adverse clinical outcomes were defined as the composite of death, use of vasopressors, and need for ultrafiltration for refractory oedema. WRF developed in 40% of patients. Mean values of renal AT, RI, and PI on admission were 59.7 ± 15, 0.717 ± 0.08, and 1.5 ± 0.48 ms, respectively. At 24 h, there was significant decrease in AT (to 56.7 ± 10 ms, P = 0.02) and renal RI (to 0.732 ± 0.07; P < 0.001); these changes were maintained up to 72 h. Renal PI showed no significant changes. Independent predictors of WRF were renal AT at 24 h and admission values of renal RI, left ventricular ejection fraction, and plasma cystatin C. Renal AT at 24 h ≥ 57.8 ms had 89% sensitivity and 70% specificity for the prediction of WRF. Independent predictors for adverse clinical outcomes were left ventricular end systolic dimension and WRF. Conclusions: Among ADHF patients receiving diuretic therapy, measurement of renal AT and RI by IRD can help identify patients at increased risk for WRF. [ABSTRACT FROM AUTHOR]

Smartphones are an indispensable tool in modern day-to-day life. Their widespread use has spawned numerous applications targeting diverse domains, such as biomedical, environment sensing, and infrastructure monitoring. In such applications, the accuracy of the sensors at the core of the system is still questionable since these devices are not originally designed for high-accuracy sensing purposes. In this article, we investigate the accuracy limits of one of the commonly used sensors, namely, smartphone accelerometer. We focus on the efficacy of a smartphone as an acceleration measuring device, rather than focusing only on the accuracy of its internal accelerometer chip. This holistic approach includes additional errors that arise from the device operating system, such as sampling time uncertainty. Hence, we propose a novel smart device accelerometer error model that includes the traditional additive noise as well as sampling time uncertainty errors represented by a white Gaussian process. The model is validated experimentally using shake table experiments, and the maximum likelihood estimation (MLE) is used to estimate the sampling time uncertainty standard deviation. Moreover, we derive the Cramer–Rao lower bound (CRLB) of acceleration estimation based on the proposed model. [ABSTRACT FROM AUTHOR]

Continuous structural health monitoring of civil infrastructure can be achieved by deploying an Internet of Things network of distributed acceleration sensors in buildings to capture floor movement. Postdisaster damage levels can be computed based on the peak relative floor displacement as specified in government standards. This article uses machine learning approaches to identify the status of buildings postevent based on accelerometer traces. Prior work in the field assumed the use of high-quality accelerometers for displacement estimation. In this article, we focus on using lower quality and cheaper accelerometers, while accounting for noise effects by incorporating noisy data sets in machine learning approaches for classification. A labeled acceleration data set of buildings response to earthquakes was created, where each sample is labeled with its corresponding damage severity. Sensor noise is included in the data set to model nonideal sensors. Classification performance of machine learning algorithms, such as support vector machine, K-nearest neighbor, and convolutional neural network, is presented. Techniques for addressing noise levels are proposed, and the results are compared with regular noise cancellation techniques that adopt high-pass filtering. Note to Practitioners—This article presents a methodology for automatic estimation of buildings status in the aftermath of a natural disaster, such as an earthquake. It focuses on using low-cost inertial sensors, such as accelerometers, to sense buildings’ vibrations and then applying machine learning algorithms to detect damage. Utilizing the convolutional network approach, the proposed methods detect the building damage state with high accuracy. Since this article focuses on using cheap sensors, the cost of deploying a sensor network to monitor buildings is reduced significantly. Deploying this network enables rescue and reconnaissance teams to have a clear view of the most vulnerable structures. [ABSTRACT FROM AUTHOR]

Natural disasters affect structural health of buildings, thus directly impacting public safety. Continuous structural monitoring can be achieved by deploying an Internet of things network of distributed sensors in buildings to capture floor movement. These sensors can be used to compute the displacements of each floor, which can then be employed to assess building damage after a seismic event. The peak relative floor displacement is computed, which is directly related to damage level according to the United States federal agencies standards. With this information, the building inventory can be classified into immediate occupancy, life safety, or collapse prevention categories. In this paper, we propose a zero velocity update technique to minimize displacement estimation error. Theoretical derivation and experimental validation are presented. In addition, we investigate modeling sensor error and interstory drift ratio distribution. Moreover, we discuss the impact of sensor error on the achieved building classification accuracy. [ABSTRACT FROM AUTHOR]