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This paper presents a transition‐limited pulse‐amplitude modulation (TLPAM) signaling method to enable a high data rate and robust wireline communications. TLPAM signaling addresses the impact of high intersymbol interference (ISI) ratios in conventional M‐ary PAM signaling methods by limiting the maximum voltage transition level between adjacent symbols. The implementation of a TLPAM signaling encoder is realized by setting back the most significant bits (MSBs) in the queue. The correlation between TLPAM's maximum transition level, effective data rate, and eye width/height is analyzed with various channel loss parameters, followed by characterization and measurement results with a realistic channel setup. The analysis and experimental results reveal the effectiveness of the proposed TLPAM signaling scheme for achieving a high data rate with minimal interference. [ABSTRACT FROM AUTHOR]

This paper addresses the protection capability of a runway pavement by executing a field blast test on an airfield pavement subjected to blast loading from a CBU (cluster bomb unit), and by confirming the numerical simulation of warhead penetration and the form of damage. The CBU's blast loading applies the BAP 100 of an air-to-ground munition in a similar scale. Penetration depth is calculated by a formula which incorporates the terminal speed of a free-falling cluster munition dispersed 20 km above the ground. According to the result of the calculation, the penetration depth by a cluster munition is 33 cm from the surface of the pavement. The field blast test was conducted based on this result. Furthermore, LS-DYNA software simulation was used to assess the condition of damage, determined by the depth of penetration and explosive pressure from a free-falling CBU landing on the airfield pavement from 20 km above the ground. The condition was ultimately used to verify the result of field testing and to confirm the scale of damage repair. The depth of explosion was 78 cm, from the surface to the crushed stone and sand layer below the pavement, and the diameter was 30 cm. The size of the crushed concrete that needed to be removed was an average diameter of 156 cm. The simulation result confirms that the diameter and depth of the crater are 67.6 cm and 67 cm, respectively, when the CBU is detonated under the same depth as the field testing, and the height of upheaval is 12 cm. The most appropriate method for repair, after a series of reviews, is to cut and remove a concrete slab 1.8 m × 1.8 m and cast the crushed stone layer disrupted from the explosion, followed by repairing the removed damaged concrete slab sections using rapid hardening concrete. [ABSTRACT FROM AUTHOR]

This article presents a 200-Gb/s pulse amplitude-modulation four-level (PAM-4) and 100-Gb/s non-return-to-zero (NRZ) transmitter (TX) in 28-nm CMOS technology. To achieve the target data rate, the output bandwidth and swing of the proposed TX are optimized by minimizing the output capacitance of the 4:1 multiplexer (MUX) and driver stage with pull-up current sources and adopting a fully reconfigurable 5-tap feed-forward equalizer (FFE). The key circuit includes a segmented 8:4 MUX and 4:1 MUX/driver, a thermal encoder and retimer, and a flexible clock distribution network. Using the layout generated with Berkeley Analog Generator (BAG), the proposed TX achieves an eye opening with >52.9-mV eye height, 0.36 UI eye width, >98% RLM, and 4.63 pJ/b at 200-Gb/s PAM-4 signaling under >6-dB channel loss at 50 GHz, demonstrating the highest data rate achieved using a planar process. [ABSTRACT FROM AUTHOR]

Raw data acquired by imaging devices are converted into digital images by post-processing algorithms. However, these algorithms are significantly affected by numerous illumination conditions. Particularly, in the case in which illumination conditions depend on canonical light sources, unwanted light sources that locally illuminate the scene or mixed light from several light sources are recognized as the spatially varying illumination conditions. These complex illumination conditions cause several artifacts by affecting the digital image acquisition process. For example, optical aberrations are generated by refraction of complex light, or illumination estimation is significantly affected by the different color temperatures of multiple light sources. To overcome these problems, this study proposes an algorithm that decomposes the complex illumination from several light sources. First, the spatially varying illumination condition is discussed, and the artifacts generated by the conditions, such as false colors and aberrations, are analyzed. Second, mixed light from several canonical light sources is decomposed based on the imaging devices and spectral information of the canonical light sources. The proposed method has low complexity and increased applicability. Furthermore, the improvement scheme based on the proposed method has a parallelized structure and can be easily applied to various types of algorithms, such as color constancy, deconvolution, denoising, and contrast enhancement. The algorithms employing the improvement scheme show the potential of the proposed method for solving the problems associated with multiple light sources. [ABSTRACT FROM AUTHOR]

This paper demonstrates a signal analysis system-on-chip (SoC) consisting of a general-purpose RISC-V core with vector extensions and a fixed-function signal-processing accelerator. Both the application core and the accelerators are design instances produced through an agile design-space exploration process by generators that allow for a wide range of parameter configurations. The signal processing chain consists of generated instances of a time-interleaved analog-to-digital converter (ADC) followed by a digital tuner, a finite-impulse response (FIR) filter, a polyphase filter, and a fast Fourier transform (FFT) all connected to the five-stage, in-order RISC-V Rocket processor via an AXI4 bus. The generator-based design methodology is detailed, along with the agile design process of producing the fabricated design instance. The $5\,\,\text {mm}\times 5\,\,\text {mm}$ chip is implemented in a 16-nm FinFET process and operates at 410 MHz at 750 mV drawing 600 mW. Presented applications show coupled functionality of the application processor and accelerator performing spectrometry and radar receive processing, and a comparison with other state-of-the-art application-specific integrated circuits (ASICs) proves that generators can produce performance-competitive designs. [ABSTRACT FROM AUTHOR]

A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis system-on-chip (SoC), integrating a subsampling analog-to-digital converter (ADC) frontend with a digital reconstruction backend and implementing a 21 600-point sparse Fourier transform based on the fast Fourier aliasing-based sparse transform (FFAST) algorithm has been co-designed by using the Constructing Hardware in a Scala Embedded Language (Chisel) and Berkeley Analog Generator (BAG) circuit generator frameworks in 16-nm CMOS. Three sets of $25\times $ , $27\times $ , and $32\times $ subsampling successive approximation register (SAR) ADCs acquire signal with ~5.4–6.3 effective number of bits (ENOB)/slice. The digital backend consists of mixed-radix 864-, 800-, and 675-point fast Fourier transforms (FFTs), a signal location estimator, and a peeling decoder that recovers aliased signals from a sparsely populated spectrum. A single-issue, in-order, fifth-generation reduced instruction set (RISC-V) Rocket processor interacts with the spectrum analyzer for post-processing and calibration. The ADC consumes 49.8 mW with a 3.78-GHz reference clock. At 400 MHz and 0.7-V digital supply voltage (VDD), the Rocket core and the FFAST digital signal processing (DSP) together consume 133.5 mW. [ABSTRACT FROM AUTHOR]

Supporting a wide operating range for industrial-standard backward-compatible transmitters often results in energy inefficiency. This paper describes an energy-efficient voltage-mode-serializing transmitter with an operating range of up to 32 Gb/s. The proposed transmitter uses a programmable internal supply to set the voltage level for various data rates optimally, thus improving overall energy efficiency. Output swing and pre-emphasis levels are largely adjustable while the constant output impedance is maintained using a dedicated control loop. CMOS-logic-based circuits and quarter-rate clocking enhance the energy efficiency over the entire data rate range, while a P-over-N voltage-mode driver is used to achieve a high maximum output swing. Two supply regulators with replicas provide constant pull-up and pull-down impedances of the output driver. The variable output swing, pre-emphasis, and internal supply are realized by using segmented output drivers and replicas. The proposed transmitter, fabricated in a 65-nm CMOS process, occupies an active area of 0.173 mm2. The prototype chip achieves a wide output swing range of 0.4–1.3 Vppd and an energy efficiency of 2.10–3.45 pJ/bit, across a data rate of 5 –32 Gb/s. [ABSTRACT FROM PUBLISHER]

A 40–56 Gb/s PAM-4 receiver with ten-tap decision-feedback equalization (DFE) targeting chip-to-module and board-to-board cable interconnects is designed in 16-nm FinFET. The design implements direct feedback of the first post-cursor (h1) DFE tap to reduce the number of slicers. The h1 feedback signals are directly tapped from the master latch output of the StrongArm-based slicers. A CMOS amplifier with delayed pre-charge release is used to boost and pre-condition the h1 feedback signals before being applied to current-mode logic tap cell for optimum DFE summer settling time. The receiver achieves less than 1E-12 PRBS31 bit error rate (BER) over a channel with 10-dB loss at 14-GHz consuming 230 mW. Fully adapted by off-chip software, the receiver performance demonstrates the effectiveness of direct h1 loop and the need for higher DFE taps to achieve a required BER over channels with reflections. Receiver performance over higher loss channels up to 23 dB and/or under emulated cross-talk noise injection cases are also presented. [ABSTRACT FROM AUTHOR]

Design techniques for a complete 60-Gb/s non-return-to-zero transceiver with adaptive equalization as well as baud-rate clock and data recovery (CDR) are demonstrated. A complete equalization front end with per-path adaptation and per-sampler offset calibration enables 60-Gb/s operation over realistic channels. Current integration in the front end for energy-efficient equalization is combined with integration phase dithering to realize a robust baud-rate CDR. Correlation of the adaptive error sampler output with the phase dithering sequence indicates the direction of phase offset, and the resulting baud-rate CDR saves power and complexity compared to an oversampling CDR by not requiring additional clock phases/deserializers. The proposed 65-nm CMOS transceiver operates at 60 Gb/s with an eye opening of 30% UI and consumes 288 mW while equalizing 21 dB of loss at 30 GHz over a 0.7-m Twinax cable. [ABSTRACT FROM AUTHOR]

Design techniques for a complete 60 Gb/s receiver frontend with equalization, output slicing/demultiplexing, and clocking capabilities are described. Current integration combined with a cascode gate-voltage bias gain-control technique enables energy-efficient implementation of CTLE, FFE, and DFE circuits while operating near the speed limits of the technology. Despite following the DFE that has already in principle sliced the data, adaptive error-sampling requires high gain to resolve small residual error signals—this challenge is addressed by the addition of interleaved, offset-canceled deserializing samplers. Clock generation as well as distribution circuits are implemented to complete the receiver frontend. The proposed 65 nm CMOS receiver operates at 60 Gb/s, consuming 173 mW from 1.2 V and 1.0 V supplies. [ABSTRACT FROM PUBLISHER]

• The proposed prior selection strategy based on maximum a posteriori estimation achieves the optimal image prior without additional attempts. • The developed statistical modeling method generalizes the heavy-tailed gradient distributions of images based on the kurtosis. • An ADMM-based scheme is adopted with IRLS to reduce the complexity of non-convex image deconvolution problem. • The proposed method shows high performance in restoring the textures of the images. The natural image prior generalizes the heavy-tailed gradient distributions of clear images to L p regularized problems in the image deconvolution process. Employing a maximum a posteriori estimator, this prior should be carefully selected to precisely model the gradient statistics of the corresponding natural image. However, in several deconvolution algorithms, p has been randomly determined to obtain a high-quality image without considering the essence of the image prior. In this study, we proposed an automatic prior selection strategy based on the statistical properties of restored images. The probabilistic characteristics of the images were derived and investigated by statistically modeling the individual gradient distributions. Subsequently, the regularization term of the objective function was iteratively updated based on the analysis of image restoration. Instead of the unavailable original images, we focused on the utilization of the observed image to estimate the image prior. Overcoming the ill-posedness of the prior selection problem, the proposed algorithm achieved the optimal image prior and effectively restored the degraded image simultaneously. [ABSTRACT FROM AUTHOR]

This paper presents a duty cycle correction scheme based on asynchronous sampling and associated settling analysis. The proposed duty cycle corrector circuit consumes less power and area compared to other corrector circuits due to the low-frequency operation of asynchronous sampling. However, the settling behavior of an asynchronous sampling duty cycle corrector is limited in some operation conditions, which degrades its robustness and performance. This paper, therefore, performs analysis on the settling behavior of the asynchronous sampling in various operating conditions and proposes a control scheme to avoid the lagged settling. To verify the proposed duty cycle corrector and its analysis, a prototype design is implemented in a 40-nm CMOS process and its performance is verified by post-layout simulations. The proposed duty cycle corrector achieved very small duty cycle errors (less than 0.8%) and consumed 540 uW per one DCC unit. [ABSTRACT FROM AUTHOR]

An imaging system has natural statistics that reflect its intrinsic characteristics. For example, the gradient histogram of a visible light image generally obeys a heavy-tailed distribution, and its restoration considers natural statistics. Thermal imaging cameras detect infrared radiation, and their signal processors are specialized according to the optical and sensor systems. Thermal images, also known as long wavelength infrared (LWIR) images, suffer from distinct degradations of LWIR sensors and residual nonuniformity (RNU). However, despite the existence of various studies on the statistics of thermal images, thermal image processing has seldom attempted to incorporate natural statistics. In this study, natural statistics of thermal imaging sensors are derived, and an optimization method for restoring thermal images is proposed. To verify our hypothesis about the thermal images, high-frequency components of thermal images from various datasets are analyzed with various measures (correlation coefficient, histogram intersection, chi-squared test, Bhattacharyya distance, and Kullback–Leibler divergence), and generalized properties are derived. Furthermore, cost functions accommodating the validated natural statistics are designed and minimized by a pixel-wise optimization method. The proposed algorithm has a specialized structure for thermal images and outperforms the conventional methods. Several image quality assessments are employed for quantitatively demonstrating the performance of the proposed method. Experiments with synthesized images and real-world images are conducted, and the results are quantified by reference image assessments (peak signal-to-noise ratio and structural similarity index measure) and no-reference image assessments (Roughness (Ro) and Effective Roughness (ERo) indices). [ABSTRACT FROM AUTHOR]

Image deconvolution is an ill-posed problem that usually requires prior knowledge for regularizing the feasible solutions. In literature, iterative methods estimate an intrinsic image, minimizing a cost function regularized by specific prior information. However, it is difficult to directly minimize the constrained cost function, if a nondifferentiable regularization (e.g., the sparsity constraint) is employed. In this paper, we propose a nonderivative image deconvolution algorithm that solves the under-constrained problem (i.e., a non-blind image deconvolution) by successively solving the permuted subproblems. The subproblems, arranged in permuted sequences, directly minimize the nondifferentiable cost functions. Various Lp-regularized (0 < p ≤ 1, p = 2) objective functions are utilized to demonstrate the pixel-wise optimization, in which the projection operator generates simplified, low-dimensional subproblems for estimating each pixel. The subproblems, after projection, are dealt with in the corresponding hyperplanes containing the adjacent pixels of each image coordinate. Furthermore, successively solving the subproblems can accelerate the deconvolution process with a linear speed-up, by parallelizing the subproblem sequences. The image deconvolution results with various regularization functionals are presented and the linear speed-up is also demonstrated with a parallelized version of the proposed algorithm. Experimental results demonstrate that the proposed method outperforms the conventional methods in terms of the improved-signal-to-noise ratio and structural similarity index measure.