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Abstract In this paper, we introduce a novel Forkshape nanosheet Inductive Tunnel Field-Effect Transistor (FS-iTFET) featuring a Gate-All-Around structure and a full-line tunneling heterojunction channel. The overlapping gate and source contact regions create a strong and uniform electric field in the channel. Furthermore, the metal–semiconductor Schottky junction in the intrinsic source region induces the required carriers without the need for doping. This innovative design achieves both a steeper subthreshold swing (SS) and a higher ON-state current (I ON). Using calibration-based simulations with Sentaurus TCAD, we compare the performance of three newly designed device structures: the conventional Nanosheet Tunnel Field-Effect Transistor (NS-TFET), the Nanosheet Line-tunneling TFET (NS-LTFET), and the proposed FS-iTFET. Simulation results show that, compared to the traditional NS-TFET, the NS-LTFET with its full line-tunneling structure improves the average subthreshold swing (SS AVG) by 19.2%. More significantly, the FS-iTFET, utilizing the Schottky-inductive source, further improves the SS AVG by 49% and achieves a superior I ON/I OFF ratio. Additionally, we explore the impact of Trap-Assisted Tunneling on the performance of the three different integrations. The FS-iTFET consistently demonstrates superior performance across various metrics, highlighting its potential in advancing tunnel field-effect transistor technology.

Abstract Nanosheet transistors are poised to become the preferred choice for the next generation of smaller-sized devices in the future. To address the future demand for high-performance and low-power computing applications, this study proposes a nanosheet structure with a vertically stacked design, featuring a high I ON/I OFF ratio. This Nanosheet design is combined with an induced tunnel field-effect transistor. By utilizing SiGe with a carrier mobility three times that of Si and employing a line tunneling mechanism, the research successfully achieves superior Band to Band characteristics, resulting in improved switching behavior and a lower Subthreshold Swing (SS). Comparative studies were conducted on three TFET types: Nanosheet PIN TFET, Nanosheet Schottky iTFET, and Fin iTFET. Results show that the Nanosheet PIN TFET has a higher I ON/I OFF ratio but poorer SSavg values at 47.63 mV/dec compared to the others. However, with a SiGe Body thickness of 3 nm, both Nanosheet iTFET and Fin iTFET exhibit higher I ON/I OFF ratios and superior SSavg values at 17.64 mV/dec. These findings suggest the potential of Nanosheet iTFET and Fin iTFET for low-power, lower thermal budgets, and fast-switching applications.

Abstract In this paper, we propose the use of punch-through nMOS (PTnMOS) as an alternative to pMOS in complementary metal oxide semiconductor (CMOS) circuits. According to the TCAD simulation results, PTnMOS exhibit sub-threshold characteristics similar to those of pMOS and can be formed by simply changing the doping concentration of the source and drain. Without the need for sizing, which solves the area occupation problem caused by the need to increase the width of pMOS due to insufficient hole mobility. In addition, we compose a PTnMOS and nMOS without sizing to form a single-carrier CMOS in which only electrons are transmitted, and We extract its performance for comparison with conventional CMOS (Wp/Wn = 1). The results indicate that single-carrier CMOS has symmetric noise margin and 29% faster delay time compared to conventional CMOS (Wp/Wn = 1). If III–V or II–VI group materials could be applied to single-carrier CMOS, not only could costs be reduced and wafer area occupancy minimized, but also significant improvements in the performance and bandwidth application of microwave circuits could be achieved.

Abstract In this paper, we present a new novel simple iTFET with overlapping gate on source-contact (SGO), Drain Schottky Contact, and intrinsic SiGe pocket (Pocket-SGO iTFET). The aim is to achieve steep subthreshold swing (S.S) and high I ON current. By optimizing the gate and source-contact overlap, the tunneling efficiency is significantly enhanced, while the ambipolar effect is suppressed. Additionally, using a Schottky contact at the drain/source, instead of ion implantation drain/source, reduces leakage current and thermal budget. Moreover, the tunneling region is replaced by an intrinsic SiGe pocket posing a narrower bandgap, which increases the probability of band-to-band tunneling and enhances the I ON current. Our simulations are based on the feasibility of the actual process, thorough Sentaurus TCAD simulations demonstrate that the Pocket-SGO iTFET exhibits an average and minimum subthreshold swing of S.S avg = 16.2 mV/Dec and S.S min = 4.62 mV/Dec, respectively. At V D = 0.2 V, the I ON current is 1.81 $$\times$$ × 10–6 A/μm, and the I ON/I OFF ratio is 1.34 $$\times$$ × 109. The Pocket-SGO iTFET design shows great potential for ultra-low-power devices that are required for the Internet of Things (IoT) and AI applications.

Abstract In this paper, we propose an inductive line tunneling FET using Epitaxial Tunnel Layer with Ge-Source and Charge Enhancement Insulation (CEI ETL GS-iTFET). The CEI ETL GS-iTFET allows full overlap between the gate and source regions, thereby enhancing the line tunneling. In addition, a germanium layer is introduced on the source side to form a heterojunction, effectively improving the device's conduction current. An ETL is incorporated to combat point tunneling leakage, resulting in a steeper subthreshold swing. Furthermore, a CEI consisting of Si3N4 is introduced between the germanium source and the Schottky metal, which effectively reduces carrier losses in the inversion layer and improves the overall device performance. This study presents a calibration-based approach to simulations, taking into account practical process considerations. Simulation results show that at V D = 0.2 V, the CEI ETL GS-iTFET achieves an average subthreshold swing (SS avg) of 30.5 mV/dec, an I on of 3.12 × 10–5 A/μm and an I on/I off ratio of 1.81 × 1010. These results demonstrate a significantly low subthreshold swing and a high current ratio of about 1010. In addition, the proposed device eliminates the need for multiple implantation processes, resulting in significant manufacturing cost reductions. As a result, the CEI ETL GS-iTFET shows remarkable potential in future low-power device competition.

Abstract This article presents a new line tunneling dominating metal–semiconductor contact-induced SiGe–Si tunnel field-effect transistor with control gate (CG-Line SiGe/Si iTFET). With a structure where two symmetrical control gates at the drain region are given a sufficient negative bias, the overlap of the energy bands at the drain in the OFF-state is effectively suppressed, thus reducing the tunneling probability and significantly decreasing leakage current. Additionally, the large overlap area between the source and gate improves the gate’s ability to control the tunneling interface effectively, improving the ON-state current and subthreshold swing characteristics. By using the Schottky contact characteristics of a metal–semiconductor contact with different work functions to form a PN junction, the need to control doping profiles or random doping fluctuations is avoided. Furthermore, as ion implantation is not required, issues related to subsequent annealing are also eliminated, greatly reducing thermal budget. Due to the different material bandgap characteristics selected for the source and drain regions, the probability of overlap of the energy bands in the source region in the ON-state is increased and that in the drain region in the OFF-state is reduced. Based on the feasibility of the actual fabrication process and through rigorous 2D simulation studies, improvements in subthreshold swing and high on/off current ratio can be achieved simultaneously based on the proposed device structure. Additionally, the presence of the control gate structure effectively suppresses leakage current, further enhancing its potential for low-power-consumption applications.

This paper proposes symmetrical and crossed double-sided passivation emitter and surface field solar cells for bifacial applications which are fully compatible with the passivated emitter and rear contact (PERC) fabrication process. Our simulations use Silvaco TCAD Atlas, calibrated by real measurements. At an ideal albedo level where light enters both sides equally, these symmetrical and crossed structures boost energy by 88.78% and 106.74%, respectively. The reason for the crossed structure's better performance is that it has a surrounding electric field. The crossed structure also obtains a 40.18 mA/cm2 short-circuit current (Jsc), a 0.67 V open-circuit voltage (Voc), an 81.07% fill factor and a 21.93% conversion efficiency (η). Compared with PERC+, the crossed structure improves low bifaciality factor (φη) and increases η by 6.44% and energy boost by 31.41% for bifacial. For more-realistic albedo levels, the structure also performs strongly. At the spectral albedo level of snow, the energy boost of the crossed structure is 102.06%, which is close to the performance at ideal albedo. At the spectral albedo level of white sand, the energy boost is 77.13%. At lower albedos, the energy boost remains between 20% and 30%.

In this paper, we propose a novel structure of doping-less 1T-DRAM with raised body and Schottky contact to source/drain regions which uses thermionic emission to generate electrons and holes. As the device is free from physical doping, the problems associated with random dopant fluctuations will be eliminated in the proposed doping-less topology. Our simulation results show that a programming window of 28.7 μA/μm at a gate length of 10 nm with the retention time of 466 ms at 27 °C and 79 ms at 85 °C can be achieved with the proposed doping-less 1T-DRAM, which is much better than a conventional charge-plasma based doping-less 1T DRAM.

We experimentally demonstrate a new type of silicon-based capacitorless one-transistor dynamic random access memory (1T-DRAM) with an electron-bridge channel. The fabrication steps are fully compatible with modern CMOS technology. An underlap device structure is exploited and positive charges are primarily stored in drain-side and source-side p-type pseudo-neutral regions under the oxide spacer. These regions are isolated by the gate/drain or gate/source depletion regions during programming and read “1” operations which facilitates the device to achieve a 4-second-long retention time at room temperature. The carrier mobility of the electron-bridge 1T-DRAM also exhibits reduced dependence on temperature, thereby the programming window remains viable at high temperatures, while also maintaining 26% of the retention performance at 358 K. The benefits of the planar cell enable the realization of a scalable vertical channel structure.

The electrical conduction mechanisms of Ni-Cr thin film resistor are demonstrated by different film thickness through scattering models fitting. The resistivity and temperature coefficient of the resistance of Ni-Cr thin film are measured to investigate the influence of thickness with different annealing temperature. Finally, an oxidation and atom inter-diffusion model was proposed to explain the effects of film thickness on the electrical properties of Ni-Cr thin film resistor under different annealing temperature.

We demonstrate improved device performance by applying oxide sidewall spacer technology to a block-oxide-enclosed Si body to create a fully depleted silicon-on-insulator (FDSOI) nMOSFET, which overcomes the need for a uniform ultrathin silicon film. The presence of block-oxide along the sidewalls of the Si body significantly reduces the influence of drain bias over the channel. The proposed FDSOI structure therefore outperforms conventional FDSOI with regard to its drain-induced barrier lowering (DIBL), on/off current ratio, subthreshold swing, and threshold voltage rolloff. The new FDSOI structure is in fact shown to behave similarly to an ultrathin body (UTB) SOI but without the associated disadvantages and technological challenges of the ultrathin film, because a thick Si body allows for reduced sensitivity to self-heating, thereby improving thermal stability.

A high-performance polysilicon thin-film transistor (poly-Si TFT) with a trenched body is prepared and analyzed. The studies have shown that the TFT with multitrenched body has better current-voltage characteristics than the TFT with dual-trenched body.

Self-assigned II-shaped source/drain ultrathin silicon-on-insulator (UTSOI) field-effect transistor (FET) is proposed for reducing the self-heating effects in the SOI-based devices. Findings reveal significant improvement in device reliability.

An original blocking technology for improving the short-channel characteristics of polycrystalline silicon thin-film transistors (poly-Si TFTs) is presented. A significant reduction is observed in short-channel effects and thermal instability of poly-Si TFTs due to the proposed technology.

The influence of block oxide width variations on a newly designed 40-nm gate-length silicon-on-partial-insulator field-effect transistor with block oxide (bSPIFET) is examined. Results suggest the observation of good ultrashort-channel effects (USCEs) control and a high-drive current in bSPIFET.

In this work, we report on the impact of position, bias, and workfunction of back gate on retention time of Tunnel Field Effect Transistor (TFET) based dynamic memory in ultra thin buried oxide and Double Gate (DG) transistors. The front gate of the TFET is aligned at a partial portion of the semiconductor film and controls the read mechanism based on band-to-band tunneling. The back gate is engineered to improve the performance of the dynamic cell by positioning it at the region uncovered by the front gate where it forms a deep potential well. The physical well formed by the back gate misalignment is made more profound by using a p+ poly workfunction as it accumulates more holes in the storage region and forms a deep potential well that sustains holes for longer duration, thereby increasing the retention time. The retention time is also governed by the generation and recombination phenomenon which can be controlled through the applied bias at the back gate. The retention time attained is ~2 s at a temperature of 85 °C through optimal back gate engineering in DG transistors. The work shows innovative viewpoints of transforming gate misalignment, traditionally considered detrimental into a unique opportunity, coupled with appropriate selection of back gate workfunction and bias to significantly improve the retention time of capacitorless dynamic memory. [ABSTRACT FROM AUTHOR]

A nonclassical poly-Si thin-film transistor (poly-Si TFT) with a [pi]-shaped active region is described for improving device reliability. The analysis has shown that the reliability of a [pi]-TFT can be improved as the gate length is scaled down.

This paper demonstrates the use of doublegate accumulation mode (AM) and junctionless (JL) transistors for dynamic memory applications at 85 °C. The doping dependent assessments of AM and JL devices include an analysis of storage volume, carrier lifetime, and depth of potential well to determine characteristics of Dynamic Random Access Memory (DRAM). This paper shows significant impact of carrier lifetime for channel doping (Nd) ≤ 1018 cm-3 on Retention Time (RT), while the depth of potential well is more critical at higher doping (>1018 cm-3). RT of ~2.5 s at 85 °C and ~4.5 s at 27 °C is achieved for gate length (Lg) of 400 nm with Nd = 1017 cm-3 which reduces to ~90ms at 85 °C for Lg = 25 nm. This paper discusses the storage volume (Lg x film thickness for a fixed volume with width of 1 µm) optimization to attain maximum retention. Insights and guidelines, as a function of doping and device dimensions, are outlined for dynamic memory applications. [ABSTRACT FROM AUTHOR]

In this paper, we propose a recessed-gate tunneling field-effect transistor (TFET) to improve the on current of TFETs by increasing the tunnel area with line tunneling. We investigate the effects of the recessed-body thickness and the doping level on the device performance. For optimal device structures, our proposedn-TFET reaches 1.44 x 10-6 A/µm of on current and 3.22 x 109 ON/OFF current ratio. A minimum subthreshold swing SSmin = 28.3 mV/dec and an average swing SSavg = 59.8 mV/dec over seven orders of drain current are achieved. In addition, complementary TFET inverters showgood noisemargins of NMH = 65 mV (38.5 % VDD) and NML = 77 mV (32.5 % VDD) and also a high voltage gain even at VDD = 0.2 V. [ABSTRACT FROM AUTHOR]

In this paper, we propose a vertical transistor with n-bridge and body on gate (BOG-DRAM) for Low-power 1T-DRAM application. The vertical channel of the device can reduce the short-channel effect and improve scalability. The storage region stacked on the gate leads to the efficient utilization of storage space. The device with junctionless channel layers on three sides can improve writing time. The conventional current bridge device only has one side gatecontrol depletion region, but the proposed BOG-DRAM has triple-side gate-control depletion region which can improve programming window at shorter gate lengths. BOG-DRAM achieves programming window of 33.6 μA/μm when the storage length is 20 nm. In addition, the work function offset is exploited for low-power application. [ABSTRACT FROM AUTHOR]