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This paper introduces novel driving methods of the pull-down unit in a gate driver circuit for enhancement- and depletion-mode a-IGZO thin-film transistors (TFTs). The proposed gate driver circuit can achieve uniform output characteristics and effectively reduce the VOUT ripple voltage because the threshold voltage (VTH) of the pull-down units is compensated regardless of the a-IGZO TFT operation characteristics (enhancement mode: positive value of VTH, depletion mode: negative value of VTH). Many groups proposed the VTH compensation method for pull-down TFTs in the gate driver circuit using a diode connection structure. However, the diode connection structure to extract the VTH value cannot be applied in the depletion-mode oxide TFTs because TFT enters the turn-on state even when the VGS value is 0 V. To solve this problem, we adopted the VTH extraction period only once in one frame time. As a result, our circuit can compensate for VTH of the pull-down unit in the enhancement mode and can be normally operated in the depletion mode. Adjunctively, two low signals (VGL1 and VGL2) and QC node were designed to prevent the leakage current path for Q and VOUT nodes. To verify the threshold voltage tolerance for various stress conditions, we demonstrated the reliability of the circuit according to the threshold voltage change of the TFTs. The simulation result shows that all the VOUT waveforms are maintained at +28 V (VGH) under the VTH shift conditions from -7 V to +11 V; further, the rising time and falling time are less than 0.62 μs and 0.96 μs, respectively. Based on a 120Hz ultra-high definition (UHD) graphics (3840×2160) display panel, the proposed circuit has uniform VOUT characteristics compared to previous VTH compensation circuit when ΔVTH changes from -3 V to +11 V. When ΔVTH changes from -4 V to -7 V, there is also no circuit malfunction, even with slight increase in the falling time and power consumption.

We fabricated ultrathin flexible thin film transistors with hydrophobic encapsulation layer by debonding process. In the debonding process, to separate the transistors from the carrier glass in deionized (DI) water, a strong hydrophobic material such as CYTOP was used for encapsulation, thus increasing their resistance to moisture. PVA was used as a release layer and the debonding process was optimized to separate the carrier glass and the transistors. It was confirmed that water penetration into the device can be suppressed effectively when the CYTOP thickness is 800 nm. In addition, the electrical characteristics remained almost constant even in the presence of water for 50 min. The total thickness after debonding process was approximately 2 μm. Waterproof experiments and debonding process were performed for a simple inverter circuit as well as a discrete device, and the operation and voltage gain of the inverter did not change when water was placed on the device or after debonding process. Finally, the flexibility was measured by transferring the device to a flexible PI substrate. Consequently, it was confirmed that degradation in the electrical properties was slightly up to a bending radius of 2.5 mm. [ABSTRACT FROM AUTHOR]

We propose a new gate driver circuit, in which the Q node can be operated as a pull-up either as a hold-down controller. The number of transistors for the QB nodes is reduced because the one QB node can be replaced by the pull-up unit of the Q node. With an additional VOUT pull-down unit designed using only two transistors and one capacitance, we can control the discharge interval of the VOUT node to 100% duty ratio. Despite the simplified circuit configuration, the VOUT characteristic is almost the same as that of a conventional circuit with an AC-driven structure using one Q node, and two or more QB nodes. Our simulation results show that the VH voltage operates at +28 V from the 1071st to 1080th VOUT and the rising/falling time is less than 1 μs. To verify the reliability of this circuit, we further confirmed the VOUT according to the change in the threshold voltage (VTH). The proposed circuit can be operated even when the VTH is shifted to +20.5 V from the initial value (VTH = +1.09 V). Further, the VOUT characteristic is not degraded although the VTH was shifted by +18.5 V for the pull-up unit (TFT’s ΔVTH except for pull-up unit: +2 V), and the rising/falling time were confirmed to be less than 3.2 μs. [ABSTRACT FROM AUTHOR]