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This letter presents an automatic power‐stage implementation and optimization methodology for fully‐integrated reconfigurable switched‐capacitor (SC) DC‐DC converters with fine‐grained voltage conversion ratios (VCRs). The proposed technique resolves the design challenge of a simultaneous realization of full capacitance utilization, optimal sub‐cell sizing ratio, and implementation complexity reduction. It is based on the proposed partitioning algorithms and attains a significant sub‐cell number reduction, particularly for finer‐grained VCR designs, saving the power‐stage area overhead. With a given set of VCRs and hardware constraints, the proposed methodology can generate a specific power‐stage partitioning solution, including the total number and sizing ratio for the power stage sub‐cells, ensuring an optimal power‐stage conduction loss property under a given on‐chip capacitance area. The proposed methodology is applicable to both linear and binary types of SC converters. Compared with the advanced works, the proposed method realizes the number of sub‐capacitors reduction over 50% under the same VCRs. Meanwhile, over 90% of the sub‐cells can be eliminated for linear‐type SC converters with a VCR range of 10:1–2:1, theoretically. [ABSTRACT FROM AUTHOR]

This letter presents two transient enhancement techniques for multi‐path switched‐capacitor‐inductor (MP‐SCI) hybrid DC–DC converters to eliminate the line‐transient‐induced voltage coupling to the converter output. Since the existing input‐feedforward method is hard to apply to the MP‐SCI converter, the proposed techniques tackle the intrinsic hard‐charging property with the MP‐SCI topology, preventing the line‐coupling current through topology operation reconfiguration and power‐switch modulation. The proposed controller also achieves adaptive line‐transition detection and automatic flying‐capacitor voltage balancing, ensuring a fast line regulation feature. Implemented with an MP‐SCI topology for a 9 to 14 V‐input to 5 V‐output conversion, the proposed control techniques provide an output (VOUT) overshoot and undershoot as low as 0.5% of the output DC level under a 3‐V input voltage step. From the simulation, the corresponding output variation reduction can be more than 94% when compared with the existing MP‐SCI operations. Besides, the proposed controller is compatible with a voltage‐mode (VM) V2 pulse‐width modulation (PWM) function, achieving a fast load‐transient recovery in six switching cycles and a VOUT variation of 75 mV at a 5 V DC level under a 0‐to‐3 A load step. The peak conversion efficiency can be as high as 95.5%, and the targeted load current delivery is up to 3 A. [ABSTRACT FROM AUTHOR]

This article presents a BJT-based CMOS temperature sensor with a wide sensing range from −50 °C to 180 °C. To effectively relax the sensor resolution requirement and conversion time over the entire temperature range to improve energy efficiency, we introduce a nonlinear subranging readout scheme together with double sampling to achieve dynamic reconfiguration of the sensor readout according to the ambient temperature. We further reduce the sensor power at high temperature by devoting the $\beta $ -cancellation circuit only for BJT biasing while applying a temperature-independent bias current for the other sensor building blocks. Implemented in 0.18- $\mu \text{m}$ CMOS with four-wire connections and switch-leakage compensation based on small BJTs, the proposed sensor chip prototype achieves a high resolution-FoM of 7.2 pJ $\cdot \text{K}^{{2}}$ at 150 °C, while featuring a small sensing error of ±0.45 °C under a 1.5-V supply. [ABSTRACT FROM AUTHOR]

This brief presents a fully integrated low-power, low noise bandgap reference (BGR) with load driving capability. With the BGR core resistors functioning as the feedback network of the current sourcing power transistor, the proposed BGR saves chip area, reduces noise while supporting current load driving. The circuit is implemented in two different processes for performance comparison, namely the $0.18\mathbf {\mathrm {\mu }}\text{m}$ RF CMOS and the BCD mixed-signal CMOS processes. Measurement results from chip samples of the two processes show similar performances, with an average temperature coefficient (TC) of 27.1ppm/°C over $\mathbf {-} 40\mathbf {\mathrm {\sim }} 125\mathbf {^{\circ} }\text{C}$ at a 1.8-V supply. The corresponding measured coefficient of variation ($\mathbf {\mathrm {\sigma }}/\mathbf {\mathrm {\mu }}$) is around 0.3%, and the load driving capability can be up to $800\mathbf {\mathrm {\mu }}\text{A}$. By reusing the feedback resistors, the chip prototype achieved a low noise density of $1.92~\mathbf {\mathrm {\mu }}\text{V}/\surd $ Hz, 285nV/ $\surd $ Hz and 4nV/ $\surd $ Hz at 10 Hz, 10 kHz and 100 kHz, respectively, while consuming a quiescent current of 396nA. The measured power supply rejection (PSR) is −39dB at 5Hz and −45dB at 1MHz. The influence of load current on PSR has also been analyzed and verified. [ABSTRACT FROM AUTHOR]

This article presents an arithmetic progression (AP) switched-capacitor (SC) dc–dc converter topology for systematic step-down reconfigurable rational voltage conversion ratio (VCR) generation while exhibiting soft VCR transitions and quasi-symmetric two-phase charge delivery. The proposed AP topology features fixed steady-state voltage in all the flying capacitors ($C_{\mathrm {FLY}}$) irrespective of VCR change, essentially eliminating the internal $C_{\mathrm {FLY}}$ hard-charging loss due to voltage rebalancing, effectively improving the overall dynamic efficiency. It also achieves optimal steady-state slow-/fast-switching loss. Furthermore, due to the inherent quasi-symmetric output charge ($Q_{\mathrm {OUT}}$) delivery property in the two-phase switching operations, the proposed topology alleviates the VCR-dependent imbalanced per-phase $Q_{\mathrm {OUT}}$ delivery to relax the $C_{\mathrm {OUT}}$ requirement in a single-branch converter implementation. We propose a cross-coupled bootstrapping driver (XCBD) operated at half of the converter switching frequency ($f_{\mathrm {SW}}$) to adaptively control the flying power switches without relying on dual-branch interleaved architecture. Fabricated in 65-nm CMOS, the implemented AP chip prototype achieves a step-down VCR of 5:4/3/2/1 and converts a 1.5-V input to a 0.18–1.19-V output. With a measured steady-state peak power conversion efficiency (PCE) of 93.7%, this work can deliver a maximum output current of 400 mA while attaining an average conversion efficiency of up to 89% under a periodic VCR transition at 100 kHz as benefitted from the intrinsic soft VCR transition and low conduction loss properties. [ABSTRACT FROM AUTHOR]

This work presents a ${128}\times {128}$ multi-function CMOS vision sensor with motion direction detection (MDD) and simultaneous energy harvesting (EH) capability, featuring: 1) light weight template-based optical flow (OF) algorithm for on-chip MDD with high energy efficiency and small area overhead; and 2) independent imaging and energy harvesting (EH) operations using vertically stacked N+/PW and PW/DNW+DNW/PSUB junctions without photodiode reconfiguration. Fabricated in $0.18\mu \text{m}$ standard CMOS, this work demonstrates the first CMOS vision sensor featuring both MDD and EH modes within a compact pixel pitch of $4.75\mu \text{m}$. With a power consumption of $10.5\mu \text{W}$ at 15fps in MDD mode, the chip prototype achieves a motion sensing figure-of-merit (MS-FoM) of 171 pJ/pixel $\cdot $ frame, which is 30% better than the state-of-the-art MDD sensors. The proposed EH configuration achieves continuous power generation at 267pW/lx/mm2 irrespective of the imaging/MDD operation, demonstrating a $1.56\times $ improvement over prior arts. [ABSTRACT FROM AUTHOR]

This tutorial brief reviews highly-integrated switched-capacitor (SC) DC-DC converter topologies for miniaturized energy harvesting (EH) IoT systems. Aiming to provide a concise overview of SC converter-based EH interfaces, we first discuss the system level design considerations for energy balancing between source, storage, and load under different environmental conditions. The key factors dominating the energy extraction and power conversion efficiencies, including the source adaptation strategies and SC power stage intrinsic losses, are outlined to establish a fundamental understanding on the EH system performance. After studying different state-of-the-art SC topologies in terms of their rational boost voltage conversion ratio (VCR) generation flexibility, loss characteristics, and implementation tradeoffs, we further introduce two advanced SC converter-based EH system examples, highlighting the SC converter operation in enhancing the EH system functionality and performance. The pros and cons of different SC converter topologies for EH systems will also be discussed. [ABSTRACT FROM AUTHOR]

Single-nucleotide polymorphism (SNP) plays a critical role in personalized medicine, forensics, pharmacogenetics, and disease diagnostics. Among different existing SNP genotyping techniques, melting curve analysis (MCA) becomes increasingly popular due to its high accuracy and straightforward procedures in extracting the melting temperature (Tm). Yet, its study on existing digital microfluidic (DMF) platforms has intrinsic limitations due to the temperature inhomogeneity within a thickened droplet during the on-chip rapid heating process. Although the utilization of an on-chip thermostat can regulate and monitor the dynamic melting process in real time, the limited Tm accuracy resulting from the insufficient system response time to accommodate the fast-melting evolution still poses a great challenge for precise MCA with high throughput. This work proposes a one-shot MCA on a DMF platform. The tailoring of a functional substrate with hierarchical micro/nano structure enables high-resolution patterning of pL-scale droplets. Specifically, the hydrothermal and photocatalysis treatment allows the functional substrate to exhibit a superwettability contrast of >170°, facilitating passive isolation of the pL-scale DNA sample into highly-resolved pL droplets above the 200 μm superhydrophilic patterns. This high-resolution MCA technique can successfully discriminate KRAS gene targets with single-nucleotide mutations in 3 seconds. The high accuracy and consistency in the acquired Tm when compared with off-chip results demonstrate its opportunities for near-patient diagnostics, precision medicines, genetic counseling, and prevention strategies on DMF platforms. [ABSTRACT FROM AUTHOR]

This Special Issue of the IEEE Journal of Solid-State Circuits is dedicated to a collection of the best papers selected from the 2021 IEEE International Solid-State Circuits Conference (ISSCC) that took place on February 13-22, 2021, virtually. This issue covers papers from the Analog, Power Management, Data Converters, RF, and Wireless committees. [ABSTRACT FROM AUTHOR]

This brief describes a fully integrated 10-V pulse driver. It comprises a four-stage switched-capacitor voltage multiplier (SCVM) and a dedicated high-voltage output driver (HVOD) with multiband pulse-frequency modulation (MPFM) to generate efficiently 10 V regulated output pulses. Specifically, an analog/digital hybrid-controlled current-starved ring oscillator (HCRO) modulates the switching frequencies at distinct bands to regulate the high-voltage (HV) supply for the HVOD, while enabling fast output transitions with an improved driving efficiency. Prototyped in 65-nm bulk CMOS, the driver demonstrates 10-V pulse generations over a 0.1-to-1-MHz range for a 15 pF//50 kΩ load. With the proposed MPFM, this work measures an overall driving efficiency of up to 19.9%, corresponding to a ~1.6 × improvement over prior arts. The measured output rise time of 119 ns is also ~25% faster when compared with using the conventional pulse-frequency modulation (PFM) scheme. [ABSTRACT FROM AUTHOR]

SUMMARY: The Internet of Everything (IoE), clearly a 21st century's technology, brilliantly plays with digital data obtained from analog sources, bringing together two different realities, the analog (physical/real), and the digital (cyber/virtual) worlds. Then, with the boundaries of IoE still analog in nature, the required functions at the interface involve sensing, measuring, filtering, converting, processing, and connecting, which imply that the analog layer governs the entire system in terms of accuracy and precision. Furthermore, such interface integrates several analog and mixed‐signal subsystems that comprise mainly signal transmission and reception, frequency generation, energy harvesting, data, and power conversion. This paper sets forth a state‐of‐the‐art design perspective of some of the most critical building blocks used in the analog/digital interface, covering wireless cellular transceivers, millimeter‐wave frequency generators, energy harvesting interfaces, plus, data and power converters, that exhibit high quality performance achieved through low‐power consumption, high energy‐efficiency, and high speed. [ABSTRACT FROM AUTHOR]

This article proposes a split-phase flipping-capacitor rectifier (SPFCR) to resolve the hard tradeoff between the number of capacitors and the energy-extraction efficiency for capacitive piezoelectric energy-harvesting (PEH) interfaces. By splitting the capacitor usage into multiple phases, this article can achieve the most number of flipping phases using the same number of capacitors when compared with the state of the art. We also relaxed the implementation complexity by removing insignificant SFPCR flipping phases without sacrificing the energy-harvesting efficiency. To improve further the input power adaptation, the flipping capacitors are reconfigured as a multiple-voltage-conversion-ratio (MVCR) switched-capacitor dc–dc converter during the non-flipping period without using extra passives. Maximum-power-point tracking (MPPT) is also accomplished using the full-bridge rectifier (FBR) fractional open-circuit voltage ($V_{{\text {OC}, \text {FBR}}}$) to relax the voltage-tolerance requirements. Fabricated in 0.18- $\mu \text{m}$ CMOS, the proposed 21-phase SPFCR PEH interface demonstrates a measured maximum output power improving rate (MOPIR) of up to 9.3 $\times $ with $V_{D}= 0.12$ V (6.5 $\times $ with $V_{D}= 0$ V) when compared with the conventional FBR interface over an equivalent FBR input power range ($P_{{\text {in, FBR}}}$) from 0.15 to 5.57 $\mu \text{W}$. [ABSTRACT FROM AUTHOR]

This article presents a low-power multi-mode CMOS vision sensor with mixed-signal in-sensor computation capabilities targeting the next-generation wireless sensing applications. To support the always-on and scene-adaptive edge computing scenarios with low power and low bandwidth, the sensor is reconfigurable for three operation modes, namely: 1) motion sensing (MS); 2) object segmentation (OS); and 3) full imaging (FIM). A mixed-signal cooperative scheme of frame differencing (FD) and background subtraction (BS) is proposed to achieve high-accuracy MS with varying object sizes and speeds. The mixed-signal BS-based OS can minimize both object localizing and imaging efforts for object analysis upon motion triggering, while FIM enables complete scene recording for the identified object of interest. The complete CMOS vision sensor is implemented through reconfigurable and fully dynamic mixed-signal processing at both pixel and column levels cooperatively to achieve low power and compact area. Fabricated in a 0.18- ${ {\mu }}\text{m}$ CMOS, the 256 $ {\times }$ 216 chip prototype achieves the cooperative MS with only 2.36 ${\mu }\text{W}$ at 15 frames/s, when composed of 14 FD frames (147 nJ/frame) and 1 BS frame (302 nJ/frame). The OS mode consumes 1.44~2.04 $ {\mu }\text{J}$ /frame at 0%~100% object occupancy, linearly corresponding to 41%~16% power saving when compared with the conventional digital OS. The FIM mode operates with only 1.41 ${\mu }\text{J}$ /frame for complete scene recording. The achieved energy efficiencies for all operation modes compare favorably with the state of the art. [ABSTRACT FROM AUTHOR]

This paper presents an ultra-high-frequency (UHF) passive sense tag for electrical grid and substation thermal monitoring, with emphasis on the tag system optimization and the design of a low power embedded temperature sensor. The designed tag achieves a sensitivity of $-$ 12.3 dBm under active temperature monitoring operation, which is the state of the art among existing UHF passive temperature sense tag products. The sensing inaccuracy of the tag is $\pm$ 2.5 $^{\circ }$ C (3 $\sigma$) from $-$ 25 to 120 $^{\circ }$ C after a low-cost wireless single-point trim. An antimetal ceramic-packaged tag was tested by attaching to a ring main unit in the substation and complete tag system demonstrated robust wireless operation with a sensing distance of 3.5 m. The combination of batteryless and wireless operation, high sensitivity, wide sensing range, and small incident-power-dependent error ($\pm$ 0.2 $^{\circ }$ C) makes this tag suitable for the target applications. [ABSTRACT FROM AUTHOR]

This article presents an algebraic series–parallel (ASP) topology for fully integrated switched-capacitor (SC) dc–dc boost converters with flexible fractional voltage conversion ratios (VCRs). By elaborating the output voltage (${V} _{\textrm {OUT}}$) expression into a specific algebraic form, the proposed ASP can achieve improvements on both the charge sharing and bottom-plate-parasitic losses while maintaining the high topology and fractional VCR flexibility of conventional two-dimensional series–parallel (2DSP) converters. The proposed method consists of a generic ASP topology framework with systematic parameter determination for a precise converter implementation, and can theoretically surpass the power-conversion efficiency (PCE) of 2DSP converters. Fabricated in 65-nm bulk CMOS, we designed a fully integrated ASP-based SC rational boost converter by cascading with the Dickson topology, with a total of seven rational VCRs to boost an input voltage of 0.25–1 V to a 1-V output. Delivering a maximum loading power of 20.4 mW, the chip prototype achieves a peak efficiency of 80% at a power density of 22.7 mW/mm2. [ABSTRACT FROM AUTHOR]

This brief presents the design methodology of an integrated KY dc–dc step-up converter with constant on-time (COT) control under discontinuous conduction mode (DCM) operation. The method improves the efficiency during the deep-light-load situation, and we analyze the design criteria of the flying capacitor as well as the COT controller of the KY converter under DCM. The simulation results verify that the design obtains higher conversion efficiency than the pulse width modulation controlled KY converter. The KY converter with COT control has been fabricated in 65-nm CMOS with a core area of 0.55 $\times $ 0.55 mm2. The circuit uses an off-chip inductor of 12 nH and an output capacitor of 4 nF. The converter operates with a current load ranging from 500 $\mu \text{A}$ to 10 mA with an output voltage ripple lower than 70 mV in the deep-light-load range. [ABSTRACT FROM AUTHOR]

This brief presents a high efficiency fully integrated high-voltage (HV) pulse driver in standard CMOS. Powered by a standard I/O DC voltage of 2.5 V, the proposed system employs an optimized 4-stage cross-coupled switched-capacitor voltage multiplier (SCVM) together with an on-chip HV output driver to generate HV pulses of >10 V. We propose an area-efficient HV output driver stage to reach up to 12% total active area reduction when compared with the conventional implementation while maintaining the low static power characteristics. We also present a synchronous charge compensation (SQC) technique to alleviate the loading-dependent signal distortion through reducing the HV rail voltage droop and improving the HV pulse settling time during the driver output transitions. Fabricated in 65-nm bulk CMOS, the chip prototype can successfully generate HV pulses from 250 kHz to 1 MHz with a 15 pF load while ensuring no device breakdown. Measurement results demonstrate a peak SCVM power conversion efficiency (PCE) of 50% and an overall driving efficiency of 12.25%. The chip prototype attains a $\sim 2\times $ faster output pulse transition speed compared with the state-of-the-art. [ABSTRACT FROM AUTHOR]

We propose an algorithmic voltage-feed-in (AVFI) topology capable of systematic generation of any arbitrary buck–boost rational ratio with optimal conduction loss while achieving reduced topology-level parasitic loss among the state-of-the-art works. By disengaging the existing topology-level restrictions, we develop a cell-level implementation using the extracted Dickson cell (DSC) and charge-path-folding cell (QFC) to minimize the power-stage parasitic loss, exhibiting a Dickson-like switching pattern. The proposed partitionable main cell (MC) and auxiliary cell (AC) architecture achieves fined-grained voltage conversion ratio (FVCR) reconfiguration with optimal power cell utilization and reduced control complexity. Implemented in 65-nm bulk CMOS, the fully integrated switched-capacitor power converter (SCPC) using 10 MCs and 10 ACs executes a total of 24 VCRs (11 buck and 13 boost) with wide-range efficient buck–boost operations through the proposed reference-selective bootstrapping driver (RSBD). Based on the AVFI topology, the chip prototype reaches a measured peak efficiency of 84.1% at a power density of 13.4 mW/mm2 over a wide range of input (0.22–2.4 V) and output (0.85–1.2 V). [ABSTRACT FROM AUTHOR]

This brief presents a low-power compression-based CMOS image sensor for wireless vision applications. The sensor implements low-bit-depth imaging with planned sensor distortion (PSD) to effectively compress both data bandwidth and processing power while maintaining high reconstruction image quality. Accordingly, a column-parallel microshift-guided successive-approximation-register (SAR) ADC is proposed to enable 3-bit PSD imaging based on a ${3\times 3}$ pattern. To support normal imaging with low area overhead, the circuit is reconfigurable as an 8-bit SAR/single-slope ADC. The data bandwidth is further compressed by a customized lossless encoder based on predictive coding and run length coding. A ${256\times 216}$ prototype imaging system composed of the compression-based image sensor and the lossless encoder is fabricated in a 0.18- ${\mu }\text{m}$ standard CMOS process. Measurement results show that the image sensor achieves 3 bit/pixel (bpp) with 34.9-dB reconstruction peak signal-to-noise ratio (PSNR) and 0.91 structural similarity index (SSIM). With 1/4 spatial downsampling and lossless encoding, 0.31 bpp is obtained with 29.2-dB PSNR and 0.83 SSIM. The sensor consumes $14.8~{\mu }\text{W}$ (full resolution) and $4.3~{\mu }\text{W}$ (downsampling) at 15 fps, achieving state-of-the-art FoMs of 17.8 and 5.2 pJ/pixel $\cdot $ frame, respectively. Including the encoder, the overall system dissipates as low as $1.2~{\mu }\text{J}$ /frame, making it an attractive solution for wireless sensor networks. [ABSTRACT FROM AUTHOR]

This paper reports a regulation-free sub-0.5-V crystal oscillator (XO). The XO specifically designed for Bluetooth low-energy (BLE) radios aims for direct-powering by the harvested energy. To secure its performance against process, voltage, and temperature (PVT) variations, while reducing its startup time and energy, we propose a dual-mode $g_{m}$ scheme and a scalable self-reference chirp injection (SSCI) technique. The former employs an inductive multistage $g_{m}$ to mitigate the crystal’s stray capacitance during the startup, but a single-stage $g_{m}$ in the steady state to preserve the phase noise (PN). For the latter (SSCI), we generate a scalable chirping sequence to kick-start the XO, avoiding trimming of the auxiliary oscillator. The XO fabricated in 65-nm CMOS is measured with two common crystals (16/24 MHz) over a 0.3-to-0.5-V supply. At 24 MHz and 0.35 V, the startup time and energy of the XO are 400 $\mu \text{s}$ and 14.2 nJ, respectively, while showing a steady-state power of 31.8 $\mu \text{W}$ and a PN of −134 dBc/Hz at 1-kHz offset. The frequency stability is 14.1 ppm against temperature (−40 °C–90 °C) and 17.9 ppm against voltage (0.3–0.5 V), both conform to the BLE standard (±50 ppm) with adequate margin. [ABSTRACT FROM AUTHOR]

This brief reports a small size single-photon avalanche diode (SPAD) in baseline 65-nm CMOS suitable for low-cost time-of-flight application with high spatial resolution. By exploiting the less-doped n-well region to surround the vertical p-well/deep-n-well multiplication region, the electric field at the SPAD periphery can be reduced without process modifications while avoiding premature lateral breakdown. Validated using TCAD simulations, the fabricated 4-μm diameter SPAD device exhibits a compact device size with a low dark count (73 cps/μm2 at 20 °C) and a high fill factor (17.7%) using 65-nm baseline CMOS, while demonstrating competitive performance when compared with the state of the art. [ABSTRACT FROM AUTHOR]

This brief presents a 0.9- $\mu \text{W}$ duty-cycle-modulated temperature sensor with a sub- $\mu \text{A}$ peak current for energy harvester- or micro-battery-powered systems. A compact sensing frontend is proposed to achieve low power, together with various device-level leakage and nonlinearity compensation techniques adopted to minimize the sensor error. In addition, a current-starved multivibrator which provides inherent clamping voltages is used for duty cycle modulation for overall energy savings. The sensor designed in 0.18- $\mu \text{m}$ CMOS process achieves a resolution figure of merit of 10.6 pJ $\cdot \text{K}^{2}$ , which is among the most energy-efficient designs to date. Trimmed at 30 °C, the sensor achieves ±0.85 °C precision from −30 °C to 120 °C. The maximum supply sensitivity is 0.7 °C/V for a 1.6–2 V supply. [ABSTRACT FROM AUTHOR]

This paper presents a nano-watt class energy-efficient capacitive sensor interface with on-chip temperature compensation. To achieve both high resolution and sensing accuracies, we exploit the fundamental limits of a two-step incremental-ADC and present a systematic study on the optimal coarse/fine bit allocations in the presence of mismatch errors. Efficient hardware reuse is ensured by utilizing the same loop filter, capacitive DAC, and digital controller in coarse/fine conversions for both capacitance and temperature readouts. A reconfigurable pre-gain stage for both capacitance and temperature sensing and a block-based data weighted averaging scheme are also employed to improve the overall system efficiency with 60% control overhead reduction. Optimized biasing circuit and subthreshold-biased amplifier with indirect compensation are utilized to achieve high accuracy with nano-watt power. Fabricated in a standard 0.18- \mu \textm CMOS process, the chip prototype consumes only 570 nW and achieves measured capacitance and temperature sensing inaccuracies of ±0.17 fF ( $1\sigma$ ) from 0 to 10.8 pF and ±0.18 °C ( $3\sigma$ ) from 0 to 100 °C, respectively. System level verification with a commercial MEMS pressure sensor shows a measured pressure sensing error improvement of > $150\times$ after temperature compensation. [ABSTRACT FROM PUBLISHER]

This paper presents a fully integrated piezoelectric energy harvesting interface without external components. Instead of relying on bulky external inductors with high quality factor as in the conventional parallel-synchronized-switch harvesting-on-inductor (P-SSHI) approach, we propose a flipping-capacitor rectifier (FCR) topology to achieve voltage inversion of the piezoelectric energy harvester through a reconfigurable capacitor array. This fundamentally preserves a fully integrated solution without inductors while achieving a high-energy extraction capability. Measurement results from FCR1 using discrete components shows an output power enhancement of up to 3.4 \times , which is close to the theoretical prediction. We also fabricated a seven-phase FCR3 with four MIM capacitors and 21 switches using a 0.18- \mu \text{m} 1.8/3.3/6 V CMOS process, occupying an active area of ~1.7 mm2. Additionally, we implemented an active rectifier based on a common-gate comparator with phase alignment to ensure high-speed operation while minimizing the diode voltage drop. A phase generate-and-combine circuit eliminates redundant switching activities. Systematic optimization of the three main energy loss mechanisms during the finite flip time: 1) phase offset; 2) incomplete charge transfer; and 3) reduced conduction time, is also introduced. Measurement results show that the output power enhancement can reach up to 4.83 \times $ at an excitation frequency of 110 kHz. [ABSTRACT FROM AUTHOR]

This paper presents a real-time electrocardiogram (ECG) data compression processor with improved energy efficiency while maintaining high accuracy and real-time operation. Wavelet shrinkage is exploited to filter the noise and achieve sparse ECG signal representation. Adaptive temporal decimation is proposed to achieve configurable processing to adaptively reduce the data amount and computational activities for further power reduction. Modified Huffman and run-length wavelet source coding (MHRLC) is also designed to represent wavelet coefficients with optimized average code length and reduced memory requirement. Fabricated in 0.18- \mu \textm CMOS, the ECG processor is implemented with customized near-threshold digital logics for minimum energy operation. The prototype was fully validated with the MIT-BIH Arrhythmia database. With a power consumption of 147–375 nW at 0.45 V, the proposed ECG processor exhibits a wide compression ratio ranging from 2.89 to 26.91, corresponding to a percentage-RMS-distortion from 0% to 3.11%. [ABSTRACT FROM PUBLISHER]

This brief presents a dual-path CMOS rectifier with adaptive control for ultrahigh-frequency (UHF) RF energy harvesters. The input power range with high power conversion efficiency (high PCE) of the rectifier is extended by the proposed architecture, which includes a low-power path and a high-power path. The dual-path rectifier with an adaptive control circuit is fabricated in a 65-nm CMOS process. Operating at 900 MHz and driving a 147- \textk\Omega load resistor, the measured PCE of this work can be maintained above 20% with an 11-dB input range from −16 to −5 dBm, while only an 8-dB input range can be achieved with traditional single-path rectifiers. A sensitivity of −17.7 dBm is measured with 1-V output voltage across a capacitive load. [ABSTRACT FROM PUBLISHER]

In this paper, an ultra-compact single-chip solar energy harvesting IC using on-chip solar cell for biomedical implant applications is presented. By employing an on-chip charge pump with parallel connected photodiodes, a 3.5 \times efficiency improvement can be achieved when compared with the conventional stacked photodiode approach to boost the harvested voltage while preserving a single-chip solution. A photodiode-assisted dual startup circuit (PDSC) is also proposed to improve the area efficiency and increase the startup speed by 77%. By employing an auxiliary charge pump (AQP) using zero threshold voltage (ZVT) devices in parallel with the main charge pump, a low startup voltage of 0.25 V is obtained while minimizing the reversion loss. A 4\, {\mathbf{V}}_{\mathbf{in}} gate drive voltage is utilized to reduce the conduction loss. Systematic charge pump and solar cell area optimization is also introduced to improve the energy harvesting efficiency. The proposed system is implemented in a standard 0.18- \mu\text{m} CMOS technology and occupies an active area of 1.54 \textmm^2. Measurement results show that the on-chip charge pump can achieve a maximum efficiency of 67%. With an incident power of 1.22 \textmW/cm^2 from a halogen light source, the proposed energy harvesting IC can deliver an output power of 1.65 \mu\textW at 64% charge pump efficiency. The chip prototype is also verified using in-vitro experiment. [ABSTRACT FROM PUBLISHER]

We report a micro-nuclear magnetic resonance (NMR) system compatible with multi-type biological/chemical lab-on-a-chip assays. Unified in a handheld scale (dimension: 14 \times 6 \times 11 cm ^{3} , weight: 1.4 kg), the system is capable to detect <100 pM of Enterococcus faecalis derived DNA from a 2.5~\mu \text {L} sample. The key components are a portable magnet (0.46 T, 1.25 kg) for nucleus magnetization, a system PCB for I/O interface, an FPGA for system control, a current driver for trimming the magnetic (B) field, and a silicon chip fabricated in 0.18~\mu \text m CMOS. The latter, integrated with a current-mode vertical Hall sensor and a low-noise readout circuit, facilitates closed-loop B-field stabilization (2 mT \to 0.15 mT), which otherwise fluctuates with temperature or sample displacement. Together with a dynamic-B-field transceiver with a planar coil for micro-NMR assay and thermal control, the system demonstrates: 1) selective biological target pinpointing; 2) protein state analysis; and 3) solvent-polymer dynamics, suitable for healthcare, food and colloidal applications, respectively. Compared to a commercial NMR-assay product (Bruker mq-20), this platform greatly reduces the sample consumption ( $120\times $ ), hardware volume ( $175\times $ ), and weight ( $96\times $ ). [ABSTRACT FROM AUTHOR]

Complementary metal oxide semiconductor (CMOS) technology enables low-cost and large-scale integration of transistors and physical sensing materials on tiny chips (e.g., ＜1 cm2), seamlessly combining the two key functions of biosensors: transducing and signal processing. Recent CMOS biosensors unified different transducing mechanisms (impedance, fluorescence, and nuclear spin) and readout electronics have demonstrated competitive sensitivity for in vitro diagnosis, such as detection of DNA (down to 10 aM), protein (down to 10 fM), or bacteria/cells (single cell). Herein, we detail the recent advances in CMOS biosensors, centering on their key principles, requisites, and applications. Together, these may contribute to the advancement of our healthcare system, which should be decentralized by broadly utilizing point-of-care diagnostic tools. [ABSTRACT FROM AUTHOR]

This paper describes a 20 MHz micro-nuclear magnetic resonance ( $\mu $ NMR) transceiver (TRX) featuring a butterfly-coil input for chemical/biological assays. It enables integration with a 2D multi-electrode digital microfluidic (DMF) device inside a space-limited portable magnet (0.46 T, 1.25 kg), making multi-sample management compatible with \mu $ NMR measurements, and supporting electronic automation. The transmitter (TX) incorporates a pulse-sequence synthesizer followed by an inverter-based power amplifier (PA), to emit the exciting pulses for magnetizing the protons of the samples. For the receiver (RX), it is headed by a multi-stage low-noise amplifier (LNA) using NMOS-PMOS-complementary differential pairs, achieving a sub-nV/ \surd $ Hz input-referred noise at low power. Sixth-order Butterworth low-pass filters constitute the core of the RX I/Q baseband. Their source-follower-based topology allows fast and coherent scaling of all poles by the bias current, reducing the dead-time of the RX for better sensitivity. Fabricated in CMOS, the TRX occupies a die area of 2.1 mm2, consumes 6.6/23.7 mW of power in the TX/RX mode, and demonstrates the feasibility of electronic-automated biological (avidin) and chemical (CuSO4) assays achieving a detection limit on avidin of 0.2 pmol. [ABSTRACT FROM PUBLISHER]

A bipolar junction transistor (BJT)‐based CMOS temperature sensor exploiting the piecewise BJT process spread compensation property of the base recombination current is proposed to reduce the process variations of the base–emitter voltage (Vbe). The weighted combinations of different on‐chip resistors are explored to minimise their associated process spread. Fabricated in standard 0.18‐μm CMOS, the chip prototype occupies an active area of 0.036 mm2 and draws 3 μA from a 1.2 V supply, with a measured maximum inter‐/intra‐die variation in Vbe of <1.5 mV from −40 to 125°C from two batches. Using the measured Vbe, ΔVbe and the first‐batch‐only calibration parameters, the chip prototype demonstrates an untrimmed batch‐to‐batch inaccuracy of ± 1.5°C (3σ) within the same temperature range (24 samples from 2 batches). [ABSTRACT FROM AUTHOR]