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Grid forming (GFM) control strategy has been increasingly used in grid-connected converters to regulate system frequency and mimic the inertia of synchronous generator. However, the description of its power angle dynamics under large disturbances is still lacking up to date, which may pose great challenges to stable operation and economic configuration of grid-connected converters in the future power system. To overcome the aforementioned obstacle, a Krylov–Bogoliubov–Mitropolsky (KBM) asymptotic method with the perturbation theory is presented first in this article to derive an analytical solution for power angle trajectory under large disturbances. Considering that the antiderivative problem is usually unsolvable due to the complicated perturbation function, a tailored integral method is further proposed to address this problem and simplify the final result, which facilitates the KBM asymptotic method to the analysis and calculation of power angle trajectory. As a result, an explicit and accurate time-domain expression is obtained, and it reveals the quantitative relationships between control parameters and dynamic characteristics, which may provide a good potential for system transient stability analysis and GFM converter design. In the end, the effectiveness and accuracy of the proposed method are verified by both simulations and control-hardware-in-loop experiments. [ABSTRACT FROM AUTHOR]

The medium-voltage dc (MVDC) system are intensely investigated by both industry and academy. However, how to realize a lower power circuit directly fed by MVDC is an important but easily neglected problem, which seriously affects the reliability of the dc system. The current high step-down circuits are mostly suitable for high-power applications, while the circuits for low-power applications are designed case by case. To address the obstacle, a generalized buck-boost type high step-down converter (BHSC) structure is proposed in this article. The submodules of BHSC are derived from basic dc–dc converter. As a result, the features of high modularity, simple structure, and low cost can be obtained, and each submodule operates independently without communication and synchronization to achieve voltage balance. Furthermore, a submodule strategy with Bang-Bang control, instead of hardware modification, is proposed to overcome the limitation of BHSC generality in medium-voltage (MV) and high-voltage (HV) applications, due to the operating current difference in different submodules of the cascaded structure. Therefore, BHSC can be easily extended to MV or HV by increasing the number of submodules. Finally, an experimental evaluation of a 1 kV/80 W prototype converter is presented, which can be applied as auxiliary power supply for high-power converter. [ABSTRACT FROM AUTHOR]

Interior permanent magnet synchronous motor (IPMSM) with back electromotive-force (EMF) based sensorless field-oriented control (FOC) is widely used in medium-high speed applications. Unfortunately, the back EMF is too small to be estimated accurately during low speed operation. Hence, the current-frequency (I–f) control with controllable current vector is used for startup. However, the conventional I–f control is hard to realize the tradeoff between startup speed and load capacity, suffering high-acceleration and high-load startup failure. In this article, a current vector angle controller for sensorless IPMSM startup is proposed to adjust speed-up-stage current acceleration and constant-speed-stage current amplitude with load automatically. The proposed angle controller guarantees the current vector angle close to the maximum torque per ampere angle, which contributes to large startup torque, high operating efficiency and smooth transition from I–f startup to sensorless FOC. Furthermore, the robustness against parameters variation of angle controller is evaluated quantitatively. These theoretical advantages are verified in experiments with a 380 V, 1.5 kW IPMSM. In particular, the experimental results demonstrate that the proposed I–f control realizes full-load startup even with ${\rm{ \pm }}$ 50% flux linkage and ${\rm{ \pm }}$ 30% inductance variation. Furthermore, the startup acceleration auto-adjusts with load to reconcile startup speed and load capacity. [ABSTRACT FROM AUTHOR]

In this letter, an internal electric field shielding layer for high voltage winding of medium voltage high frequency transformer used in a modular cascaded medium voltage solid state transformer is proposed. Without breaking the litz wire insulation layer, the high electric field is effectively shielded by a semiconducting layer and an unclosed copper foil spiral, which are electrically connected together. Not only the electric field in the main wall insulation is uniformed but also the peak value of the internal field is greatly reduced, which will help to achieve lower partial discharge and higher insulation reliability. With this structure, the difficulties of pouring process and electric field estimation for the litz wire winding are both avoid. Finally, a no partial discharge 100 kW medium voltage high frequency transformer prototype with 75 kV base insulation level is built and verified with the insulation tests. [ABSTRACT FROM AUTHOR]

Switching ripple communication (SRC), which modulates the PWM carrier with digital data and takes the switching ripple as a signal carrier, helps power electronic converters to transfer digital data along with power. This article discusses the theory and implementation of SRC technology. It proves that the modulation using square wave and sinusoidal wave carriers is compatible. The fundamental principles of frequency hopping–differential phase shift keying (FH–DPSK) modulation are then analyzed in detail, and an improved FH–DPSK scheme is proposed to suppress output voltage disturbances, thereby maintaining power quality, reducing communication noise, and separating power control and data modulation. Furthermore, to evaluate the reliability of the communication technique, the effect of power conversion on communication is discussed in detail. Finally, a buck converter with a switching frequency of 100/83.3 kHz is set up, and the experiment achieves a 16.7 kbps bit rate using quaternary modulation, demonstrating the correctness of the scheme. [ABSTRACT FROM AUTHOR]

Multichip silicon carbide power modules with integrated snubbers are promising for large-capacity converters with high speed and cost efficiency. In the design stage, the parasitic inductance of module layout generally attracts the primary efforts of designers because of its severe impact on dynamic performance, e.g., voltage overshoot and transient current imbalance. However, due to the complexity of the heterogeneous layout, the solution space and development efficiency are always limited by the traditional manual design approach. Thus, this article proposes a generative method to optimize the layout autonomously. First, a graph model is built to describe heterogeneous layouts with all interconnectivity and design constraints retained. Based on the model, integer programming is introduced to generate layout templates with variable geometric topologies. Then, coupled with a self-developed discrete extractor, the Pareto-front is obtained by genetic algorithm, providing a tradeoff boundary for loop inductance and branch mismatch. The proposed method is systematic, flexible, and requires few designers’ expertise. A 1200 V/240 A half-bridge module is designed and fabricated to validate its capability. The experimental results show that the loop inductance of 5.59 nH is achieved, and less than 5% of the transient current imbalance is realized under 6.2 A/ns turn-on in the rated. [ABSTRACT FROM AUTHOR]

Following the continuous development of wide bandgap (WBG) devices and multilevel converter technology, medium voltage active front ends are becoming promising in future high-power-density and high-power applications. However, the cost issue is one of the major drawbacks, which stops the WBG devices from being widely applied in high-power areas. This article proposes a silicon carbide (SiC) and silicon (Si) hybrid five-level unidirectional rectifier. It requires only four SiC MOSFETs with relatively low blocking voltage and four Si diodes. Meanwhile, by adding snubber capacitors, all the Si devices are with low-speed switching, and the voltage stresses of fast SiC MOSFETs are minimized. In this article, operational analysis and carrier-based phase-disposition pulsewidth modulation scheme for this circuit are discussed in detail. The capacitor voltage balancing and unity power factor are both realized. Simulation and scaled-down experimental results are demonstrated to verify the proposed rectifier. Furthermore, the comparison of the hybrid five-level rectifiers is given to show the advantages of the proposed rectifier in terms of voltage stress, efficiency, and cost. [ABSTRACT FROM AUTHOR]

The stitch wire configuration is widely adopted for large-area IGBT chips. However, an inhomogeneous wire current density introduces uneven self-heating and nonuniform chip heating, which exacerbates the chip thermal stress. In this article, a multicellular electro-thermal model considering the stitch-bonding wires is derived to optimize the wire layout parameters. Furthermore, the current density alleviation of wire bonds is investigated to be the most sensitive and effective method to comprehensively mitigate the thermal nonequilibrium and local overheating. Consequently, an improved multitier layout is proposed to further achieve thermal stress suppression without any additional components and advanced materials. Finally, a triple-tier-bonded IGBT module with optimal design parameters is fabricated to validate the thermal mitigation performance. The prototype experimental results demonstrate that the modeling error is less than 3.0%. The multitier layout decreases the current density by 57.6%, hence, the maximum and average chip temperature are reduced by 21.8% and 12.4%, respectively. [ABSTRACT FROM AUTHOR]

Implementation of the series connection of the SiC MOSFETs in medium voltage (MV) high power converters faces a series of challenges, including the electrical/thermal stress imbalance, insulation coordination design, high dv/dt elimination and robustness under variable operating conditions. This paper stresses these challenges and proposes a comprehensive design of a 9.6 kV/200 A power block based on the series connection of SiC MOSFETs. The power block has been verified under the continuous operation, which demonstrates the highly efficient and reliable operation under the variable switching current condition. Afterward, performance screening in a 5 kV/1 MW inverter is conducted to assess the efficiency in MV converters. Compared with the advanced high voltage high power devices, the proposed power block demonstrates fast switching speed and low switching loss, which indicates that the series connection of SiC MOSFETs is a promising technique to expand the operation voltage/power of the SiC MOSFETs to the MV megawatt level. The proposed design can be expanded to other specifications as well. [ABSTRACT FROM AUTHOR]

In this article, the output voltage control strategy of modular multilevel resonant dc converters (MMRDC) for medium-voltage wide-input-range applications is studied. First, the feasibility and influence of the switching frequency regulation and modulation index regulation are investigated in detail. It is found that the switching frequency choice has a significant effect on the voltage stress of arm inductors and the transformer. Then, based on these considerations, the modulation index regulation plus switching frequency regulation based design and control optimization is proposed. With the proposed design and control method, the switching frequency range for adapting to a wide input range is further reduced, especially under light load operating conditions. Besides, the high voltage stress on arm inductors is avoided and the high voltage dv/dt on the transformer is also eliminated. Finally, a laboratory prototype with 8–16 kV input and 375 V/60 kW output has been built and the experimental validation under a wide input range has been done. The efficiency over 96.4% under the wide input range proved the effectiveness of the optimized control methods. [ABSTRACT FROM AUTHOR]

A boost-type converter is derived by inserting a third winding of the winding-cross-coupled inductors (WCCIs) between the secondary winding and the output diode of the interleaved flyback converter in this paper. A family of isolated interleaved boost or buck dc/dc converters with WCCIs is summarized by employing the four main types of interleaved structures, which is suitable for step-up or step-down isolated distribution power systems. Then, an interleaved flyback-boost converter with WCCIs and an active clamp circuit is analyzed as an example to explore the advantages of the derived converters. The active clamp scheme is adopted to recycle the leakage energy and to suppress the turn-off voltage spikes on MOSFETs. And only one set of active clamp circuit is necessary for the interleaved two phases. Zero voltage transition (ZVT) soft switching performances are achieved for all MOSFETs during the whole switching transition. Furthermore, the output diode turn-off current falling rate is controlled by the inherent leakage inductance of the WCCIs, and the output diode reverse-recovery problem is alleviated. A clear picture is made in this paper of the general law and structure of the isolated interleaved dc/dc converters with WCCIs. At last, a 650 W prototype with 48 V-to-180 V is built and tested to verify the theoretical analysis in this paper. Index Terms--Active clamp, interleaved converter, winding-cross-coupled inductor (WCCI).

A basic cell with winding-cross-coupled inductors (WCCIs) and interleaved structure is proposed in this paper. A family of dc-dc converters is deduced from the proposed basic cell, which is suitable for high step-up or step-down conversions. The passive-lossless clamp scheme is derived from the active clamp scheme to recycle the leakage energy and to suppress the voltage spikes caused by the leakage inductance. The advantages of the derived interleaved boost converter with WCCIs and passive-lossless clamp circuits are analyzed as an example. The voltage gain is extended and the switch voltage stress is reduced to minimize the conduction losses. The rectifier reverse-recovery problem is alleviated by the leakage inductance. Furthermore, a series of dc-dc converters with WCCIs and passive-lossless clamp circuits are summarized for high efficiency, high power and high step-up or step-down applications. A clear picture is made in this paper on the general law and structure of the WCCIs for dc-dc conversion in high step-up or step-down applications. At last, the simulated and experimental results of a 1 kW 40 V-to-380 V prototype with WCCIs and passive-lossless clamp circuits verify the significant improvements in performance. Index Terms--Basic cell, passive-lossless clamp, winding-cross-coupled inductor (WCCI).

The fundamental limitations of the current topologies for isolated high step-up dc-dc conversion are summarized. The primary-parallel-secondary-series structure is employed in this paper to handle the large input current, sustain the high output voltage and extend the voltage gain. A novel active clamp boost converter with coupled-inductors is proposed for high step-up applications. The third windings of the coupled-inductors have the function of voltage gain extension and the switch voltage stress reduction. The active clamp circuit serves for the interleaved two phases, which reduces the circuit complexity. Both the main and the auxiliary switches of the proposed converter are zero voltage transition performances during the whole switching transition. Meanwhile, the leakage energy is recycled by the active clamp circuit. The rectifier voltage stress is reduced by the primary-parallel-secondary-series structure. The rectifier reverse-recovery problem is alleviated by the leakage inductance. Experimental results for a 40-V-to-760-V converter verify the significant improvements in efficiency. Index Terms--Active clamp, coupled-inductors, isolated boost converter.

An interleaved winding-coupled boost converter is proposed in order to realize ZCS turn-on condition and to achieve high step-up gain. The voltage gain is extended easily and the voltage stress on the switches is reduced with different turns ratios of the coupled inductors. The output diode reverse-recovery problem is alleviated due to the inherent leakage inductor of the winding-coupled inductors. The simple but effective passive lossless clamp circuits are introduced to limit the voltage stress on the switches when they turn off so that the low-voltage, high-performance devices with low conduction resistor can be used in the proposed converter to reduce the relative losses. The leakage energy is ultimately recovered to the load. The high efficiency of 90.7% at full load and the maximum efficiency of 92.6% are achieved in a 1-kW 40-V-input-to-380-V-output prototype for front-end application. There is more than 10% efficiency improvement with the passive lossless clamp circuits compared to the case with RCD dissipated snubbers. The efficiency of 5% improvement at full load is achieved with the proposed converter with passive lossless circuits compared to the conventional interleaved boost converter. Index Terms--Interleaved boost, passive lossless clamp, winding-coupled inductors.

The modularity of a modular multilevel dc converter (MMDC) makes it attractive for medium-voltage distribution systems. Inherent balance of submodule (SM) capacitor voltages is considered as an ideal property, which avoids a complex sorting process based on many measurements thereby reducing costs and enhancing reliability. This article extends the inherent balance concept previously shown for square-wave modulation to a multilevel version for MMDCs. A switching duty matrix dU is introduced: it is a circulant matrix of preset multilevel switching patterns with multiple stages and multiple durations. Inherent voltage balance is ensured with a full-rank dU. Circulant matrix theory shows that this is equivalent to a simplified common factor criterion. A nonfull rank dU causes clusters of SM voltage rather than a single common value, with the clusters indicated by the kernel of the matrix. A generalized coprime criterion is developed into several deductions that serve as practical guidance for design of multilevel circulant modulation. The theoretical development is verified through full-scale simulations and downscaled experiments. The effectiveness of the proposed circulant modulation in achieving SM voltage balance in an MMDC is demonstrated. [ABSTRACT FROM AUTHOR]

In this letter, a junction-temperature and current extraction method is presented based on the electroluminescence mechanism of the SiC mosfet body diode. Starting from the observation of two characteristic peaks in the emitted light spectrum, we proved that the junction temperature and the drain current can be simultaneously measured. This novel method consists of decoupling the relationship between the intensity of the electroluminescence peaks, the current, and the temperature. Through this optical method with inherent electrical isolation, the junction temperature and current in the SiC chip can be simultaneously measured with high precision. The total error of the junction temperature estimation is within ±3 °C, and the error of the current estimation is about ±0.2 A. [ABSTRACT FROM AUTHOR]

A shunt active power filter (SAPF) is coupled with load admittance in weak grid conditions, which poses a challenge to stability analysis. In this article, the admittance model of the SAPF is developed, which reveals the coupling mechanism between SAPF and load concisely and accurately. On top of that, the stability region of the system is investigated. The passivity region of the load admittance to guarantee the system stability is first explored. However, the passivity region has a very narrowband at a specific frequency, which makes it difficult to achieve. The stability region is then studied and it turns out to be an extension of the passivity region, and especially the narrowband is expanded. Therefore, the stability region is much easier to meet. The stability-oriented design is then summarized in a flowchart. In the end, the effectiveness of the newly defined stability region is verified by experimental results. [ABSTRACT FROM AUTHOR]

This work presents a 48-1V dc–dc converter with an on-chip switch and gallium nitride (GaN) hybrid power conversion. By series connecting a 12-level Dickson switched-capacitor with a two-phase switched-inductor circuit, the capacitors take over most of the 48-V voltage stresses. The circuit, thus, reduces to an equivalent 4-1V converter, making the on-chip 5-V transistor applicable for a 48-V high-voltage design. Due to the easy integration of on-chip switches and superior switch figures of merit over other 48-1V counterparts, this proposed design is able to achieve the highest switching frequency, the lowest external switch count, and the improved power density compared with other prior-state-of-the-arts. The prototype was fabricated using a 0.18- $\mu \text{m}$ BCD process with an evaluation board volume of 17 mm $\times $ 15 mm $\times $ 2.6 mm. The converter achieves a maximum 8-A loading capacity with the input range from 36 to 60 V and the output from 0.5 to 1 V. The measured peak power efficiency is 90.2%, and the power density is 998 A/in3 considering the power stage volume. [ABSTRACT FROM AUTHOR]

The wear resistance capability of die surfacing layer under different Post Weld Heat Treatments (PWHT) was analysed by Finite Element Method (FEM) simulation and experiments. Taking the hot forging process of crankshaft as example, a wear model of hot forging die coated with surfacing layer was established by the software DEFORM-3D. The simulation results indicate that the wear resistance capability of the die surfacing layer is optimal when tempering temperature and holding time are 550 ∘C and 4h respectively. To verify the wear calculation result, 16 groups of different PWHT orthogonal wear tests were performed under atmospheric condition at 400 ∘C. The wear test result shows a good agreement with the FEM simulation result. SEM observation of the wear debris shows that oxidative wear plays a dominant role in 400 ∘C among 16 specimens. Furthermore, when tempering temperature and holding time are 550 ∘C and 4h respectively, the alloy carbide dispersively distributes in the metallographic structure, which can improve the wear resistance of the surfacing.

The wear resistance capability of die surfacing layer under different Post-Welding Heat Treatments (PWHT) was analysed by Finite Element (FE) simulation and experiments. Taking hot forging process of a crankshaft as an example, a wear model of the hot forging die coated with surfacing layer was established using FE software DEFORM-3D. The simulation results indicated that the wear resistance capability of the die surfacing layer is optimal when tempering temperature and holding time are 550 °C and 4 h respectively. To verify the wear computational results, 16 groups of PWHT orthogonal wear tests were performed at a temperature of 400 °C, which is a similar temperature to that occurs in an actual hot forging die. The wear-test result showed a good agreement with the FE simulation. SEM observation of the wear debris on 16 specimens showed that oxidative wear is dominant when the temperature was in 400 °C. Furthermore, when tempering temperature and holding time were 550 °C and 4 h respectively, the carbide alloy dispersively distributes in the metallographic structure, which helps to improve the wear resistance of the surfacing layer.

Series connection of SiC power MOSFET is an attractive approach to expand the blocking voltage of SiC devices, whereas the dynamic voltage balancing among the series-connected devices is the most critical challenge of the technique. In this article, a simple, fast, and cost-effective dynamic voltage balancing circuit of the series-connected SiC MOSFETs is proposed to suppress the voltage imbalance among the devices. The proposed circuit is composed of a resistor-capacitor (RC) snubber with a coupled inductor to effectively sense the voltage imbalance and add a compensated signal to the gate driving voltage. In the article, the operation principle of the proposed method is described in detail and the parameter selection of the circuit is given. Then the optimized layout of the circuit in a typical half-bridge SiC power module is proposed to reduce the stray parameters introduced by the coupled inductor effectively. The proposed method is verified by experiments under different conditions. Compared with a purely RC snubber balancing strategy, the capacitor can be significantly reduced. Since only passive components are required in the feedback loop, the proposed method demonstrates a reliable and straightforward approach to achieve equal voltage sharing of the series-connected devices. [ABSTRACT FROM AUTHOR]

The oscillation frequency of the point of common coupling (PCC) voltage is proposed as a new detecting freedom for dc-based islanding events in this article. In the presented method, the voltage positive feedback with a frequency selection is applied to a distributed generator to make the PCC voltage oscillate at the selected frequency when islanding events occur. With the frequency information, islanding events can be identified by the small-amplitude oscillation superimposed on the normal dc voltage without the necessity of voltage amplitude to be shifted out of the normal range. Thus, the islanding events can be effectively distinguished from other abnormal conditions that lead to large voltage fluctuations, and so, the accuracy of islanding detection is improved. Also, the power quality at islanding events is enhanced, which provides important benefits for seamless transfer from the unintentional islanding conditions to the controlled islanding conditions. Moreover, the frequency selection is designed to only transfer the voltage signal at the sensitive frequency band of the islanding condition. As a result, the deterioration of stability caused by the voltage positive feedback can be relieved under the grid-connected condition compared to the existing methods. Finally, the effectiveness of the proposed method has been verified by both time-domain nonlinear simulation and experimental results. [ABSTRACT FROM AUTHOR]

DC transformers based on power electronics are key items of equipment for medium voltage dc (MVDC) distribution systems. Both high and low step-ratio dc–dc conversions are required to interface dc links at different voltages to form an integrated dc distribution system. The transformer-coupled resonant modular multilevel dc–dc converter (RMMC) is well-suited to high step-ratio connection between an MVDC network and a low voltage dc network but it is not suitable in low step-ratio conversion for linking two MVDC networks with similar but not identical voltages. This article presents a circuit evolution of the high step-ratio transformer-coupled RMMC into its low step-ratio transformer-less RMMC counterpart. These two RMMCs share the same structure and the same resonant process within the resonant submodule stack giving rise to the same operational advantages. Also, the circuit design experience can be readily transferred from one to the other. From these two base RMMC circuits, a family of RMMCs with further configurations is elaborated that provide a wider variety of connection options for MVDC distribution systems. In this circuit family, each high step-ratio transformer-coupled RMMC has a low step-ratio transformer-less RMMC counterpart and one can be transformed into the other via the circuit evolution process presented. The theoretical analysis for both high and low step-ratio RMMCs has been verified through full-scale simulations of medium voltage examples and further verified through down-scaled experiments on laboratory prototypes. [ABSTRACT FROM AUTHOR]

This brief presents a simple and power-efficient impedance adapting compensation scheme for high current NMOS low-dropout regulators (LDOs). By the proposed technique, the low-frequency node impedance retains to high value, while the high-frequency impedance is greatly attenuated. Therefore, both high gain and decent transient response is achieved simultaneously. Besides, the proposed impedance adaption waived the need for a commonly required power-hungry driver circuit, leading to a more simplified and energy-efficient design. In addition, the load-tracking technique is applied to further cancel the effect of load current variations, and helps achieve decent frequency and transient responses over a wide load range. Fabricated in a 0.35 ${\mu }\text{m}$ CMOS process, the chip regulates an output voltage form 0.8 V to 1.8 V with 6 A current capacity and 114 mV maximum dropout voltage. The measurement results show an over-/undershoot voltages of 35.4 mV and −32.2 mV, respectively, for load transitions between 400 mA and 5A. The load and line regulations are 0.7mV/A and 0.12 mV/V, respectively, and the power supply rejections are −55 dB and −30 dB at 10 KHz and 1 MHz, respectively. [ABSTRACT FROM AUTHOR]

In this article, the arm phase-shift conducting modulation (PSCM) is proposed for the alternate arm multilevel converter (AAMC). With the PSCM strategy, the half-bridge (HB) structure could be applied as the submodule (SM) topology to reduce the circuit complexity of the full-bridge submodule based AAMC. First, the phase-shift angle is introduced to match the voltage modulation ratio and power factor of ac grid. The energy stored in the submodule capacitors are balanced by regulating the phase-shift angle. Then, the design criteria and operation performance for HBSM-AAMC with the proposed PSCM strategy are analyzed and presented. Compared with HBSM-modular multilevel converters (MMC), 18% HBSMs and 9% power devices are reduced with the proposed topology and modulation, resulting in the lower construction cost. Furthermore, the loss distribution is analyzed, and the operating losses of HBSM-AAMC are smaller than that of HBSM-MMC. Finally, the simulation and experiment are performed to verify the effectiveness of the derived topology and the proposed modulation strategy. [ABSTRACT FROM AUTHOR]

Nowadays, due to the growing demands of data centers, the traditional line frequency transformer based data center power distribution system (DC-PDS) is becoming bulky and inefficient. Although SST-based DC-PDS dramatically improves the system efficiency, the traditional multicell SST with input-series output-parallel architectures has limitations. Using high-voltage devices to develop single-cell SST improves system performance, however, its application is limited by high-voltage power devices. As an alternative solution, achieving high blocking voltage through the series connection of low-voltage devices brings several advantages. Nevertheless, the series connection brings about two main problems, namely the voltage imbalance among devices and the increment of switching loss. This article proposes a medium voltage series resonant converter (MVSRC) with series-connected SiC MOSFETs. By adding snubber capacitor to each SiC MOSFET and working at LLC resonant soft-switching mode, the voltage imbalance is reduced and switching loss is decreased. Due to snubber capacitors, there are differences between MVSRC and traditional LLC converter, hence the analytical model of MVSRC is established. Moreover, the voltage imbalance model is established and the voltage imbalance sensitivity is defined to guide the snubber parameter selections. Then, a design example of the 99% efficient 5-kV/400-V prototype is presented. Last, the experimental results show that the voltage imbalance is reduced effectively and the switching loss is decreased dramatically, verifying the validity of proposed methods and the accuracy of analysis. [ABSTRACT FROM AUTHOR]

Integrated charging for electric vehicles (EVs) is considered as a good transitional scheme to expand the mileage range under the battery capacity limit. It can save the costs and reduce the volume by replacing the on-board charger, and can increase the charging power by reusing the high power propulsion system. Then, the charging and propulsion system will therefore be light and compact. As the charging topology is based on the propulsion system, the design degrees of freedom are not very high, further resulting in limited application. And the laws of topological construction are lacking. Therefore, most of the integrated charging schemes are designed for a specific occasion and are difficult to adopt for other applications. In this article, a general derivation law with a unified design criterion is proposed to improve the generality of integrated charging, by considering the charging torque and equivalent filter inductance of the multiplexed converter and motor. The criterion is illustrated and analyzed in a specific scheme that is applied in the Toyota plug-in hybrid EV. The simulation results in a software-in-the-loop environment and experimental results in a down-scaled prototype are demonstrated to confirm the validity of the unified criterion and the effectiveness of the control schemes. It is suitable for the design of integrated charging solutions with multiphase power and multiphase motors. [ABSTRACT FROM AUTHOR]

The modular multilevel matrix converter (M3C) is introduced and applied to a single-stage ac/dc solid-state transformer (SST), which uses only one concentrated medium-frequency transformer (MFT) for isolation. As a result, the transformer insulation design is simplified significantly and higher power density could be achieved. Meanwhile, a novel decoupling transformation based on two internal three-phase circulating systems is proposed to improve the previous method. Through this transformation, the unbalanced capacitor voltage components can be divided into four independent dimensions, which correspond to four kinds of capacitor voltage ripple frequency. And a dc-side vector model is then established to calculate the required circulating current reference for capacitor balancing. Besides, under the application of SST, the capacitor voltage ripple suppression strategy via injection of extra circulating current is proposed. The amplitude and frequency index is optimized to obtain the best effect. Therefore, the submodule capacitor volume can be reduced to achieve higher power density. Simulation and experimental results are also provided to verify the theoretical analysis. [ABSTRACT FROM AUTHOR]

A modular multilevel resonant (MMR) dc–dc converter, its modulation, and control are proposed in this article. The MMR converter inherits the desirable features of both the modular multilevel converter and LLC resonant converter, such as high voltage capability, easy fault-tolerant operation, and soft switching. Besides, the MMR can regulate the output voltage over a wide input voltage range with much narrower frequency range compared to conventional resonant converters. By constantly inserting certain number of submodules into the arm according to the input voltage, the resonant tank voltage can be regulated with a relatively constant amplitude regardless of the wide input variation. This modulation technique is acted as a feedforward loop to roughly regulate the output according to the input voltage, and the feedback loop in the control system precisely regulates the output by varying the switching frequency. Simulations on a 200-kW MMR that converts 9–15 kV to 750 V are provided to verify the effectiveness of the proposed topology and control method. Experimental results on an MMR prototype are also given to demonstrate the feasibility. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive solution to mitigate the sub-synchronous oscillation (SSO) in wind farms connected to series-compensated transmission lines. The concept of motion-induction amplification (MIA) is introduced to reinterpret the physical root cause of the negative resistance in doubly-fed induction generators (DFIGs). Based on this new interpretation, a novel control scheme called motion-induction compensation (MIC) is proposed to counteract the MIA effect. The MIC control eliminates the negative resistance in DFIGs across the entire frequency range, and makes the Type-III (DFIG) generator behave like a Type-IV generator in dynamics. The proposed solution provides wide-range SSO damping and also shows excellent robustness against model and measurement errors. [ABSTRACT FROM AUTHOR]

The thermal management plays an important role in improving the reliability and lifetime of high power converters, especially for the high voltage direct current (HVdc) transmission system. In the voltage source converter based HVdc systems (VSC-HVdc), the hybrid modular multilevel converters (MMCs) are taken as the excellent candidates due to their dc short-circuit fault ride-through ability and less submodule (SM) devices. Furthermore, the voltage modulation index of hybrid MMCs can be promoted to achieve higher power rating and efficiency. However, in this article, it is revealed that thermal stress distribution inside the SMs becomes more unbalanced under a high voltage modulation index, which would lead to serious thermal fatigue. To overcome this problem, the active bypass with thyristor for half-bridge submodules (HBSMs) and symmetrical modulation for full-bridge submodules (FBSMs) based active thermal control strategies are employed. With the presented thermal control strategies, the junction temperature of the most stressed devices in both HBSMs and FBSMs is reduced enormously. Besides, the thermal control strategy does not bring negative influence on the steady-state output performance of hybrid MMC. Finally, the theoretical analysis and effectiveness of the proposed control methods are verified based on a laboratorial MMC prototype. [ABSTRACT FROM AUTHOR]

Medium-voltage high-speed drive is promising in applications, such as the centrifugal compressors and electrified transportation. However, it raises lots of design challenges for the converters, which drive the motors. A SiC and Si hybrid ANPC converter is developed to address these challenges. In this article, the essence of this hybrid structure is investigated to clearly show the derivation process of the hybrid active neutral-point-clamped (ANPC) converter and inspire future research on these hybrid topologies. A dedicated space vector modulation (SVM) scheme is proposed for the hybrid ANPC converter, which enables the three-phase hybrid ANPC converter operating with SiC mosfets in high frequency and Si IGBTs in fundamental frequency. A neutral point (NP) voltage balancing scheme is added to the SVM scheme to balance the NP voltage imbalance under low-frequency modulation index. All these efforts make the hybrid ANPC converter become a high power density and fairly low-cost solution. A 400 Hz fundamental frequency, 3.6 kHz switching frequency, medium-voltage high-speed drive system is assumed and tested by the scaled-down experimental results. The effectiveness of the proposed SVM and NP voltage balancing method have both been verified. [ABSTRACT FROM AUTHOR]

Reactive power control loop (RPCL) in virtual synchronous generator (VSG) plays the role of excitation circuit in conventional SG. The control strategy improvement or parameters configuration method of RPCL is always the emphasis of analysis. However, the impacts of RPCL on VSG system performance are usually overlooked. On the basis of that, this study aims to investigate the effects of RPCL on power control performance. First, a simplified SG model is established and implemented to VSG. Then, VSG system modelling with state equations in power control time scale is elaborated. The excitation current in the modelling is regarded as one crucial state variable to identify the effects of the excitation circuit on VSG system. Eigenvalue locus analysis and eigenproperties analysis reveal how the excitation circuit affects power oscillation damping performance and even results in power coupling issue of power control. The effects of operating points on system power control are also taken into account. Finally, the experimental results are given to verify the theoretical analysis. [ABSTRACT FROM AUTHOR]

In this letter, a compact silicon carbide (SiC) power module featuring low stray inductance and balanced thermal resistance is proposed. To make full utilization of SiC devices in high-frequency and high-power-density applications, the laminated busbar and double-sided cooling heatsinks are directly packed as parts of the SiC power module. To balance the mechanical and thermal stress on the chips, a press-pack-like package technology is adopted. The electrical and thermal experiments of the prototype are evaluated to validate the design of low inductance and balanced thermal distribution. [ABSTRACT FROM AUTHOR]

The crosstalk voltage on the gate-source terminal of SiC power mosfets in a phase-leg circuit is composed of the gate–drain capacitor introduced voltage and the common-source inductor introduced voltage. The mathematical model of the crosstalk voltage indicates that to suppress two types of crosstalk voltage, there exists a contradictory requirement on the off-state gate loop impedance. This challenge reduces the effectiveness of conventional crosstalk elimination methods. As an improvement, a crosstalk voltage suppression circuit that synchronously eliminates the crosstalk voltage of gate–drain capacitance and the common-source inductance is proposed. In this article, instead of creating low-impedance gate loop in the off-state, a high-impedance gate loop is formatted to eliminate the voltage drop on the common-source inductance. Meanwhile, the potential false turn-on or the negative voltage spikes caused by gate–drain capacitance is eliminated by the precharge voltage in the gate-source capacitor. The required prestored charge is analyzed considering the nonlinear behavior of the junction capacitance of the SiC mosfets. The proposed gate driver is experimentally verified in different switching conditions. [ABSTRACT FROM AUTHOR]