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As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

uIn this work, we discuss three novel Ti (germano-)silicidation techniques featuring respectively the pre-contact amorphization implantation (PCAI), the TiSi co-deposition, and Ti atomic layer deposition (ALD). All three techniques form TiSix(Ge-y) contacts with ultralow contact resistivity (rho(c)) of (1-3)x10(-9) Omega.cm(2) on both highly doped n-Si and p-SiGe substrates: these techniques meet rho(c) requirement of 5-14 nm CMOS technology and feature unified CMOS contact solutions. We further discuss the compatibility of these techniques to the realistic CMOS transistor fabrication.

© 2016 Author(s). Applying simulations and experiments, this paper systematically compares contact resistivities (ρc) of metal-insulator-semiconductor (MIS) contacts and metal-semiconductor (MS) contacts with various semiconductor doping concentrations (Nd). Compared with the MS contacts, the MIS contacts with the low Schottky barrier height are more beneficial for ρc on semiconductors with low Nd, but this benefit diminishes gradually when Nd increases. With high Nd, we find that even an "ideal" MIS contact with optimized parameters cannot outperform the MS contact. As a result, the MIS contacts mainly apply to devices that use relatively low doped semiconductors, while we need to focus on the MS contacts to meet the sub-1 × 10-8 Ω cm2 ρc requirement for future Complementary Metal-Oxide-Semiconductor (CMOS) technology. ispartof: Applied Physics Letters vol:108 issue:17 pages:1-5 status: published

Accurate determination of contact resistivities ( ${\rho_{c}}$ ) below $1 \times 10^{-8}\Omega \cdot \text {cm}^{2}$ is challenging. Among the frequently applied transmission line models (TLMs), circular TLM (CTLM) has a simple process flow, while refined TLM (RTLM) has a high $\rho _{c}$ accuracy at the expense of a more complex fabrication. In this letter, we will present a novel model—multiring CTLM (MR-CTLM) , which combines the advantages of a simple process and a high $\rho _{c}$ extraction resolution. We fabricated ultralow- $\rho _{c}$ Ti/n-Si contacts and demonstrated the capability of MR-CTLM to extract the $\rho _{c}$ as low as $6.2 \times 10^{-9}~\Omega \cdot {\rm cm}^{2}$ with high precision.

Thin vanadium nitride (VN) layers were grown by atomic layer deposition using tetrakis(ethylmethylamino)vanadium and NH3 plasma at deposition temperatures between 70 °C and 150 °C on silicon substrates and polymer foil. X-ray photoelectron spectroscopy revealed a composition close to stoichiometric VN, while x-ray diffraction showed the δ-VN crystal structure. The resistivity was as low as 200 μΩ cm for the as deposited films and further reduced to 143 μΩ cm and 93 μΩ cm by annealing in N2 and H2/He/N2, respectively. A 5 nm VN layer proved to be effective as a diffusion barrier for copper up to a temperature of 720 °C.

Vanadium dioxide (VO2) has the interesting feature that it undergoes a reversible semiconductor-metal transition (SMT) when the temperature is varied near its transition temperature at 68°C.1 The variation in optical constants makes VO2 useful as a coating material for e.g. thermochromic windows,2 while the associated change in resistivity could be interesting for applications in microelectronics, e.g. for resistive switches and memories.3 Due to aggressive scaling and increasing integration complexity, atomic layer deposition (ALD) is gaining importance for depositing oxides in microelectronics. However, attempts to deposit VO2 by ALD result in most cases in the undesirable V2O5. In the present work, we demonstrate the growth of VO2 by using Tetrakis[EthylMethylAmino]Vanadium and ozone in an ALD process at only 150°C. XPS reveals a 4+ oxidation state for the vanadium, related to VO2. Films deposited on SiO2 are amorphous, but during a thermal treatment in inert gas at 450°C VO2(R) is formed as the first and only crystalline phase. The semiconductor-metal transition has been observed both with in-situ X-ray diffraction and resistivity measurements. Near a temperature of 67°C, the crystal structure changes from VO2(M1) below the transition temperature to VO2(R) above with a hysteresis of 12°C. Correlated to this phase change, the resistivity varies over more than 2 orders of magnitude.

Deposited silicon and, in particular, hydrogenated amorphous silicon forms an attractive alternative platform for realizing compact photonic integrated circuits. In this paper we report on trimming (toward lower wavelengths) and tuning (toward higher wavelengths) of photonic devices through a suitable thermal treatment. The former is achieved by a material density change, the latter through the thermo-optic effect. By using Fourier transform infrared spectroscopy, a change in the hydrogen content is identified as the source of the density change. A total wavelength tuning range of 24.6 nm is achievable, which can be used for compensating fabrication imperfections. c 2010 American Institute of Physics. [doi:10.1063/1.3479918]