Search

Internet of things (IoT) has evolved as the internet of everything, and it has grabbed the interest of all the researchers in recent days. Almost all the objects, including nonelectronics devices, can also be connected with the internet through radio frequency identification (RFID) technology. The security of the perception layer is crucial to secure the entire IoT network. RFID-enabled IoT perception layer has secured reader-to-server channel and unsecured tag to reader channel. Hence, securing the unsecured communication channel between the reader and the tag is the need of the hour. This work proposes a simple yet secure permutation approximate adder (SYSPXA)-based RFID mutual authentication protocol to address the need. The proposed protocol dramatically reduces the tag's storage and computational overhead. It needs 40% less storage and 66.7% less permutation operation in comparison with the existing protocols. Nondisclosure of the key and freshness of key, IDS and random numbers at every mutual authentication process gives resistance to the protocol against de-synchronization attack, disclosure attack, tag tracking, replay attack. The SYSPXA protocol is validated for its security features using Burrows–Abadi–Needham (BAN) logic formal verification. The performance and security of the proposed protocol are contrasted with various futuristic permutation-based protocols, and its superiority over other protocols is highlighted. We have simulated the SYSPXA protocol with ModelSim tool for verifying its functionality. The protocol encoder architecture is implemented in the Intel cyclone IV Field Programmable Gate Array (FPGA) EP4CE115F29C7 device. [ABSTRACT FROM AUTHOR]

Wireless sensor networks find applications everywhere in day to day activities right from attendance entry systems to healthcare monitoring systems. The evolution of the Internet of Things (IoT) as the Internet of Everything (IoET) makes the wireless sensor network omnipresent and increases the use of Radio Frequency Identification (RFID) for the proper identification of devices and sensor nodes which are mostly battery operated. As technology evolves, security threats also increase rapidly. This mandates a strong and energy-efficient green solution. This work attempted to address these issues by effectively deploying the lightweight encryption scheme called Extended Tiny Encryption Algorithm (XTEA). Though the XTEA is lightweight and famous, it is commonly known for various attacks. Our work patches the security threats in the XTEA by applying domain-specific customization, random number utilization, and undisclosed key renewal techniques. Two custom Renovated XTEA Mutual Authentication Protocol (RXMAP) encoder architectures, namely, RXMAP-1 and RXMAP-2, are proposed based on the replacement of accurate computational blocks with approximate blocks. The proposed RXMAP protocol is evaluated for its computational and storage overhead and verified against various security threats using BAN logic formal verification and informal verification. The proposed encoder architectures are simulated for functional verification, and ASIC implementation is done with a 132 nm process node. ASIC implementation results show that the proposed designs RXMAP-1 and RXMAP-2 occupy 53.11% and 53.31% lesser area compared to XTEA I and 52.97% and 53.18% lesser area compared to XTEA II implementation. The total power consumed by the proposed encoder architectures RXMAP-1 and RXMAP-2 is 68.76% and 71.64% lesser than XTEA II implementation, respectively, while maintaining the equal throughput. [ABSTRACT FROM AUTHOR]

The post‐silicon validation and debug is the most important task in the contemporary integrated circuit design methodology. The vital problem prevailing in this system is that it has limited observability and controllability due to the minimum number of storage space in the trace buffer. This tends to select the signals prudently in order to maximize state reconstruction. In the reported works, to select and to restore the signals efficiently it is categorized into two types like low simulation with high‐quality technique and high simulation with low‐quality technique. In this work, a node‐based combinational gate signal selection algorithm is proposed based on machine learning method that maximizes the state restoration capability. A significant improvement (80%) has made to achieve adequate simulation time with the high‐quality associated with the state‐of‐the‐art of supplementary methods. [ABSTRACT FROM AUTHOR]

Approximate computing is a rapidly growing technique to speed up applications with less computational effort while maintaining the accuracy of error-resilient applications such as machine learning and deep learning. Inheritance properties of the machine and deep learning process give freedom for the designer to simplify the circuitry to speed up the computation process at the expense of accuracy of computational results. Fundamental blocks of any computation are adders. In order to optimize it for better performance, 2-bit multi-bit approximate adders (MAPX) are proposed in this work which breaks the lengthy carry chain. In contrast with other approximate larger width adders, instead of using accurate adders for the most significant part, here proposed 2-bit MAPX-1 and MAPX-2 adders are arranged in various ways to compose most and least significant parts. Designed 8-bit and 16-bit adders are evaluated for their performance and error characteristics. Proposed 2-bit MAPX-2 shows better error characteristics whose MED is 0.250 while occupying less area and MAPX-1 consumes less power and delay at the cost of accuracy. Among the extended adders, MAPX 8-bit adder design1 outperforms the best performing APX based 8-bit adder design1. The error performance of it is improved by 14%, 42.1% and 50.4% compared to the existing well-performing APX 8-bit Design1, Design2 and Design3 respectively. Similarly, proposed MAPX 16-bit Design1 exhibits overwhelming performance compared to best performing APX 16-bit Design1, and its error performance is improved by 24.3%, 34.9% and 50.3% compared to APX 16-bit Design1, Design2 and Design3 respectively. In order to evaluate the proposed adder for a real application, extended MAPX 16-bit Design1 is fit in the convolution layer of Low Weights Digit Detector (LWDD) convolutional neural network-based digit classification system. Our modified system accelerates the computation process by 1.25 factors while exhibiting the accuracy of 91% and it best fits error-tolerant real applications. All the adders are synthesized and implemented in the Intel Cyclone IV EP4CE22F17C6N FPGA. [ABSTRACT FROM AUTHOR]

In modern System on Chip (SoC) design consist of intelligence of products, Internet of Things (IoT) based devices, mobile phones, laptops, servers etc. This shrinking market reduces the design automation validation process. Signal selection is the most effective and challenging technique in post-silicon validation and debug. The vital problem prevailing in this method is that it has limited observability and controllability due to the minimum number of storage space in the trace buffer. This tends to select the signals prudently in order to maximize the state reconstruction. To identify the trace signals, signal restoration is the extensive metric that has been used so far. Topology-based restoration method is proposed here to minimize the error detection latency which helps to select the trace signals with minimum error or even errorless. This method aid to detect more number of errors within limited number of clock cyclesthan the restoration only selection techniques. [ABSTRACT FROM AUTHOR]

Guaranteeing the reliability of cyber-physical systems (CPS) requires analog integrated circuits for correct functioning. Analog integrated circuits capture the continuous signal and amplify the signal for further processing in CPS applications. This paper presents the hybrid swarm intelligence based approach for determining the optimal transistors sizes and bias current values of CMOS differential amplifier and an operational amplifier. We proposed the simplex search based global optimization method called a hybrid grey wolf optimization (GWO) for solving amplifiers circuit sizing problems. Simplex and GWO techniques were combined to improve the local search capabilities of the optimization method. Our main aim is to optimize the transistor size and bias current values using hybrid GWO algorithm for an optimal design of the CMOS amplifiers. CMOS 180 nm technology was utilized to finding the circuit performance using proposed optimization approach. Simulation result shows that the proposed method provides the better result for circuit performance parameters such as DC gain, phase margin, unity gain bandwidth and power dissipation. [ABSTRACT FROM AUTHOR]

In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies. [ABSTRACT FROM AUTHOR]

Sweep frequency response analysis (SFRA) is a diagnostic technique which can identify faults within transformers. Though SFRA approaches are used to identify faults, their effectiveness in discriminating two same level faults at two different locations within transformer is not much analysed and reported. Experiments were carried out on a 1 kVA, single phase, 240 V/240 V laboratory transformers and on a 315 kVA, three phase, 11 kV/433 V, Dyn11, ONAN, distribution transformer, to analyse the usefulness of SFRA in inter turn short identification and discriminations. Faulty conditions were created artificially in transformers, by shorting the tappings provided in one of their windings, at different levels and locations. Open circuit self-impedance and transfer voltage transfer function approaches were experimented and transfer function plots representing winding impedance and voltage transfer ratios at various frequencies were developed for transformers, under normal and faulty conditions. Significant differences were identified at some frequencies while comparing normal case plots with faulty case plots. It was observed that the SFRA is effective in identifying shorts within transformer winding as well as, discriminating two same level shorts (i.e.) locating shorts. Statistical analysis using absolute difference and min-max ratio also confirmed the efficacy of these approaches. [ABSTRACT FROM AUTHOR]

Electrical shorts in transformers on load can be diagnosed by frequency response analysis (FRA) using impulse or sinusoidal sweep signal. At HV laboratory of SASTRA, a low-voltage impulse based on-line on-load FRA (OLOL FRA) was carried out on a single phase 50 Hz, 1 kVA, 240 V/240 V small laboratory transformer while delivering power to lamp load, and the effectiveness in electrical short diagnosis was analysed. For this purpose, some artificial faults were created within one of the windings of the transformer investigated, and the responses of the winding to different frequency components of the impulse voltages were observed before and after introducing these faults. Comparison of the frequency response (impedance) of the winding under normal condition with frequency response under fault condition was made, which clearly indicated that faults had altered the winding impedance for some frequency components of the impulse. This reveals that fault within the winding can be identified and located, by the OLOL FRA technique, through careful comparisons of frequency response. Statistical analysis of transfer function magnitudes with correlation coefficient, standard deviation and absolute sum of logarithmic error has also validated the same. [ABSTRACT FROM AUTHOR]

Electrical shorts in transformers on load can be diagnosed by frequency response analysis (FRA) using impulse or sinusoidal sweep signal. At HV laboratory of SASTRA, a low‐voltage impulse based on‐line on‐load FRA (OLOL FRA) was carried out on a single phase 50 Hz, 1 kVA, 240 V/240 V small laboratory transformer while delivering power to lamp load, and the effectiveness in electrical short diagnosis was analysed. For this purpose, some artificial faults were created within one of the windings of the transformer investigated, and the responses of the winding to different frequency components of the impulse voltages were observed before and after introducing these faults. Comparison of the frequency response (impedance) of the winding under normal condition with frequency response under fault condition was made, which clearly indicated that faults had altered the winding impedance for some frequency components of the impulse. This reveals that fault within the winding can be identified and located, by the OLOL FRA technique, through careful comparisons of frequency response. Statistical analysis of transfer function magnitudes with correlation coefficient, standard deviation and absolute sum of logarithmic error has also validated the same. [ABSTRACT FROM AUTHOR]