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This paper presents a 32 Gb/s non-return-to-zero optical link using 850-nm vertical-cavity surface-emitting laser-based multi-mode optics with 14-nm bulk FinFET CMOS circuits. The target application is the integration of optics on to the first-level package, connecting high-speed optical I/O directly to an advanced CMOS host chip (e.g., processor and switch) to increase package I/O bandwidth density and lower overall system power and cost. The optical link is designed for maximum link margin to tolerate high optical losses created by low-cost optical packaging. The transmitter (TX) uses a three-tap, 1/2-unit-interval-spaced feed-forward equalizer to improve eye opening. The receiver (RX) uses a low-bandwidth, low-noise transimpedance amplifier and a speculative one-tap decision-feedback equalizer for high sensitivity. The TX and RX power efficiencies are 3.3 and 1.4 pJ/bit, respectively. The TX optical modulation amplitude (OMA) is 1.2 dBm, and the RX sensitivity is −11.7 dBm OMA at a bit error rate of 10−12 with PRBS31 data, providing 12.9-dB link margin. [ABSTRACT FROM AUTHOR]

A power-scalable 2 Byte I/O operating at 12 Gb/s per lane is reported. The source-synchronous I/O includes controllable TX driver amplitude, flexible RX equalization, and multiple deskew modes. This allows power reduction when operating over low-loss, low-skew interconnects, while at the same time supporting higher-loss channels without loss of bandwidth. Transceiver circuit innovations are described including a low-skew transmission-line clock distribution, a 4:1 serializer with quadrature quarter-rate clocks, and a phase rotator based on current-integrating phase interpolators. Measurements of a test chip fabricated in 32 nm SOI CMOS technology demonstrate 1.4 pJ/b efficiency over 0.75” Megtron-6 PCB traces, and 1.9 pJ/b efficiency over 20” Megtron-6 PCB traces. [ABSTRACT FROM PUBLISHER]

This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip communications over high-loss electrical channels such as backplanes. The equalization needed for such applications is provided by a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter and a two-stage peaking amplifier and 15-tap decision-feedback equalizer (DFE) in the receiver. The transmitter employs a source-series terminated (SST) driver topology which doubles the speed of existing half-rate designs. The high-frequency boost provided by the peaking amplifier is enhanced by adopting a structure with capacitively coupled parallel input stages and active feedback. A capacitive level-shifting technique is introduced in the half-rate DFE which allows a single current-integrating summer to drive the four parallel paths used for speculating the first two DFE taps. Error-free signaling at 28 Gb/s is demonstrated with the transceiver over a channel with 35 dB loss at half-baud frequency. In a four-port core configuration, the power consumption at 28~Gb/s is 693 mW/lane. [ABSTRACT FROM PUBLISHER]

A source synchronous I/O system based on high-density silicon carrier interconnects is introduced. Benefiting from the advantages of advanced silicon packaging technologies, the system uses 50 \mum-pitch \muC4s to reduce I/O cell size and fine-pitch interconnects on silicon carrier to achieve record-breaking interconnect density. An I/O architecture is introduced with link redundancy such that any link can be taken out of service for periodic recalibration without interrupting data transmission. A timing recovery system using two phase rotators shared across all bits in a receive bus is presented. To demonstrate these concepts, an I/O chipset using this architecture is fabricated in 45 nm SOI CMOS technology. It includes compact DFE-IIR equalization in the receiver, as well as a new all-CMOS phase rotator. The chipset is mounted to a silicon carrier tile via Pb-free SnAg \muC4 solder bumps. Chip-to-chip communication is achieved over ultra-dense interconnects with pitches of between 8 \mum and 22 \mum. 8\,\times\,10-Gb/s data is received over distances up to 4 cm with a link energy efficiency of 5.3 pJ/bit from 1 V TX and RX power supplies. 8\,\times\,9-Gb/s data is recovered from a 6-cm link with 16.3 dB loss at 4.5 GHz with an efficiency of 6.1 pJ/bit. [ABSTRACT FROM PUBLISHER]

This paper presents a 90-nm CMOS 10-Gb/s transceiver for chip-to-chip communications. To mitigate the effects of channel loss and other impairments, a 5-tap decision feed- back equalizer (DFE) is included in the receiver and a 4-tap baud-spaced feed-forward equalizer (FFE) in the transmitter. This combination of DFE and FFE permits error-free NRZ signaling over channels with losses exceeding 30 dB. Low jitter clocks for the transmitter and receiver are supplied by a PLL with LC VCO. Operation at 10-Gb/s with good power efficiency is achieved by using half-rate architectures in both transmitter and receiver. With the transmitter producing an output signal of 1200 mVppd, one transmitter/receiver pair and one PLL consume 300 mW. Design enhancements of a half-rate DFE employing one tap of speculative feedback and four taps of dynamic feedback allow its loop timing requirements to be met. Serial link experiments with a variety of test channels demonstrate the effectiveness of the FFE/DFE equalization. [ABSTRACT FROM AUTHOR]

Presents information on a single-chip digital SQUID magnetometer, which integrates a sensitive analog SQUID sensor with a comparator gate and feedback circuitry on the same chip. Information on the comparator gate; Dynamic range of digital chips.

Reports on the development and demonstration of high bandwidth Josephson circuits to interface the output of Rapid Single Flix Quantum (RSFQ) circuits to room temperature electronics. Design of asynchronous dc powered voltage driver circuits; Characterization of the driver circuits.

Presents information on digital error-correction circuits which were designed, fabricated and tested to improve the performance of superconductive flash analog-to-digital converters (ADCs). Information on the comparators coding the most significant bits (MSBs); Other information on the experiment.

Compares the Superconducting Quantum Interference Device (SQUID) wheel/Quantum Flux Parametron (QFP) comparator to a Rapid Single Flux Quantum (RSFQ) compatible design. Simulation of the devices to demonstrate threshold accuracy; How the designs were demonstrated.

Presents information on a Time-to-Digital converter (TDC) which was designed, fabricated and tested. What the TDC circuit consists of; Value of th counter; How the TDC resolution is determined.