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A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology.
- Source :
- IEEE Journal of Solid-State Circuits; Aug2015, Vol. 50 Issue 8, p1917-1931, 15p
- Publication Year :
- 2015
-
Abstract
- A power-scalable 2 Byte I/O operating at 12 Gb/s per lane is reported. The source-synchronous I/O includes controllable TX driver amplitude, flexible RX equalization, and multiple deskew modes. This allows power reduction when operating over low-loss, low-skew interconnects, while at the same time supporting higher-loss channels without loss of bandwidth. Transceiver circuit innovations are described including a low-skew transmission-line clock distribution, a 4:1 serializer with quadrature quarter-rate clocks, and a phase rotator based on current-integrating phase interpolators. Measurements of a test chip fabricated in 32 nm SOI CMOS technology demonstrate 1.4 pJ/b efficiency over 0.75” Megtron-6 PCB traces, and 1.9 pJ/b efficiency over 20” Megtron-6 PCB traces. [ABSTRACT FROM PUBLISHER]
- Subjects :
- CLOCK distribution networks
COMPUTER systems
BANDWIDTHS
SILICON
WAVEGUIDES
Subjects
Details
- Language :
- English
- ISSN :
- 00189200
- Volume :
- 50
- Issue :
- 8
- Database :
- Complementary Index
- Journal :
- IEEE Journal of Solid-State Circuits
- Publication Type :
- Academic Journal
- Accession number :
- 108597472
- Full Text :
- https://doi.org/10.1109/JSSC.2015.2412688