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The effects of top-cut stress liners for damascene gate MOSFETs are examined by stress simulation. The results have shown that high channel stress is induced for shorter gate lengths and hence high drive current n- and pFETs are achieved by using top-cut stress liners with dual metal/high-k gates and eSiGe for damascene gate devices.

An experimental study of mobility and velocity enhancement effects is reported for highly strained short-channel p-channel field-effect transistors (pFETs) using a damascene-gate process on Si (100) and (110) substrates. The relationship between the mobility and the saturation velocity of hole under a compressive stress over -2.0 GPa is discussed. The local channel stress of -2.4 GPa is successfully measured with ultraviolet- Raman spectroscopy for the 30-nm-gate-length device with top-cut compressive-stress SiN liner and embedded SiGe. Mobility and saturation-velocity enhancements of (100) substrate are larger than those of (110) under the high channel stress. In consequence, the saturation current on (100) is larger than that on (110) for the pFETs with higher channel stress and shorter gate length. Moreover, the large enhancement rate of saturation velocity to mobility by the uniaxial stress suggests high injection velocity for the pFETs with the stressors since the high channel stress is induced near the potential peak of the source by using the damascene-gate technology. [ABSTRACT FROM AUTHOR]

A damascene-gate process enhances the drivability in the shorter gate length region, as compared to a conventional gate-first process for pFETs with compressive stress SiN liners and embedded source/drain SiGe. The origin of the gate length effect for damascene-gate pFETs is studied by using UV-Raman spectroscopy and stress simulation. Moreover, the relationship between channel strain and channel width is analyzed, and the enhancement effect of the drivability on channel width is demonstrated. It is found that channel strain is considerably enhanced with the narrower channel width and shorter gate length by the process combination of the damascene gate and stress enhancement techniques. Owing to the enhancement effects of both channel width and gate length, a high drive current of 1090 µA/µm at Vds = Vgs = --1.0 V and Ioff = 100 nA/µm is achieved for the damascene-gate pFET with 0.3-µm channel width and 40-nm gate length. [ABSTRACT FROM AUTHOR]

This letter provides channel-stress behavior results induced by a local strain technique which consists of the process combination of a damascene-gate and top-cut tensile stress SiN liner for narrow channel-width nFETs using 3-D stress simulations and demonstrations. The dummy-gate removal, which is an intrinsic step in the damascene-gate process, is found to enhance tensile channel stress along the gate length at the edge of the channel beside the shallow trench isolation. In consequence of a mobility boost due to the high tensile stress, drain-current enhancement in the saturation is achieved for the damascene-gate nFETs with the narrow channel width and short gate length. [ABSTRACT FROM AUTHOR]

A new concept planar metal–oxide–semiconductor field-effect transistor (MOSFET) which was fabricated by in situ doped selective Si epitaxy, has been proposed. Owing to the ultra-shallow junction, the short-channel effects were improved, and the drive current was increased by the gate overlapped structure as well. The characteristics of this new concept MOSFET were improved compared with those of a conventional MOSFET because of improvements in short-channel effects and parasitic resistances. [ABSTRACT FROM AUTHOR]

Junction depth and parasitic resistance have a trade-off relationship. To improve this relationship, in situ boron-doped selective Si epitaxy was used to fabricate metal–oxide–semiconductor field-effect transistors (MOSFETs) with raised source and drain extensions and a facet. The amount of boron diffusion was small and the MOSFET also had low extension sheet resistance. Furthermore, with the optimization of four process parameters, spike rapid thermal annealing (RTA) temperature, halo dose, impurity concentration introduced by in situ doping, and epitaxial Si thickness, the relationship between the gate length at Ioff=100 nA/µm and the drive current at Ioff=100 nA/µm was improved. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate a wet treatment for the HfSix/HfO2 gate stack of n-type metal oxide semiconductor field effect transistor (nMOSFET) fabricated by a gate-last process in order to scale down the electrical thickness at inversion state Tinv value and reduce the gate leakage Jg. As a result, we succeeded in scaling down Tinv to 1.41 nm without mobility or Jg degradation by ozone–water-last treatment. We found that a high-density interfacial layer (IFL) is formed owing to the ozone–water-last treatment, and Hf diffusion to the IFL is suppressed, which was analyzed by high-resolution angle-resolved spectroscopy. [ABSTRACT FROM AUTHOR]

We propose a fluorine (F) treatment technique that is suitable for threshold voltage (Vth) modulation in p-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) with the atomic layer deposition (ALD) TiN/HfO2 gate structure. A work function near the band edge is achieved using the F treatment technique without the degradation of hole mobility in PMOSFETs. Vth shift value is almost the same regardless of gate length. The barrier height shift attributable to the F treatment corresponds closely to the Vth shift. It is found that the F treatment technique modulates the effective work function. No Vth shift in n-channel MOSFET (NMOSFETs), namely, the ALD-TiN/HfSix/HfO2 gate stack structure, is observed with F treatment. It is confirmed that F treatment is a suitable technique for complementary MOSFET (CMOSFETs) due to the confinement of Vth shift only to PMOSFETs. [ABSTRACT FROM AUTHOR]