Search

Reconfigurable ferroelectric transistor (R-FEFET) is a variant of a ferroelectric transistor (FEFET), which utilizes two asymmetrically sized gate stacks to achieve voltage-controlled modulation in hysteresis and dynamic reconfigurability between volatile and non-volatile modes. However, due to a floating internal metal layer (IML), gate leakage (GL) can lead to a polarization-dependent shift in device characteristics over time. This degrades read disturb margins (RDM) and the non-volatile memory (NVM) robustness. In this work, we propose an R-FEFET with symmetric gate stacks to diminish the adverse effects of GL on NVM operation. Utilizing our new R-FEFET, we propose a two-transistor NVM (2T-R), which exhibits up to 12% higher energy efficiency, $3\times $ increase in the RDM, and 14% lower area compared to an existing R-FEFET NVM. We also perform variation analysis showing a robust operation of the symmetric R-FEFET NVM. [ABSTRACT FROM AUTHOR]

In this paper, we present the operation principle of an organic metal–insulator–semiconductor (MIS) capacitor where the organic semiconductor is undoped. In spite of a low charge concentration within the semiconductor, this device exhibits a capacitance variation with respect to the applied gate voltage yielding the capacitance–voltage characteristics similar to that of a traditional MIS capacitor based on the doped semiconductor. A physics-based model is developed to derive the charge concentration, surface potential, and the capacitance of the organic MIS capacitor. The model is validated with TCAD simulation results as well as with experimental data obtained from the fabricated organic MIS capacitor consisting of poly(4-vinylphenol) and poly(3-hexylthiophene-2, 5-diyl) as an insulator and a semiconductor, respectively. [ABSTRACT FROM AUTHOR]

In Part I, we proposed reconfigurable ferroelectric transistors (R-FEFETs) with a unique property of dynamic modulation between the volatile (logic) and nonvolatile (memory) modes of operation with the help of a control signal. They showcase excellent robustness in the presence of gate leakage with larger hysteresis in the nonvolatile mode with respect to ferroelectric FETs (FEFETs) and higher ON current in the volatile mode compared with standard FETs. Using the unique attributes of R-FEFETs presented in Part I, we explain the dynamics of transition between various modes of operation for circuit-level applications in this paper. We propose a 3T nonvolatile memory design that offers significant power savings over FEFET-based memories by virtue of the control terminal. Our analysis shows that the proposed R-FEFET memory exhibits 55% lower write power and 37%–72% lower read power at iso access time and 33% lower area compared with a recently proposed standard FEFET-based memory. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel reconfigurable ferroelectric FET (R-FEFET), which can reconfigure its operation between volatile and nonvolatile modes during run-time by dynamically modulating its hysteresis. The R-FEFET comprises of two gates with ferroelectric (FE) in both the gate stacks. One of these terminals serves as a regular gate, while the other is used as a control to introduce reconfigurability. Employing Landau–Khalatnikov equation-based FEFET model, we extensively analyze the device characteristics in both FinFET and planar technologies. We show that by changing the control voltage between 0 and 1 V, the hysteresis width (HW) can be modulated between 1.1 and 0.3 V. In addition, we show the device characteristics and advantages that R-FEFETs possess to overcome the drawbacks encountered with gate leakage in standard FEFETs. The hold margins in the nonvolatile mode of R-FEFETs increase by ~ $10\times $ with respect to standard FEFETs, and the drive current strengths in the volatile mode show 13% improvements when compared to standard FETs. Using the proposed R-FEFETs, we examine a low-power nonvolatile memory design in Part II of this paper. [ABSTRACT FROM AUTHOR]

We propose the application of ferroelectric (FE)-based transistors, viz., negative capacitance FET (NCFET) and Hysteretic ferroelectric FET (FEFET) in the design of coupled oscillators. The proposed oscillator utilizes hysteretic inverter voltage transfer characteristics, which is achieved by virtue of: 1) negative output conductance (NOC) in NCFETs and 2) hysteretic transfer characteristics in FEFETs. With the aid of output-to-input feedback in the inverter, we show sustained oscillations which are controllable by the gate voltage of the feedback transistor (${V} _{\mathrm {BIAS}}$). With focus on NCFET-based designs, we show that feedback implementation with pass transistor (PT) and transmission gate (TG) yields relaxation and sinusoid-like characteristics, respectively. Such behavior offers promises for dynamically reconfiguring the oscillator dynamics. We report the fundamental frequency (${f}$) in the range of 12 MHz–800 MHz and 0.7 MHz–417 MHz for TG and PT implementations, respectively. We discuss how this approach can be extended to hysteretic FEFET-based designs. We also analyze coupling between two oscillators considering various strengths of coupling capacitance (${C} _{\mathrm {CP}}$). We establish the conditions for synchronization of ${f}$ between the two oscillators with respect to difference in ${f}$ and ${C} _{\mathrm {CP}}$. [ABSTRACT FROM AUTHOR]