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In this paper, a joint design of sparse code multiple access (SCMA) codebook and peak-to-average power ratio (PAPR) reduction based on the partial transmit sequence (PTS) technique is proposed for the downlink orthogonal frequency division multiplexing (OFDM) scheme. A benchmark scheme is firstly devised based on a direct extension of the conventional PTS-based OFDM scheme. Based on the characteristics of the near-optimal SCMA codebook designs reported in our previous work, a PTS-based SCMA-OFDM design is proposed by carefully determining the rotation angles of the SCMA codebooks, according to the adopted signal sub-constellations. A receiver which does not need the side information is further devised. Considering the phase ambiguity issue of the receiver, the PTS angles have been carefully refined. When compared to both the original scheme that does not consider PAPR reduction techniques and the benchmark scheme, the proposed scheme achieves a significantly enhanced PAPR performance with approximately the same error performance. In addition, a comparable PAPR performance, an improved error performance, and a lower computational complexity can be achieved when compared to the clipping-based SCMA-OFDM scheme reported in the previous literature. [ABSTRACT FROM AUTHOR]

We propose two techniques for the low-density parity-check (LDPC) coded partial response channel with run-length-limited (RLL) constraints. The first is a modification of the selective flipping technique so that side information is not needed. The second is based on the estimation of flipped bits for the selective flipping technique. The second technique can achieve significant performance improvement over the simple selective flipping technique either with side information or without side information. We also incorporate these two techniques into a known technique to design LDPC coded recording systems that can meet strict RLL constraints without performance degradation. Index Terms--Constrained codes, low-density parity-check (LDPC) codes, recording, run-length-limited (RLL) codes.

This letter presents a construction flow for rate-compatible LDPC (RC-LDPC) codes, collaboratively using both extension and splitting schemes. In addition to the decoding threshold used for selecting the degree distribution, a new metric, known as the Average ACE ($A^{2}CE$) value, is introduced in order to estimate the Tanner graph connectivity. The proposed collaborative scheme provides more flexibility in the designs of the degree distribution and graph connectivity, both of which are critical for RC LDPC codes that have short and/or moderate lengths. The designed LDPC codes achieve a comparable or better error rate performance compared to existing codes. [ABSTRACT FROM AUTHOR]

In this letter, three post-processing schemes for cyclic redundancy check (CRC-)aided successive cancellation list (CA-SCL) decoding are presented for polar codes. The re-decoding based on our post-processing schemes can effectively alleviate both the channel and decision errors encountered via CA-SCL decoding. Simulation results show that our schemes perform better than conventional re-decoding schemes and can be incorporated into a polar decoder that has a small list size to achieve a performance that is expected for a large list size. [ABSTRACT FROM AUTHOR]

Among various massive multiple-input multiple-output (MIMO) signal detection schemes, expectation propagation (EP) achieves superior performance in high-dimensional systems with high-order modulations and flexible antenna configurations. However, the inevitable matrix inversion in each iteration of EP brings unbearable computational burden, which hinders the efficient implementation. Several reduced-complexity variants of EP are proposed recently, which effectively alleviate the computational cost but at the expense of unacceptable performance loss. In this paper, a low-complexity massive MIMO detection is first proposed based on approximate EP, which relieves the computational complexity of the exact EP while maintaining the good performance. Particularly, the EP moment matching equations are reformulated to simplify the sequential updating procedure. In addition, an approximation based on the channel-hardening phenomenon is proposed to eliminate the matrix inversion at each iteration. Numerical results show that, for high-dimensional MIMO the proposed detector approaches the exact EP in term of bit-error-rate (BER) by a small number of iterations. No matter with symmetric or asymmetric antenna configuration, it outperforms other EP variants, Gaussian tree approximation, and channel-hardening exploiting message passing. An analysis of computational complexity reveals the high efficiency of the proposed detection compared to the state-of-the-art with flexible antenna configurations. [ABSTRACT FROM AUTHOR]

This letter presents a low-complexity redecoding-based error-floor lowering technique for quasi-cyclic low-density parity-check codes, where a predetermined set of variable nodes are attenuated before the redecoding. Using a two-stage off-line search, the attenuation set is determined based on the error patterns collected from the standard decoding simulation. It is shown that the error floor can be effectively lowered, and only a negligible amount of complexity is introduced. [ABSTRACT FROM AUTHOR]

This paper presents an efficient combined bit-flipping (BF) and stochastic low-density parity-check decoder, where a BF decoder is used to achieve a reduction in decoding cycles. A node-wise probability tracer is adopted at each variable node (VN) in order to achieve a BER performance comparable to the normalized min-sum algorithm, where check-to-variable (C2V) messages are used as inputs, rather than the variable-to-check (V2C) messages adopted in previous stochastic decoders. The complexity of the VN units is greatly reduced by sharing common units used in the generation of V2C messages together with a probability tracer. The C2V-based probability tracer enables the design of a decoder that provides a short critical path. The proposed methods are demonstrated by designing a (2048, 1723) decoder that is implemented in a 90 nm process. A total of 1460 K logic gates are integrated in a decoder that has an area of 4.12 \mboxmm^2 and achieves a coded throughput of 39.3 Gb/s at a clock frequency of 749 MHz. To the best of the authors’ knowledge, the proposed decoder achieves the best normalized throughput-to-area ratio among the stochastic decoders reported in the open literatures. [ABSTRACT FROM AUTHOR]

This paper presents a high-throughput, energy-efficient, and scalable low-density parity-check (LDPC) decoder with time-domain (TD) signal processing. The proposed arbiter-based minimum value finder is able to support practical long codes. The latency for determining the first two minimum values required in the check node unit is significantly reduced through TD processing. A layered Q -based decoding architecture together with the associated scheduling is proposed in order to reduce the amount of memory used for check node storage. Multimode operations are supported by leveraging the structure of the base matrices and the proposed scalable minimum finder architecture. As a proof of concept, a TD-based multimode LDPC decoder for high-speed IEEE 802.15.3c is designed and fabricated in a 90-nm CMOS process. The LDPC decoder integrates 495k logic gates in 2.25 mm2 and achieves a throughput of 5.28 Gb/s at 157 MHz from a 1.05 V supply voltage. The power and normalized energy dissipation are 182 mW and 34.47 pJ/b, respectively. The proposed LDPC decoder is more hardware and energy efficient than previous digital counterparts and is able to support long codes for practical applications, which is still infeasible for the state-of-the-art TD-based LDPC decoders. [ABSTRACT FROM AUTHOR]

This brief presents three strategies, including initialization based on Look Up Table (LUT), postprocessing based on bit flipping and hard decision based on the posterior information, to reduce the number of decoding cycles (DCs) for stochastic low-density parity-check decoding. For the standard IEEE 802.3an code, simulation indicates a 73.6% reduction in the average number of DCs with a satisfactory bit error rate. Moreover, hardware implementation shows that the area required for the proposed decoder is significantly reduced. [ABSTRACT FROM AUTHOR]

Aimed at the emerging massive multiple-input multiple-output (MIMO) systems, both hard-decision and soft-decision detectors are investigated for the generalized space shift keying (GSSK) modulation scheme, where a codebook-assisted technique is used to reduce the tree-search complexity. Furthermore, the outer low-density parity-check (LDPC) code is optimized such that the proposed system design can provide an error performance, which is almost the same as that of the scheme that uses the maximum a posteriori (MAP) soft detector, but with a much lower computational complexity. [ABSTRACT FROM PUBLISHER]

A construction of physical-layer Raptor (PLR) codes based on protographs is proposed. We first set up a sequence of signal-to-noise ratios (SNRs). For each SNR, we employ a modified protograph EXIT analysis to find the extra check nodes in addition to the existing check nodes so as to meet the threshold required by the outer low-density parity check code. PLR codes which are capacity-approaching for a wide SNR range can be obtained using the proposed construction. [ABSTRACT FROM PUBLISHER]

In this paper, we investigate Raptor-coded distributed unitary space–time modulation (USTM) schemes, where both the amplify-and-forward (AF) and decode-and-forward (DF) relaying scenarios are considered, under a wireless relay network with arbitrary path gains for the channel fading coefficients. First, the AF and DF relaying procedures are investigated based on the use of an inner USTM signal and an outer Raptor code, and the related noncoherent detectors are also derived. The constellation search for the USTM signal, as well as the optimization for the Raptor code, is then investigated in order to enhance the system performance. It is shown that the designed systems effectively approach the predicted limit in throughput performances and outperform the noncoherent distributed MIMO scheme reported in the previous literature. [ABSTRACT FROM PUBLISHER]

This paper presents a maximum mutual information increase (M^2I^2)-based algorithm that can be used to arrange low-density parity-check (LDPC) decoding schedules for faster convergence, where the increase is used to guide the arrangement of the fixed decoding schedule. The predicted mutual information for the messages to be updated is used in the calculation of the increase. By looking ahead for several decoding stages, a high-order prediction can be realized, which can then be used to devise a schedule with an even faster convergence. For a single received frame, different decoding results can be obtained using different schedules, and, hence, schedule diversity, that lowers the error floor resultant from the dominant trapping sets, is proposed. By adopting the M^2I^2-based schedule together with the schedule diversity, both the convergence speed in the waterfall region and the error-rate in the floor region can be improved. [ABSTRACT FROM AUTHOR]

In this paper, we investigate differential amplitude/phase modulation (APM) schemes for correlated Rayleigh fading channels. Considering the noncoherent maximum-likelihood receiver, a theoretical pairwise error probability (PEP) formula for differential signal vectors with arbitrary power values is derived. The design criterion for the signal set of differential vectors is then proposed based on the asymptotic analysis of the PEP. For both uncoded and coded APM schemes, the design criteria and optimization procedures for bit labeling rules are investigated. The designed differential APM schemes are shown to provide significant improvement in bit-error-rate performance, particularly in the error-floor regions. [ABSTRACT FROM PUBLISHER]

It is known that low-density parity-check (LDPC) codes are widely used to provide capacity-approaching performances in various transmission systems. However, the Gaussian assumption for soft messages in conventional EXIT (extrinsic information transfer)-chart-based optimization algorithms result in prediction gaps in the decoding threshold for certain transmission systems. In this letter, we propose an EXIT-chart-based optimization method, in which all the Gaussian assumptions for soft messages can be avoided. Compared to the conventional design methods, the proposed method provides a more accurate threshold prediction and can be used to design LDPC-coded schemes with better error performances. [ABSTRACT FROM PUBLISHER]

This paper presents a high-throughput decoder architecture for non-binary low-density parity-check (LDPC) codes, where the q-ary sum-product algorithm (QSPA) in the log domain is considered. We reformulate the check-node processing such that an efficient trellis-based implementation can be used, where forward and backward recursions are involved. In order to increase the decoding throughput, bidirectional forward-backward recursion is used. In addition, layered decoding is adopted to reduce the number of iterations based on a given performance. Finally, a message compression technique is used to reduce the storage requirements and hence the area. Using a 90-nm CMOS process, a 32-ary (837,726) LDPC decoder was implemented to demonstrate the proposed techniques and architecture. This decoder can achieve a throughput of 233.53 Mb/s at a clock frequency of 250 MHz based on the post-layout results. Compared to the decoders presented in previous literature, the proposed decoder can achieve the highest throughput based on a similar/better error-rate performance. [ABSTRACT FROM PUBLISHER]

When residual belief-propagation (RBP), which is a kind of informed dynamic scheduling (IDS), is applied to low-density parity-check (LDPC) codes, the convergence speed in error-rate performance can be significantly improved. However, the RBP decoders presented in previous literature suffer from poor convergence error-rate performance due to the two phenomena explored in this paper. The first is the greedy-group phenomenon, which results in a small part of the decoding graph occupying most of the decoding resources. By limiting the number of updates for each edge message in the decoding graph, the proposed Quota-based RBP (Q-RBP) schedule can reduce the probability of greedy groups forming. The other phenomenon is the silent-variable-nodes issue, which is a condition where some variable nodes have no chance of contributing their intrinsic messages to the decoding process. As a result, we propose the Silent-Variable-Node-Free RBP (SVNF-RBP) schedule, which can force all variable nodes to contribute their intrinsic messages to the decoding process equally. Both the Q-RBP and the SVNF-RBP provide appealing convergence speed and convergence error-rate performance compared to previous IDS decoders for both dedicated and punctured LDPC codes. [ABSTRACT FROM AUTHOR]

In this paper, we investigate noncoherent transmission schemes using amplitude/phase modulation. For uncoded transmission schemes, we derive the pairwise error probability (PEP) and its high-SNR approximation for signal vectors with unequal power values using a noncoherent maximum-likelihood detector under Rayleigh block fading channels. For coded transmission schemes, we consider differential amplitude/phase modulated signals and introduce a codeword-interleaving strategy to improve the error performance. The design criteria for the signal labelling and bit interleaving are also derived via the high-SNR approximation of the PEP. At the receiver, we devise an iterative channel amplitude estimator to enhance the detection reliability. With the help of a specially-designed iterative receiving algorithm, the designed noncoherent coded scheme can provide a significant improvement, either in the error-floor or the waterfall region. [ABSTRACT FROM PUBLISHER]

In this paper, a low-density parity-check (LDPC) coded recording system is investigated, for which the run-length-limited (RLL) constraint is satisfied by deliberate flipping at the write side and by estimating the flipped bits at the read side. Two approaches are proposed for enhancing the error performance of such a system. The first approach is to alleviate the negative effect of incorrect estimation of the flipped bits by adjusting the soft information. The second approach is to increase the likelihood of the correct detection of flipped bits by designing a flipped-bit detection algorithm that utilizes both the RLL constraint and the parity-check constraint of the LDPC code. These two approaches can be combined to obtain significant improvement in performance over previously proposed methods. [ABSTRACT FROM AUTHOR]

Presents information on a study which proposed two trellis coding schemes with large free distances. Review of the proposed trellis coding schemes using delay processor and signal mapper; Performance evaluation; Conclusions.