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In this study, we comprehensively investigate the constant voltage stress (CVS) time-dependent breakdown and cycle-to-breakdown while considering metal-ferroelectric-metal (MFM) memory, which has distinct domain sizes induced by different doping species, i.e., Yttrium (Y) (Sample A) and Silicon (Si) (Sample B). Firstly, Y-doped and Si-doped HfO2 MFM devices exhibit domain sizes of 5.64 nm and 12.47 nm, respectively. Secondly, Si-doped HfO2 MFM devices (Sample B) have better CVS time-dependent breakdown and cycle-to-breakdown stability than Y-doped HfO2 MFM devices (Sample A). Therefore, a larger domain size showing higher extrapolated voltage under CVS time-dependent breakdown and cycle-to-breakdown evaluations was observed, indicating that the domain size crucially impacts the stability of MFM memory. [ABSTRACT FROM AUTHOR]

This letter proposes a memory cell, denoted by 1F-1 T, consisting of a ferroelectric field-effect transistor (FeFET) cascaded with another current-limiting transistor (T). The transistor reduces the impact of drain current ($I_{d}$) variations by limiting the on-state current in FeFET. The experimental data from our 28 nm high-k-metal-gate (HKMG) based FeFET calibrates and simulates the memory arrays. The simulation indicates a significant improvement in bit-line (BL) current ($I_{BL}$) variation and the accuracy of vector-matrix multiplication of the 1F-1 T memory array. The system-level in-memory computing simulation with 1F-1T synapses shows an inference accuracy of 97.6% for the MNIST hand-written digits with multi-layer perceptron (MLP) neural networks. [ABSTRACT FROM AUTHOR]

Harnessing multibit precision in nonvolatile memory (NVM)‐based synaptic core can accelerate multiply and accumulate (MAC) operation of deep neural network (DNN). However, NVM‐based synaptic cores suffer from the trade‐off between bit density and performance. The undesired performance degradation with scaling, limited bit precision, and asymmetry associated with weight update poses a severe bottleneck in realizing a high‐density synaptic core. Herein, 1) evaluation of novel differential mode ferroelectric field‐effect transistor (DM‐FeFET) bitcell on a crossbar array of 4 K devices; 2) validation of weighted sum operation on 28 nm DM‐FeFET crossbar array; 3) bit density of 223Mb mm−2, which is ≈2× improvement compared to conventional FeFET array; 4) 196 TOPS/W energy efficiency for VGG‐8 network; and 5) superior bit error rate (BER) resilience showing ≈94% training and 88% inference accuracy with 1% BER are demonstrated. [ABSTRACT FROM AUTHOR]

In this work, we demonstrated Ga2O3-based power MOSFETs grown on c-plane sapphire substrates using in-situ TEOS doping for the first time. The β-Ga2O3:Si epitaxial layers were formed by the metalorganic chemical vapor deposition (MOCVD) with a TEOS as a dopant source. The depletion-mode Ga2O3 power MOSFETs are fabricated and characterized, showing the increase of the current, transconductance, and breakdown voltage at 150 °C. In addition, the sample with the TEOS flow rate of 20 sccm exhibited a breakdown voltage of more than 400 V at RT and 150 °C, indicating that the in-situ Si doping by TEOS in MOCVD is a promising method for Ga2O3 power MOSFETs. [ABSTRACT FROM AUTHOR]

In this study, AlGaN/GaN light-emitting HEMTs (LE-HEMT) with a single quantum well inserted in different locations in the epitaxy layers are fabricated and analyzed. For both structures, light-emitting originated from electrons in the 2DEG and holes from the p-GaN for radiative recombination is located in the quantum well. To investigate the importance of the location of single quantum well, optical characteristics are compared by simulation and experimental results. The experimental results show that the main light-emitting wavelength is shifted from 365 nm in the UV range to 525 nm in the visible range when the radiative recombination is confined in the quantum well and dominates among other mechanisms. Epi B, which has a quantum well above the AlGaN barrier layer in contrast to Epi A which has a quantum well underneath the barrier, shows better intensity and uniformity in light-emitting. According to the simulation results showing the radiative distribution and electron concentrations for both structures, the lower quantum efficiency is due to the diverse current paths in Epi A. On the other hand, Epi B shows better quantum confinement and therefore better luminescence in the same bias condition, which is consistent with experimental observations. These findings are critical for advancing the performance of LE-HEMTs. [ABSTRACT FROM AUTHOR]

Gallium nitride high electron mobility transistors outperform Silicon devices due to their excellent physical properties. However, being an immature technology, it exhibits dynamic on-state resistance ($R_{\text{ds}, \text{on}}$). This causes increased conduction loss and leads to reduced operating efficiency. To evaluate the dynamic $R_{\text{ds}, \text{on}}$ of the device, a measurement circuit is required. In literature, a standardized double pulse test is widely used for the measurement of $R_{\text{ds}, \text{on}}$. However, due to the uncontrolled off-state time and inability to independently adjust, the test conditions result in restricted measurement. This article proposes a measurement circuit of the device in power electronics operations. The circuit uses an H-Bridge-derived topology with capacitive storage to enable forward and reverse conduction mode measurement of the device. In all the modes, the circuit allows measurement from the first switching cycle and independent control over the testing conditions by using a hysteresis current control. The proposed measurement circuit is validated using simulation and experimentation. Finally, analytical efficiency compared with the state-of-the-art measurement circuits is provided. [ABSTRACT FROM AUTHOR]

In this work, we report that the VTH stability in p-GaN power HEMTs under a high dVg/dt event is highly correlated with the capacitance for the first time. The different dVg/dt event is performed by using fast sweep characterization with sweeping time (tsweep) varied from 10ms to $25~\mu \text{s}$. As the tsweep is decreased, i.e., high dVg/dt, p-GaN HEMTs show a negative VTH shift and a high measured gate current. The higher measured gate current is mainly due to the displacement current with respect to a high dVg/dt. To further understand the impacts of capacitance on VTH stability, p-GaN power HEMTs are connected with different additional capacitance (Cadditional) between gate-to-source terminals. The results indicate that the negative VTH shift and the gate current are highly correlated with the Cadditional, i.e., a large negative VTH shift and a high measured gate current in the device with a large Cadditional, suggesting that the charging capacitance caused by the displacement current during a high dVg/dt event can influence the VTHstability. Therefore, the optimization of the capacitance is crucial to improve the VTH stability during a high-speed gate operation. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate enhancement-mode regrown p-GaN gate devices with high threshold voltage as well as a robust forward time-dependent gate breakdown (TDGB) stability. The regrown p-GaN gate HEMTs are fabricated with two different AlGaN barriers. Devices with 16nm Al0.235 Ga0.765 N yield a $\text{V}_{\text {TH}}$ of 1.5V and a high threshold voltage ($\text{V}_{\text {TH}}$) of 2.7V is observed for 7nm AlGaN along with a gate breakdown voltage of more than 10V. Lastly, the regrown p-GaN gate HEMTs with 7nm AlGaN barrier demonstrate an operating $\text{V}_{\text {G}}$ of 7.46V and 7V for 1% failure rate of 10-year lifetime at 150°C and 25°C, which is amongst the highest values compared to the reported literature for regrown p-GaN gate HEMTs. [ABSTRACT FROM AUTHOR]

This work demonstrates a trench isolated lateral double-implanted MOSFET (LDMOS) on Si-face in 4H-silicon carbide (SiC). A device $\vphantom {_{\int _{}}}$ where ${L}_{\textit {ch}} = 0.8\,\,\mu \text{m}$ and ${L}_{d} = 12\,\,\mu \text{m}$ shows an ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 22.9 $\text{m}\Omega $ cm2 at a ${V}_{\text {GS}}$ of 20 V and a breakdown voltage (BV) of 1100 V, corresponding to a high BV2/ ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 55.5 MW/cm2. Devices that have different ${L}_{\text {ch}}$ , ${L}_{\text {JFET}}$ , ${L}_{d}$ , and P-top dose values are measured in order to investigate the effects of geometry on the static performance. Operations at 150 °C are measured to evaluate the temperature performance. Gate charge waveforms are also measured in order to include the switching performance in the evaluation. The ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{G}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\text {GD}}$ values are calculated as 17.7 and $9.0~\Omega $ nC, respectively, which are promising for power-integrated circuit applications. [ABSTRACT FROM AUTHOR]

In this article, a physics-based analytical model which considers the channel charge (Qch) for enhancement-mode p-GaN power high-electron-mobility transistors (HEMTs) is developed. First, by considering the same dynamic channel charge (dQch) for the Schottky/p-GaN junction capacitance (Cj,Sch) and the p-i-n-junction capacitance (Cp-i-n), due to the p-GaN/AlGaN junction and two-dimensional electron gas (2DEG) charge, the analytical formula to calculate the voltage drop in the p-GaN layer (VpGaN) is presented. Second, by implementing the analytical formulae in the advanced SPICE model (ASM) GaN model, the proposed physics-based model reliably fits the measured C – V and I – D – V – G characteristics of the samples under different processing conditions. This provides significant insight regarding the Mg concentration, the voltage drop at the Schottky metal/p-GaN junction (Vj,Sch), and the voltage drop at the p-GaN/AlGaN junction (Vp-i-n). Finally, the I – D – V – G and I – D – V – D characteristics of enhancement-mode p-GaN power HEMTs are modeled, displaying good agreement with the experimental data. [ABSTRACT FROM AUTHOR]

In this letter, a fully transparent AlGaN/GaN HEMT (FT-HEMT) using indium-tin-oxide (ITO) as a transparent electrode is fabricated. The n-ohmic contacts are formed based on a Si-implant process using a deposited ITO rather than the conventional alloyed metal stacks. Following a post-annealing process at 600°C, the field-effect mobility and the maximum current density for an FT-HEMT were 1004 cm2/ $\text{V}{\cdot }\text{s}$ and 179 mA/mm, respectively. Furthermore, the measured transmittance for a fabricated chip in the visible range of 400 - 700 nm was greater than 70%, which is almost the same as an as-grown GaN-on-sapphire substrate. These results show that, by using this approach, an FT-HEMT that has superior electronic properties, such as high mobility and high output current, can be realized, and show great promise for applications in transparent and/or flexible electronics, as well as other optoelectronic devices. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate the use of a machine learning (ML)-based statistical approach to model and analyze the impact of the fabrication processes on the threshold voltage in recessed gate AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors. First, we employ a ML-based Tikhonov regularization approach using the input of 19 different processing splits to generate a multivariable analytical equation that considers four critical processing parameters, such as the remaining AlGaN depth, ex-situ wet clean, in-situ plasma, and gate dielectric. Furthermore, the artificial neural network-based approach, which cannot be used to further analyze the impact of the process, is implemented for the comparison. Second, the results from this analytical equation show a nice agreement with the measured threshold voltage, indicating a successful correlation between the processing parameters and the threshold voltage. Finally, the impact of each process on the threshold voltage can be analyzed through the coefficient value related to each process, which can be a useful guidance for the device optimization toward the targeted performance. [ABSTRACT FROM AUTHOR]

III-V heterostructure based high electron mobility transistors (HEMTs) offer superior performance as compared to CMOS silicon transistors owing to the high mobility in the 2D electron gas (2DEG) channel at the heterostructure interface. Gallium nitride (GaN) based HEMTs are also suitable for high power and high temperature applications. GaN has a rich offering of material properties spanning domains of non-linear optics, piezoelectric micro-electro-mechanical systems, and monolithic microwave integrated circuits. In this paper, we propose HEMT inspired III-V electro-optic modulator topologies and study the light interaction with 2DEG in such structures. We analyze the electroabsorption and electrorefraction on account of the 2DEG interaction with light and present a design framework to selectively leverage the desired mechanism of modulation. Our analysis suggests that modulation index of electrorefractive modulation in a HEMT-like structure is comparable to silicon photonic modulators. By leveraging the higher electron mobility in these material platforms, the device concepts proposed here could potentially be used to design electro-optic modulators with extremely high modulation rates. [ABSTRACT FROM AUTHOR]

This article reports that the enhanced forward gate bias time-dependent dielectric breakdown (TDDB) reliability and interface quality are achieved in 5-nm ferroelectric Hf0.5Zr0.5O2 (HZO) technologies by using the NH3 plasma interfacial layer (IL) treatment and microwave annealing (MWA). An orthorhombic crystalline phase is observed in the annealed HZO film with NH3 plasma IL treatment and MWA, and NH3 plasma IL treatment can suppress Hf/Zr interdiffusion. Metal-oxide-semiconductor capacitors (MOSCAPs) subjected to NH3 plasma IL treatment and 2100-W MWA also have a higher extrapolated operating voltage for a ten-year lifetime at 0.01% failure and lower interface state density (Dit) compared to the devices subjected to only rapid thermal annealing (RTA) at 600 °C. Therefore, NH3 plasma treatment and MWA are effective for improving the TDDB reliability and interface quality of the ultrathin ferroelectric HZO. [ABSTRACT FROM AUTHOR]

In this article, we demonstrate that a physics-based compact model can facilitate to analyze the reliability using an example of γ-ray induced instability in AlGaN/GaN HEMTs. First, the typical AlGaN/GaN HEMTs are subjected to the cumulative γ-ray irradiation, exhibiting the drain current (ID) increase. In order to further elucidation, the root cause, the compact model is implemented and calibrated with the pristine case. Then, ID – VG and ID – VD characteristics subjected to the γ-ray irradiation are fitted with the compact model. The extracted μ and Rc are consistent with the results obtained by the Hall measurement and circular transmission line measurement (C-TLM). By comparing the fitted curves with considering: 1) fitted μ (Rc is fixed as the pristine case) and 2) fitted Rc (μ is fixed as the pristine case), the shift of μ is identified as the root cause leading to the ID increase because of the better fitting results. Therefore, with the assistance of the physics-based compact model, the shift of the parameter can be further analyzed to understand the origin of the instability. [ABSTRACT FROM AUTHOR]

In this letter, we investigate annealing effects in ferroelectric HfZrOx dielectric in metal–insulator–metal devices and metal–oxide–semiconductor capacitors by comparing two annealing methods: rapid thermal annealing (RTA) and microwave annealing (MWA). The tradeoff characteristics between the annealing conditions, polarization–electric field characteristics, gate leakage current, and interface state density (${D} _{\textsf {it}}$) are discussed. We show that: 1) a positive correlation between the remanent polarization (Pr), the gate leakage current, and ${D}_{\textsf {it}}$ as the annealing temperature (RTA) and the annealing power (MWA) increase and 2) the MWA is promising for ferroelectric transistors technology, since its low thermal budget can minimize ${D}_{\textsf {it}}$ and avoid increase in the gate leakage current. [ABSTRACT FROM AUTHOR]

In this letter, we analyzed the gate capacitance characteristics in p-GaN gate/AlGaN/GaN heterostructures by using a two-junction capacitor model. First, we have observed that the C – V behavior depends on the different processing conditions of the p-GaN gate. Second, a two-junction capacitor model considering a series connection of the Schottky metal/p-GaN junction capacitor and the AlGaN barrier capacitor is proposed to explain this C – V behavior. Based on this model, the junction capacitance has an influence on the total capacitance value under a high gate bias due to the Schottky metal/p-GaN junction. Furthermore, the Mg-concentration and hole density can be extracted. The extracted hole density is consistent with the results obtained by Hall measurements. [ABSTRACT FROM AUTHOR]

In this paper, fully recessed-gate GaN MISFETs with two different gate dielectrics, i.e., plasma-enhanced atomic layer deposition (PEALD) SiN and ALD Al2O3 gate dielectric, are used to study the origin of positive bias temperature instability (PBTI). By employing a set of dedicated stress-recovery tests, we study PBTI during the stress and relaxation. Hence, a defect band model with different distributions of defect levels inside the gate dielectric is proposed, which can excellently reproduce the experimental data and provide insightful information about the origin of PBTI in GaN MISFETs. The results indicate that the serious PBTI in the device with PEALD SiN is mainly due to a wide distribution of defect levels ( \sigma \sim 0.67 eV), centered below the conduction band of GaN ( E_{C} -0.05 eV), and can be easily accessed by the channel carriers already at a low-gate voltage. On the other hand, ALD Al2O3 gate dielectric shows a narrower distribution of defects ( \sigma \sim 0.42$ eV), which are far from the conduction band of GaN ( E_{C} +1.15 eV). This observations explain the improved PBTI reliability observed in devices with ALD Al2O3. [ABSTRACT FROM AUTHOR]

This letter reports an in-depth study of the negative threshold voltage instability in GaN-on-Si metal-insulator–semiconductor high electron mobility transistors with partially recessed AlGaN. Based on a set of stress/recovery experiments carried out at several temperatures, we demonstrate that: 1) operation at high temperatures and negative gate bias (−10 V) may induce a significant negative threshold voltage shift, that is well correlated to a decrease in on-resistance; 2) this process has time constants in the range between 10–100 s, and is accelerated by temperature, with activation energy equal to 0.37 eV; and 3) the shift in threshold voltage is recoverable, with logarithmic kinetics. The negative shift in threshold voltage is ascribed to the depletion of trap states located at the SiN/AlGaN interface and/or in the gate insulator. [ABSTRACT FROM PUBLISHER]

In this work we report on the three dominant trapping mechanisms affecting the dynamic performance of a double-heterostructure GaN-based MIS-HEMT grown on silicon substrate. In the OFF-state, with high drain voltage and pinched-off 2DEG, the dominant mechanism is the charge-trapping in the gate-drain access region caused by the transversal drain-to-substrate potential. This effect causes the dynamic increase of the ON-resistance, and is positively temperature-dependent, thus of great concern for high-temperature operation. In the SEMI-ON-state, due to the presence of high VDS and relatively high IDS, an additional trapping mechanism emerges, involving the injection of hot electrons from the 2DEG into trap states located in the GaN-buffer or in the AlGaN barrier. This mechanism, critical in hard-switching operations, affects both the ON-resistance and the VTH. Finally, when the gate is positively biased (gate overdrive state) trapping of electrons happens in the gate dielectric layer(s), leading to strong metastable VTH instabilities. [ABSTRACT FROM AUTHOR]

The reliability of Au-free Ohmic contacts has been evaluated under a constant current stress (500 mA/mm) in a high temperature environment (150 °C, 175 °C, and 200 °C). Two Ohmic contact schemes with different Ti/Al thicknesses (5 nm/100 nm and 10 nm/100 nm) have been tested. The results showed that the degradation of the resistance ( R increase ) is accelerated at a higher temperature condition. Moreover, R increase has a square root dependence with the time. This indicates that a diffusion process could be responsible for the observed degradation. This has been confirmed by means of physical failure analyses (FIB/TEM) performed on a highly degraded device: an apparent roughness of the interface between TiN and the Ohmic metal layer was observed. On top of this, Nitrogen out-diffusion into the Ohmic metal was observed in the EDS/EELS analyses, suggesting that a material diffusion phenomenon might play a role. In addition, we observed that the devices with a lower initial contact resistance ( R c ) showed lower degradation with respect to devices with a larger initial R c . This suggests that obtaining lower R c is beneficial not only for the performance but also for the reliability. [ABSTRACT FROM AUTHOR]

This letter demonstrates that GaN-based MIS-HEMTs submitted to stress with high-temperature, high drain bias, and constant source current (HTSC stress) may show degradation modes that are not detectable during standard high temperature reverse bias (HTRB) stress. Based on a number of stress/recovery experiments, we demonstrate the following novel results: 1) the combined presence of high drain bias and constant drain–source current (HTSC stress) can lead to a significant increase in ON-resistance ( R\mathrm{\scriptscriptstyle ON} ) that is not detected under conventional HTRB stress; 2) R\mathrm{\scriptscriptstyle ON} increases without changes in the threshold voltage, indicating that charge trapping takes place in the access regions, and not under the gate; 3) the R\mathrm{\scriptscriptstyle ON} increase has a monotonic dependence on the source current flowing during stress; and 4) for the same stress current level, the R\mathrm{\scriptscriptstyle ON} increase has a negative dependence on temperature. The strong correlation between R\mathrm{\scriptscriptstyle ON} increase and source current and the negative temperature coefficient strongly support the hypothesis that trapping originates from the injection of hot electrons toward the gate–drain access region. [ABSTRACT FROM PUBLISHER]