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Advanced front-end readout chips for medium and high energy nuclear physics experiments have shown an increasing trend towards digitization in recent years, increasing system integration and reducing power consumption. Guided by critical scientific goals, the Institute of Modern Physics of the Chinese Academy of Sciences is building a central scientific installation termed as the high intensity heavy-ion accelerator facility (HIAF). HIAF fragment separator (HFRS) is an important experimental device for radioactive beam physics research on the HIAF. The characteristics of HFRS strong current and the readout demand of the large area detectors put forward the requirements of high-count rate, high integration, and high time resolution for the front-end readout electronics, and therefore the development of the advanced digital front-end readout chip is urgently needed. The paper developed a high-count rate multi-channel time measurement and serial readout circuit (HMTRC) based on 180 nm complementary metal oxide semiconductor (CMOS) process, which can accelerate the development and iteration of such digital front-end readout chips. The HMTRC has now been integrated into a self-developed 16 channel digital-analogue hybrid front-end readout chip, EDIMS, for position sensitive detectors on HFRS. When a charge signal is input, the charge-sensitive amplifier (CSA) integrates the signal into an exponentially decaying voltage signal and fans out to the time path and the energy path. In the time path, the fast shaper inputs the output signal of the CSA into the discriminator after shaping, and outputs the self-triggering signal after comparing with the threshold. The digital first input first output (FIFO) memory in each channel records information such as the timestamp and channel number corresponding to the front time of the trigger signal. In the energy path, the slow shaper integrates the output signal of the CSA into a quasi-Gaussian signal. The output signal of the peak detect and hold circuit (PDH) follows the leading edge of the output signal of the slow shaper to detect and maintain peak energy information. The analog memory based on switched-capacitor arrays stores the information. The polling readout module based on the token ring logic reads out the stored charge and time information periodically and synchronously, which has advantages in the de-sparsification and de-randomization of nuclear events and the improvement of peak count rate. The chip has been fabricated and the HMTRC has a size of 535 μm×930 μm and a power consumption of 32.31 mW. The laboratory test system consists of a chip test board, a XILINX Kintex-7 development board, a host computer, a signal generator and an oscilloscope. The field programmable gate array (FPGA) on the development board provides the master clock and control signals for the chip under test. The output data from the chip are transferred to the development board by a high-speed connector, packaged by cache processing and uploaded to the host computer via the integrated logic analyzer for analysis. The test results show that the function of the HMTRC and the coarse time of the timestamps are in line with expectations, but the fine time of timestamp between each channel is different, and there is some error compared with the theoretical value. The test results also show that the accuracy of time resolution is better than 2 ns, which is as expected, and basically meets the requirements of the application. The next version of the design will optimize the inconsistency between the channels and fine time error of the timestamp, and add the inter-integrated circuit (I2C) or the serial peripheral interface (SPI) slow control module to improve the versatility of this circuit.

To search for dark matter candidates with masses below O (MeV), the SPLENDOR (Search for Particles of Light dark mattEr with Narrow-gap semiconDuctORs) experiment is developing novel narrow-bandgap semiconductors with electronic bandgaps on the order of 1–100 meV. In order to detect the charge signal produced by scattering or absorption events, SPLENDOR has designed a two-stage cryogenic HEMT-based amplifier with an estimated charge resolution approaching the single-electron level. A low-capacitance (∼ 1.6 pF) HEMT is used as a buffer stage at T = 10 mK to mitigate effects of stray capacitance at the input. The buffered signal is then amplified by a higher-capacitance (∼ 200 pF) HEMT amplifier stage at T = 4 K. Importantly, the design of this amplifier makes it usable with any insulating material—allowing for rapid prototyping of a variety of novel detector materials. We present the two-stage cryogenic amplifier design, preliminary voltage noise performance, and estimated charge resolution of 7.2 electrons. [ABSTRACT FROM AUTHOR]

Owing to a change in the scope of physics research, the AMBER spectrometer at CERN is undergoing an update on its instrumentation and trigger strategy for the data acquisition system. One of the key updates is the adoption of a free-running and trigger-less operation, which differs from the predecessor of AMBER, COMPASS, by working in a continuous mode but in an event-based triggered way. In this article, we present a multichannel data-acquisition platform developed in line with the next generation of trigger-less and free-running data acquisition systems. The platform is based on a pre-existing Mezzanine Sampling ADC board for the analog-to-digital conversion and a Xilinx Zynq Ultrascale+ System on Module for online real-time data processing. We also present the evaluation of the system operating in continuous mode, taking data from a 25-element electromagnetic calorimeter prototype with a muon beam, during the first AMBER pilot run. The acquired data were used for noise and pulse shape studies required for the design of the algorithms for lossless compression and data feature extraction needed for trigger-less operation. [ABSTRACT FROM AUTHOR]

We present the measured baseline ionization resolution of a HEMT-based cryogenic charge amplifier coupled to a CDMS-II detector. The amplifier has been developed to allow massive semiconductor dark matter detectors to retain background discrimination at the low recoil energies produced by low-mass WIMPs. We find a calibrated baseline ionization resolution of σ E = 91 eV e e. To our knowledge, this is the best direct ionization resolution achieved with such massive (≈ 150 pF capacitance) radiation detectors. [ABSTRACT FROM AUTHOR]

Abstract The LAB4D is a new application-specific integrated circuit (ASIC) of the Large Analog Bandwidth Recorder and Digitizer with Ordered Readout (LABRADOR) family, for use in direct wideband radio frequency digitization such as is used in ultrahigh energy neutrino and cosmic ray astrophysics. The LAB4D is a single channel switched-capacitor array (SCA) 12-bit sampler with integrated analog-to-digital converters (ADC), developed in the TSMC 0.25 µm process. The LAB4D, operating at 3. 2 GSa ∕ s , contains 4096 total samples arranged in 32 windows, for a total record length of 1280 ns. The 3 dB bandwidth is approximately 1.3 GHz, with a directly-coupled 50 Ω input. This represents a factor of 16 increase in the sample depth and an increase in analog bandwidth in comparison to the previous generation (LAB3) digitizer. Individually addressable windows allow for sampling and digitization to occur simultaneously, leading to nearly dead time-free kHz readout rates. All biases and current references are generated via internal digital-to-analog converters (DACs), resulting in a digitizer that requires minimal support circuitry. In addition, the LAB4D contains sample cell timebase trimming capabilities, reducing the intrinsic sample-to-sample time variance to less than 5 ps, an improvement of about 80%. This feature allows the LAB4D to be used in precision timing applications and reduces post-hoc calibration requirements. [ABSTRACT FROM AUTHOR]

Abstract The Thin-TOF PET (TT-PET) project aims at the construction of a small-animal PET scanner based on silicon monolithic pixel sensors with 30 ps time resolution for 511 keV photons, equivalent to 100 ps time resolution for minimum ionizing particles. The high time resolution of the pixel sensor allows for precise time of flight measurement of the two photons and a significant improvement in the signal-to-noise ratio of images. The TT-PET scanner also has sensitivity for photon depth of interaction, thus improving the spatial resolution across the whole view of the scanner. The performance of the scanner estimated by a GEANT4 Monte Carlo simulation is presented. In order to achieve the high time resolution, the SiGe heterojunction bipolar transistor technology (SG13S from IHP) was chosen for fast integration, low equivalent noise charge and low power consumption. TCAD simulations were used to design the appropriate guard rings for the pixel sensor. Laboratory measurements of the first test chip show the correct functionality of the guard ring up to a bias potential of 200 V applied to the pixels and a good signal-to-noise ratio for the detection of electrons from a 90Sr source. A test beam measurement with an un-thinned chip shows more than 99 % efficiency and approximately 200 ps time resolution for minimum ionizing particles despite the absence of wafer thinning and post-processing. Highlights • The Thin-TOF PET (TT-PET) project aims at the construction of a TOF PET scanner. • The robustness of the first prototype against breakdown up to a potential 160 V. • First prototype shows a time resolution of 200 ps for MIPs under a test beam. [ABSTRACT FROM AUTHOR]

Abstract Array optical transceiver provides high speed data transmission with low mass fibers for detector readout in collider experiments. The module assembly in miniature form factor is favorable for compactness in applications. We report on investigation for components and chip-on-board assembly of an array transmitter with an optical interface of about 2 mm in height suitable for 10+ Gbps/ch data transmission in a radiation hazard environment. The active opto-electronics of 850 nm GaAs VCSELs are investigated for ageing in burn-in at 85°C, 85% RH condition. A radiation-tolerant laser driver is developed in 65 nm CMOS technology. The module assembly includes the VCSEL aligned to optical path component for light coupling to multi-mode fibers. The tolerance of optical path component in radiation is tested in Co60 gamma-ray of up to 300 kGy. The light coupling efficiency is examined for VCSEL emission modes in far-field distributions. [ABSTRACT FROM AUTHOR]

Abstract A serializer ASIC and a VCSEL driver ASIC are needed for the ATLAS liquid argon calorimeter readout phase-I upgrade. The baseline ASICs are the serializer LOCx2 and the VCSEL driver LOCld, designed in a 0.25- μ m Silicon-on-Sapphire (SoS) CMOS technology. Based on a 130-nm CMOS technology, we design two pin-to-pin-compatible backup ASICs, LOCx2-130 and LOCld-130. Their power consumptions are much lower then their counterparts. We present the design of LOCx2-130 and LOCld-130. The test results of LOCx2-130 are also presented. Highlights • We present a serializer ASIC, LOCx2-130, and a VCSEL driver ASIC, LOCld-130, for the ATLAS Liquid Argon Calorimeter trigger upgrade. • LOCx2-130 consists of two serializer channels and each channel encodes ADC data and transmits serial data at 4.8 Gbps with a latency of less than 40.7 ns. The power consumption of LOCx2-130 is about 440 mW. • LOCld-130 is a dual-channel VCSEL driver ASIC and each channel works up to 5.12 Gbps. The total power consumption of LOCld-130 is 112 mW (56 mW/channel) including the VCSELs. • Both chips meet the requirements of the ATLAS Liquid Argon Calorimeter trigger upgrade and the power consumptions are much lower than the previous version. [ABSTRACT FROM AUTHOR]

XIDer is a 2D pixelated hybrid X-ray detector that is supposed to act as a multi-purpose platform for diffraction experiments at fourth-generation high-energy synchrotron light sources like the Extremely Brilliant Source of the European Synchrotron Radiation Facility (ESRF-EBS). As such it needs to tackle a wide variety of requirements. These include x-ray energies of 30 keV to 100 keV imposing the utilisation of high-Z sensors, a wide dynamic range from single photons to fluxes of 1 × 109 photons pixel−1 s−1 and expected raw data rates up to the order of TB s−1 in the final detector design. As a result, XIDer's readout ASIC has to provide smart and flexible ways for on-chip data pre-processing to reduce the output data rate to manageable sizes. This article focusses on introducing the ASIC's novel and unique data-handling concepts like the custom-designed telegram protocol followed by the presentation of exemplary configurations and use cases. [ABSTRACT FROM AUTHOR]

Abstract In this paper we present the Data Processor (DP) and the flight software of the EUSO-SPB1 mission. The EUSO-SPB1 experiment is a pathfinder mission of the EUSO program whose main objective is to detect Ultra-High Energy Cosmic Rays (UHECR) by measuring, for the first time from space, the fluorescence and the Cerenkov Ultra-Violet light produced by Extensive Air Shower. The instrument is a small telescope mounted on an unpressurized gondola of a super pressure balloon. Since a super pressure balloon could remain airborne up to 100 days, the requirements on the electronics and data handling are quite severe. The DP is the component of the electronics system performing the data handling, the monitoring, and the control of the instrument from ground through the interface with the telemetry system. EUSO-SPB1 was launched from Wanaka Airport (New Zealand) on the 24th of April 2017, at 22:51 UTC and the flight lasted for 12 days. [ABSTRACT FROM AUTHOR]

Abstract New physics experiments at the Facility for Antiproton and Ion Research (FAIR) in Darmstadt require application-optimized detector readout circuits. The STS/MUCH-XYTER2 (or SMX2) is a new, 128-channel prototype ASIC for silicon strip detectors and gas electron multiplier (GEM) detectors in the Compressed Baryonic Matter (CBM) experiment. It provides self-triggered amplitude and time measurement of incoming charge and serial streaming of digitized data. The 10 mm × 6.75 mm chip was fabricated employing the UMC CMOS 180 nm process. It comprises of an analog front-end with dual-path processing including a timing comparator in one path and a continuous-time 5-bit analog-to-digital converter in the other path, a digital back-end with time pre-sorting, advanced monitoring and throttling features and multiple 320 Mbps, serial links targeted for a GBT-based data acquisition structure. Specific conditions of the detector systems will be discussed prior to the structure and the features of the ASIC together with measurement results. [ABSTRACT FROM AUTHOR]

Vertex detectors provide space–time coordinates for the traversing charged particle decay products closest to the interaction point. Resolving these increasingly intense particle fluences at high luminosity particle colliders, such as SuperKEKB, is an ever growing challenge. This results in a non-negligible occupancy of the vertex detector using existing low material budget techniques. Consequently, new approaches are being studied that meet the vertexing requirements while lowering the occupancy. In this paper, we introduce a novel vertex detector architecture. Its design relies on an asynchronous digital pixel matrix in combination with a readout based on high precision time-of-flight measurement. Denoted the Timing Vertex Detector (TVD), it consists of a binary pixel array, a transmission line for signal collection, and a readout ASIC. The TVD aims to have a spatial resolution comparable to the existing Belle2 vertex detector. At the same time it offers a reduced occupancy by a factor of ten while decreasing the channel count by almost three orders of magnitude. Consequently, reducing the event size from about 1 MB/event to about 5.9 kB/event. [ABSTRACT FROM AUTHOR]

In this article, an encoder Application Specific Integrated Circuit (ASIC) for high-speed serial data transmission is presented. The ASIC implements a low-latency and low-overhead line code and is fabricated with a commercial 0.25-µm Silicon-on-Sapphire CMOS technology. The ASIC operates at 640 MHz with a latency of no greater than 6.25 ns and the overhead of 14.3%. The encoder will be integrated with a serialiser and will be used in the A Toroidal LHC ApparatuS Liquid Argon (LAr) calorimeter Phase-I trigger upgrade. [ABSTRACT FROM PUBLISHER]

We present the development of an automated testing system for the VMM hybrid of the RD51 collaboration. The VMM hybrid is a new front-end board for the RD51 common readout system, the Scalable Readout System, and will become the workhorse for the next decade to read out Micro-Pattern Gaseous Detectors. It uses the VMM chip developed for the ATLAS New Small Wheel to convert charge signals from detectors to digital data. Our testing system automatically characterises the quality of the VMM chips on the hybrid after production during multiple tests. Results are evaluated to classify the chips and hybrids and uploaded to a database. We evaluated those results for the first two production batches to measure the production yield. The yield is better than the threshold below which chip testing on a wafer level offers financial benefits. Observations on prominent chip failures were propagated back to the hybrid production process to further increase the yield for future productions. [ABSTRACT FROM AUTHOR]

The FCAL collaboration is preparing large scale prototypes of special calorimeters to be used in the very forward region at a future linear electron positron collider for a precise and fast luminosity measurement and beam-tuning. These calorimeters are designed as sensor-tungsten calorimeters with very thin sensor planes to keep the Moliere radius small and dedicated FE electronics to match the timing and dynamic range requirements. A partially instrumented prototype was investigated in the CERN PS T9 beam in 2014 and at the DESY-II Synchrotron in 2015. It was operated in a mixed particle beam (electrons, muons and hadrons) of 5 GeV from PS facilities and with secondary electrons of 5 GeV energy from DESY-II. The results demonstrated a very good performance of the full readout chain. The high statistics data were used to study the response to different particles, perform sensor alignment and measure the longitudinal shower development in the sandwich. In addition, Geant4 MC simulations were done, and compared to the data. [ABSTRACT FROM AUTHOR]

A new concept of a Charge Sensitive Amplifier without a high-value resistor in the feedback loop is presented. Basic spectroscopic parameters of the amplifier coupled to a coaxial High Purity Germanium detector (HPGe) are discussed. The amplifier signal input is realized with an n-channel J-FET transistor. The feedback capacitor is discharged continuously by the second, forward biased n-channel J-FET, driven by an RC low–pass filter. Both the analog—with a standard spectroscopy amplifier and a multi-channel analyzer—and the digital—by applying a Flash Analog to Digital Converter—signal readouts were tested. The achieved resolution in the analog and the digital readouts was 0.17% and 0.21%, respectively, at the Full Width at Half Maximum of the registered 60 Co 1332.5 keV gamma line. [ABSTRACT FROM AUTHOR]

In this paper, we present the design and test results of an encoder integrated circuit for the ATLAS Liquid Argon Calorimeter trigger upgrade. The encoder implements a low-latency and low-overhead line code called LOCic. The encoder operates at 320 MHz with a latency of no greater than 21 ns. The overhead of the encoder is 14.3%. The encoder is an important block of the transmitter ASIC LOCx2, which is prototyped with a commercial 0.25 μm Silicon-on-Sapphire CMOS technology and packaged in a 100-pin QFN package. [ABSTRACT FROM AUTHOR]

This paper describes the design, fabrication and experiment results of a 4×8-Gbps Vertical-Cavity Surface-Emitting Laser (VCSEL) array driver ASIC with the adjustable active-shunt peaking technique and the novel balanced output structure under the Silicon-on-Sapphire (SOS) process, and a custom array optical transmitter module, featuring a compact size of 10 mm×15 mm×5.3 mm. Both the array driver ASIC and the module have been fully tested after integration as a complete parallel transmitter. Optical eye diagram of each channel passes the eye mask at 8 Gbps/ch with adjacent channel working simultaneously with a power consumption of 150 mW/ch. The optical transmission of Bit-Error Rate (BER) less than 10E-12 is achieved at an aggregated data rate of 4×8-Gbps. [ABSTRACT FROM AUTHOR]

The last decades have witnessed substantial efforts in the development of several detector technologies for X-ray fluorescence (XRF) applications. In spite of the increasing trend towards performing, cost-effective and reliable XRF systems, detectors for soft X-ray spectroscopy still remain a challenge, requiring further study, engineering and customization in order to yield effective and efficient systems. In this paper we report on the development, first characterization and tests of a novel multielement detector system based on low leakage current silicon drift detectors (SDD) coupled to ultra low noise custom CMOS preamplifiers for synchrotron-based low energy XRF. This new system exhibits the potential for improving the count rate by at least an order of magnitude resulting in ten-fold shorter dwell time at an energy resolution similar to that of single element silicon drift detectors. [ABSTRACT FROM AUTHOR]

In this paper we present the general features of cryogenic (or "cold") electronics for noble liquid time projection chambers, with design principles and details for neutrino physics, a brief history of the technology and details of recent research and development that is driving the design of the detectors under construction. Finally, some comments on future R&D envisioned and the impact of this work on other fields is described. "Cold" in the context of this work applies to CMOS devices operated at 77 K and above, at liquids temperatures of LAr (89 K), LKr (125 K) and LXe (165 K), with most of the tests performed in, or at LN 2 (77 K). The paper is concentrated on the design of cold electronics for large liquid argon TPCs, those that have been successfully operated, MicroBooNE and ProtoDUNE, and those designed or under construction, such as SBND and DUNE first and second 10 kton modules. The high performance achieved with MicroBooNE and ProtoDUNE – a high signal-to-noise ratio combined with high stability of response – is mainly due to the integral approach to design and construction of sensing electrodes with cold readout electronics in a modular approach with the cryostat signal feed-throughs incorporating warm interface electronics into a Faraday cage with the cryostat. The integral concept is described in some detail in this paper. [ABSTRACT FROM AUTHOR]

This paper describes the design of the active muon veto subsystem for the MiniCLEAN dark matter direct detection experiment at SNOLAB in Sudbury, Ontario, Canada. The water-filled veto is instrumented with 48 PMTs which are read out by front-end electronics to time multiplex 48 photomultiplier channels into 6 digitizer channels and provide an instantaneous hit sum across the subsystem (N-Hit) for the veto trigger. We describe the primary system components: the PMTs, the support structure, the front-end electronics, and the data acquisition system. [ABSTRACT FROM AUTHOR]

In this paper, we present a high performance, automatic fully analog phase-to-voltage converter (PVC) circuit for phase shift measurements of periodic waveforms and repeated pulsed signals with zero and nonzero mean values. The PVC operation is fully automatic because an internal closed feedback loop guarantees the self-phase alignment (self-locking) between the reference and input signals. The system has been tested by measuring the phase shifts between the electrical signals generated by digital waveform generators and by photodiodes. The PVC output voltage dynamic range is ±10 V, independently from the phase-shift full-scales equal to ±10°, ±1°, and ±0.1°. The increase of the PVC sensitivity, expressed in volts/degree, which can be easily set to about 1, 10, and 100 V/°, is achieved without any amplification of the signal so avoiding the increasing and/or introduction of additional electronic noise to the measurements. As a consequence, for the smallest phase-shift full-scale equal to ±0.1°, the proposed PVC circuit is capable to achieve phase resolutions in the order of 0.0001°, a value one order of magnitude better than that one of commercial lock-in amplifiers. In the case of optical applications, the PVC is able to detect laser power variations with sensitivity values settable to about 6, 60, and 600 V/ $\mu \!$ W so achieving the best resolution of 16 pW. [ABSTRACT FROM PUBLISHER]

This paper reports the design of a 10-bit, high-resolution time-to-digital converter (TDC) based on Vernier residues amplification which is a novelty. This TDC architecture allows the measurement of wide time intervals with high picosecond-range resolution. The key benefits of the proposed TDC are that it reduces conversion jitter and provides more design flexibility to enhance matching performances of delay cells and thus reach high conversion linearity regardless of the process technology, which is a strong aspect of the approach. Simulations results show that the TDC achieves a timing resolution of 12 ps rms in a long 12.5 ns timing window, a low core power consumption of 4.8 mW and estimated differential and integral nonlinearities (DNL and INL) of 0.73 and 2.02 LSB with a standard deviation of 0.17 and 0.94 LSB respectively. The TDC, implemented in 0.13 mm CMOS technology, occupies a total silicon area of 1.83 $$\times $$ 2.23 mm $$^2$$ including pads. Such a TDC will find useful applications in tomographic systems, where several time-correlated single photon counting (TCSPC) channels need to be used in a massively parallel configuration such as in diffuse optical tomography or in time-of-flight positron emission tomography. [ABSTRACT FROM AUTHOR]

This paper presents the design and the test results of a 20 Gbps 4-level Pulse Amplitude Modulation (PAM4) Vertical Cavity Surface Emitting Laser (VCSEL) driving ASIC fabricated in a 55 nm CMOS technology for detector front-end readout. The PAM4 VCSEL driving ASIC consists of a Least Significant Bit (LSB) channel, a Most Significant Bit (MSB) channel and a novel PAM4-core output driver stage. This PAM4 VCSEL driving ASIC has been integrated in a customized optical module with the VCSEL array, and both the electrical function and the optical performance of the ASIC have been fully evaluated. The optical test results show that the Ratio Level Mismatch (RLM) of 20 Gbps eye diagram is 0.96, the Transmitter Dispersion Eye Closure Quaternary (TDECQ) is 0.63 dB, and the optical modulation amplitude is 761 μ W. [ABSTRACT FROM AUTHOR]