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International audience; SummaryStatic random-access memory (SRAM) is a cornerstone in modern microprocessors architecture, as it has high power consumption, large area, and high complexity. Also, the stability of the data in the SRAM against the noise and the performance under the radian exposure are main concern issues. To overcome these limitations in the quest for higher information density by memory element, the ternary logic system has been investigated, showing promising potential compared with the conventional binary base. Moreover, carbon nanotube field effect transistor (CNTFET) is a new alternative device with proper features like low power consumption and threshold voltage dependency on CNTAQAUTHOR: Please provide the expanded form of CNT at first mention in the abstract and in the body if it is an acronym. diameter. This paper proposes a new design for ternary SRAM using CNTFET and its evaluation by comparing it against two other designs in many aspects. Moreover, we investigated the static noise margin for the three designs to discuss their stability. Furthermore, we studied the reliability of the designs by evaluating the soft errors effect.

In this paper we compare simulation results on a differential pair circuit using a CNTFET model, already proposed by us, with the result obtained using Stanford model. We study the case of differential pair with differential input and single ended output as core of a 50 GHz amplifier for mm waves band. We consider the case of a CNTFET having a single CNT tube with indices (19,0) and 25 nm long. For this circuit we present result for its main parameters: gain, input impedance, output impedance, noise and distortion. Since the Stanford model includes fixed capacitance, for comparison we applied the same capacitance on our model. Since this capacitances dominate the high frequency cut, results are not much different, except for the lack of noise modelling in the Stanford model.

Overview 1. Introduction 2. Model Optimization 3. Model Verification

In this review we present many design of CNTFET-based circuits, already proposed by us and here critically examined. For some of these, we compare the performance of proposed circuits both in CNTFET and CMOS technology. For CNTFET model, we use a compact, semi-empirical model, already proposed by us and briefly recalled, while, for the MOSFET model, we use the BSIM4 one of ADS library. Moreover in some design examples we compare our results with those obtained using the Stanford model. All simulations are carried out using the software Advanced Design System (ADS), which is compatible with the Verilog-A programming language.

RF CNTFETs are one of the most promising devices for surpassing incumbent RF-CMOS technology in the near future. Experimental proof of concept that outperformed Si CMOS at the 130 nm technology has already been achieved with a vast potential for improvements. This review compiles and compares the different CNT integration technologies, the achieved RF results as well as demonstrated RF circuits. Moreover, it suggests approaches to enhance the RF performance of CNTFETs further to allow more profound CNTFET based systems e.g., on flexible substrates, highly dense 3D stacks, heterogeneously combined with incumbent technologies or an all-CNT system on a chip.

Engineering and Applied Science Research, 49, 6, 744-752

In this paper we review a procedure to design a full adder circuit based on CNTFET technology. In particular the proposed circuit is based on NAND and NOT logic gates. Using ADS software, we describe the procedure to determine the velocity, delay and power delay product (PDP), showing moreover the improvements obtained with CNTFET technology compared to CMOS one.

In this paper we propose a procedure to study the dependence of a CNTFET amplifier performance on CNT parameters that fully identify the geometrical properties of a regular CNT. In particular these parameters are the length and structural indices (n,m) of CNT. We analyse the effects on a linear common source amplifier using a N type CNTFET with a resistive gate polarization. We polarize at a fixed drain voltage and current, gradually changing the CNT parameters. As regards the indices, we present the analysis for a zig-zag CNT. However the proposed procedure can be applied to other types of CNT. We show the effect on gain, on the 3 dB cut off frequency, F3dB, on the input and output resistances, obtaining that F3dB has a clear inverse dependence on the length and that also decreases at higher structural indices for zig-zag CNT.

This paper presents a procedure to analyse the noise effects in the design of analog circuits based on CNTFETs. The noise mechanisms in electronic devices are discussed and the impact of the different noise sources is analysed. After a brief description of the basic structure of device and main noise sources existing in CNTFETs, a static, dynamic and noise analysis is presented. As an example of analog circuit, the proposed procedure is applied to study a basic current mirror and the simulation results allow to determine easily the different noise contribution of every single source. The software used is Advanced Design System (ADS) which is compatible with the Verilog A programming language.

In this paper initially we present two CNTFET models: the first, already proposed by us and the second the Stanford model, recalling our method to match the output characteristics and transconductance characteristics between these two models. Then we briefly recall a compact noise model, proposed by us, used to simulate the performance of some digital CNTFET circuits, for which we present the DC, transient and noise analysis. In particular we examine a inverter gate and the proposed analysis allows to determine the optimal value of input voltage which makes the noise effects negligible.

Memristive threshold logic (MTL) concept is emerged in many circuits to enable high-performance systems in terms of power, energy, area, and delay. This paper proposes a systematic method for building two-bit ternary number functions based on the MTL concept. The proposed method is applied to build the basic ternary arithmetic operations. The implementation of two-bit adder and multiplier is presented in the unbalanced ternary number representation. The proposed designs are verified by using VTEAM memristor and Stanford CNTFET transistor models. Finally, a comparison between the proposed circuits and related work presented in this paper is discussed. It shows that the area in case of the ternary adder is reduced by 30% and 76% and in case of the ternary multiplier by considering that memristors can be stacked above the transistors. In addition, this reduction in the number of transistors reduces the circuit static power and hence improving the overall ternary circuits performance.

In this paper we study the application of a single-CNTFET as power amplifier in the THz frequency range, using a CNTFET model, already proposed by us. We show that the device has, within stable condition, a Maximum Gain of at least 29 dB at frequencies below 30 GHz, decreasing to 20 dB at 800 GHz and reaching 18 dB at 1 THz. Through the analysis of a simple example, we show that it is possible to obtain a stable amplifier with tuned matching with a gain near the Maximum Gain at 1 THz. Finally we show that the matching of this device requires high ratio which could be hard to implement at 1 THz.

In this paper we initially present two CNTFET models: the first is already proposed by us and the second is the Stanford model, proposing a method to match the output characteristics and transconductance characteristics between these two models. Then we describe a compact noise model, used to simulate the performance of a NOT gate, in order to analyze how the noise sources constitute a significant limitation in the design of circuits based on CNTFET. All simulations are obtained using the programming language Verilog-A on the simulator Advanced Design System (ADS), highlighting the solutions proposed in order to use this software.

International audience; Multiply-Accumulate (MAC) is one of the most commonly used operations in modern computing systems due to its use in matrix multiplication, signal processing, and in new applications such as machine learning and deep neural networks. Ternary number system offers higher information processing within the same number of digits when compared to binary systems. In this paper, a MAC is proposed using a CNTFET-based ternary logic number. Specifically, we build a 5-trit multiplier and 10-trit adder as building blocks of two ternary MAC unit designs. The first is a basic MAC which has two methods to implement, serial and pipeline. The second is an improved MAC design that optimizes the number of transistors, offers higher performance and lower power consumption. The designed MAC unit can operate up to 300 MHz. Finally, a comparative study in terms of power, delay, and area variations is conducted under different supply voltages and temperature levels.

Adder core respecting to its various applications in VLSI circuits andsystems is considered as the most critical building block in microprocessors,digital signal processors and arithmetic operations. Novel designs of a lowpower and complexity Current Mode 1-bit Full Adder cell based onCNTFET technology has been presented in this paper. Three major partsconstruct their structures; 1) the first part that converts current to voltage; 2)threshold detectors (TD); and 3) parallel paths to convey the output currentsflow. Adjusting threshold voltages which are significant factor for settingthreshold detectors switching point has been achieved by means of CNTFETtechnology. It would bring significant improvements in adjusting thresholdvoltages, regarding to its unique characterizations. Simple design, lesstransistor counts and static power dissipation and better performancecomparing previous designs could be considered as some advantages of thenovel designs.

The progress of Carbon Nanotube Field Effect Transistor (CNTFET) devices has facilitated the trimness of mobile phones, computers and all other electronic devices. CNTFET devices contribute to model these electronics instruments that require designing the devices. This research consists of the design and verification of the CNTFET device's small signal model. Scattering parameters (S-parameters) is extracted from the CNTFET model to construct equivalent small model circuit. Current sources, capacitors and resistors are involved to evaluate this equivalent circuit. S-parameters and small signal models are elaborated to analyze using a technique to form the small signal equivalent circuit model. In this design modeling process, at first intrinsic device's Y-parameters are determined. After that series of impedances are calculated. At last, Y-parameters model are transformed to add parasitic capacitances. The analysis result shows the acquiring high frequency performances are obtained from this equivalent circuit.

Recently, carbon nanotube field-effect transistors (CNTFETs) have attracted wide attention as promising candidates for components in the next generation of electronic devices. In particular CNTFET-based RF devices and circuits show superior performance to those built with silicon FETs since they are able to obtain higher power-gain and cut-off frequency at lower power dissipation. The aim of this paper is to present a compact, design-oriented model of CNTFETs that is able to ease the development of a complete amplifier. As a case study, the detailed design of a high-gain CNTFET-based broadband inductorless LNA is presented.

International audience; Ternary number system offers higher information processing within the same number of digits when compared to binary systems. Such advantage motivated the development of ternary processing units especially with CNTFET which offers better power and delay results compared to CMOS-based realization. In this paper, we propose a variety of circuit realizations for the ternary memory elements that are needed in any processor including ternary D-latch, and ternary D-flip-flop. These basic building blocks are then used to design a ternary register file with multiple read and write ports. This paper is an attempt to investigate the performance aspects of using ternary RF to open the gate of more contributions and research in the direction of full ternary computer architecture. The proposed designs have been compared in terms of power, area, and latency at different supply voltages and operating temperatures.

The full adder is a key component for many digital circuits like microprocessors or digital signal processors. Its main utilization is to perform logical and arithmetic operations. This has empowered the designers to continuously optimize this circuit and ameliorate its characteristics like robustness, compactness, efficiency, and scalability. Carbon Nanotube Field Effect Transistor (CNFET) stands out as a substitute for CMOS technology for designing circuits in the present-day technology. The objective of this paper is to present an optimized 1-bit full adder design based on CNTFET transistors inspired by new CMOS full adder design [1] with enhanced performance parameters. For a power supply of 0.9V, the count of transistors is decreased to 10 and the power is almost split in two compared to the best existing CNTFET based adder. This design offers significant improvement when compared to existing designs such as C-CMOS, TFA, TGA, HPSC, 18T-FA adder, etc. Comparative data analysis shows that there is 37%, 50%, and 49% amelioration in terms of area, delay, and power delay product respectively compared to both CNTFET and CMOS based adders in existing designs. The circuit was designed in 32nm technology and simulated with HSPICE tools.

This paper proposed a new concept of highly SNM and low power SRAM cell using carbon nanotube FETs (CNTFETs) at 18nm technology node. As device physical gate length is reduced to below 65 nm, device non-idealities such as large parameter variations and exponential increase in Dynamic leakage current make the I-V characteristics substantially different from traditional MOSFETs and become a serious obstacle to scale devices. CNFETs have received widespread attention as one of the promising successor to MOSFETs. The proposed circuit was simulated in HSPICE using 32nm Stanford CNFET model. Analysis of the results shows that the proposed CNTFET based 3VL 8T SRAM cell, power dissipation, and stability substantially improved compared with the conventional CMOS 6T SRAM cell by 51% and 58% respectively at the expense of 4% write delay increase.

In this paper, in order to analyze the limits of CNTFET devices, we study the behavior of a differential amplifier based on CNTFET for application between 50 GHz and 500 GHz, determining the highest gain achievable with low noise level. In particular the examined circuit presents a differential input and single ended output, in which each CNTFET is composed by a single CNT, having the same diameter. The analysis is done without considering embedding parasitic effects since our aim is to study the intrinsic limits of CNTFET. We find a solution that is near optimum for gain and noise. In particular we obtain that, using CNTFETs whose channel length is 25 nm, it is possible to reach 27.0 dB gain at 50 GHz and 19.7 dB gain at 500 GHz with a noise spectral power density noise 95 nV/Hz and 85 nV/Hz respectively.

In this paper we have implemented the semi-empirical compact model for CNTFETs already proposed by us to simulate typical analogue circuits and logic blocks both in SPICE, using ABM library, and in Verilog-A. The obtained results have been the same in static simulations and comparable in dynamic simulations. However using Verilog-A the simulation run time has been much shorter and the software has been much more concise and clear than schemes using ABM blocks in SPICE.

CMOS transistors are most widely used for the design of computerized circuits, when scaling down the nanometer technology these devices faces the short channel effects and causes I-V characteristics to depart from the traditional MOSFETs, So the researchers have developed the other transistors technologies like CNTFET and GNRFET. Carbon nanotube field effect transistor is one of the optimistic technologies and it is a three terminal transistor similar to MOSFET. The semiconducting channel between the two terminals called source and drain comprises of the nano tube which is made of carbon. Graphene nano ribbon filed effect transistor is the most optimistic technology here the semiconducting channel is made of graphene. When contrasted with barrel shaped CNTFETs, GNRFETs can be prepared in situ process, transfer-free and silicon compatible, thus have no passage related and alignment problems as faced in CNTFET devices. This paper presents different 1-bit Full Adder Cells (FACs) like TG MUX-based FAC (TGM), MN MUX-based FAC (MNM), proposed TG Modified MUX-based FAC (TGMM) and another proposed MN Modified MUX-based FAC (MNMM) are designed using different technologies like CNTFET and GNRFET at 16nm technology with supply voltage of 0.85v and simulation is done by using Synopsys HSPICE Tool and the proposed designs are best when compared to the TGM and MNM FACs in terms of Static and Dynamic powers Dissipations and Delay.

The aim of this manuscript is to provide an overview about the possible applications of carbon nanotubes (CNTs) on two of the most crucial fields of the modern civilization, namely the electronic and propulsion ones. Specifically, implementation examples of some common electronic devices as MOSFETs, diodes and sensors, based on the unusual and exotic properties of CNTs are briefly shown. Moreover, by exploiting the photo-ignition property of CNTs (by means of an intense luminous pulse), this carbon-based material can be used to trigger the combustion of different kind of fuels in propulsion applications. In this context, the experimental results of the photo-ignition process of dry mixtures of CNTs enriched with metallic catalyzer, employing LED-based radiation source, are reported as well as the results related to the combustion tests of different fuels, mixed with air, in a combustion chamber.

This paper presents different low-leakage power Carbon NanoTube FET (CNTFET) based SRAM cells at nano technology. These SRAM cells are obtained by applying different circuit level leakage power reduction techniques called Sleep transistor, Forced stack, Data-Retention sleep transistor and Stacked sleep. All these cells are designed and simulated to assess their performance. All these techniques are compared in terms of leakage power, dynamic power, read delay, write delay, SNM and Area. Among all the SRAM cells, stacked sleep CNTFET SRAM cell is best in terms of leakage power saving with state saving capability.

In this paper presented Design and implementation of CNTFET based Ternary 1x1 RAM memories high-performance digital circuits. CNTFET Ternary 1x1 SRAM memories is implement using 32nm technology process. The CNTFET decresase the diameter and performance matrics like delay,power and power delay, The CNTFET Ternary 6T SRAM cell consists of two cross coupled Ternary inverters one is READ and another WRITE operations of the Ternary 6T SRAM cell are performed with the Tritline using HSPICE and Tanner tools in this tool is performed high accuracy. The novel based work can be used for Low Power Application and Access time is less of compared to the conventional CMOS Technology. The CNTFET Ternary 6T SRAM array module (1X1) in 32nm technology consumes only 0.412mW power and data access time is about 5.23ns.

SPICE compatible CNT interconnect and CNTFET models in Verilog-A hardware description language are presented in this paper. Metallic CNTs are shown to have current saturation characteristics above a threshold voltage and then modelled with piecewise linear functions. On the other hand, the CNTFET model developed utilizes the calculation of the self-consistent potential of the CNT channel depending on gate and drain voltages. Unlike the previous SPICE-enabled CNTFET models using approximations and curve fittings, the proposed model employs a self-consistent method for the calculation of the channel potential in SPICE, providing more accuracy. The versatility of the CNT interconnect model and that of the CNTFET model are shown in CNT circuit simulations. © 2012 Elsevier Ltd.

Carbon-based electronics is an emerging field. Its present progress is largely dominated by the materials science community due to the many still existing materials-related obstacles for realizing practically competitive transistors. Compared to graphene, carbon nanotubes provide better properties for building field-effect transistors, and thus, have higher chances for eventually becoming a production technology.

International audience; This paper presents an extension of a ballistic compact model to the case of nonballistic transport for the conventional carbon nanotube FET featuring a MOSFET-like operation. A large part of the novelty lies on the analytical implementation of acoustic phonon (AP) and optical phonon (OP) scattering mechanism. To carry out this implementation, some simplifications of the theoretical description are proposed while staying as close as possible to physics and keeping the high-speed simulation and good convergence capability of the compact model. The compact model simulation results are systematically compared and validated with respect to nonequilibrium Green function simulation results. Then, we have investigated the impact of AP and OP scattering on transistor figures of merit. Taking into account the scattering processes is of utmost importance for both analog and digital circuit designs, since neglecting the scattering leads to an overestimation of more than 70% of the main figures of merit and will mislead designers when optimizing the operating point for analog applications.

In this paper, we analyze the effects of temperature dependence of energy bandgap on [Formula: see text] characteristics in some carbon nanotube field effect transistors (CNTFETs) models proposed in literature in order to identify the one more suitable for computer aided design (CAD) applications. At first we consider a compact, semi-empirical model, already proposed by us, performing [Formula: see text] characteristic simulations at different temperatures. Our results are compared with those obtained with the Stanford-Source virtual carbon nanotube field-effect transistor model (VS-CNFET), obtaining [Formula: see text] characteristics comparable, but with lower CPU calculation time.

Band gap is an important property in designing single-walled carbon nanotube (SWCNT) for nanoelectronic devices. This paper describes the impact of SWCNT band gaps on the performance of a ballistic carbon nanotube field effect transistor (CNTFET) using the 2D numerical simulator. The results demonstrate that with the reduction in SWCNT band gap the performance parameters such as transconductance, output conductance, Ion/Ioff current ratio, gain, and carrier injection velocity enhanced while the short channel effects subthreshold slope and drain-induced barrier lowering get suppressed. The enhanced device performance and reduced short channel effects of CNTFET with the reduction in SWCNT band gaps signifying that the CNTFET is a suitable nanoelectronic device for amplification purposes, low power analog and digital circuits, high-speed and low power applications.

D-Latch has applications in Memory cells and Low power D-Latchs are important for low-power digital designs. In this paper, presents design of the low power & high speed D-Latch using carbon nanotube field effect transistor (CNTFET) that utilizes different threshold voltages for best performance. In this paper, proposed design of D-Latch is simulated with HSPICE models, cmos 32nm ptm and CNTFET 32nm which Presented by Stanford University. MOSFET and CNTFET designs are simulated in different voltage & 1MHz up to 1GHz frequency and their performances are compared. The simulation result shows that the proposed D-Latch design based on CNTFET achieved an improvement in the output parameters. Finally the results of power, Delay and power delay product show that this design based on CNTFET is more optimal than its MOSFET design.Keywords: Low power D-Latch; CNTFET; Carbon nanotubes Field effect transistors;power delay product (PDP)

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.

Presenting a novel full adder cell will be increases all the arithmetic logic unit performance. In this paper, We present two new full adder cell designs using carbon nanotube field effect transistors (CNTFETs). In the first design we have 42 transistors and 5 pull-up resistance so that we have achieved an improvement in the output parameters. Simulations were carried out using HSPICE based on the CNTFET model with 0.9V VDD. The denouments results in that we have a considerable improvement in power, Delay and power delay product than the previous works. &nbsp

The SRAM which functions as the cache for system-on-chip is vital in the electronic industry. Carbon Nanotube Field Effect Transistor (CNFET) is used for high performance, high stability and low-power circuit designs as an alternative material to silicon in recent years. Therefore Design of SRAM Cell based on CNTFET is important for Low-power cache memory. In cells, the bit-lines are the most power consuming components because of larger power dissipation in driving long bit-line with large capacitance. The cache write consumes considerable large power due to full voltage swing on the bit-line. This Paper proposes a novel 7T SRAM cell based on CNTFET that only depends on one of bit lines for Write operation and reduce the write-power consumption. The read cycle also improved because of careful transistor sizing. HSPICE simulations of this circuit using Stanford CNFET model shows that 37.2% write power saving, read cycle improvement of 38.6%.&nbsp

The effect of noise on the performance of Schottky Barrier Carbon Nanotube Field Effect Transistors (SB-CNTFETs) has been investigated under various bias conditions. In order to calculate the noise power spectral density, the Non-Equilibrium Green’s Function formalism (NEGF) is used to obtain the transmission coefficient and the number of carriers inside the channel. Results are presented in two sections: In the first section the Hooge’s empirical rule is used to investigate the flicker noise properties of SB-CNTFETs with defects in the gate oxide region, while in the second section the thermal and shot noise properties of SB-CNTFETs are studied. Finally, the best bias points in the ON and OFF states have been suggested according to the total noise power spectral density and the device signal to noise ratio.

The designs integrating the promising carbon nanotube transistors (CNTFET) will have to take into account the constraints implied by the strong dispersion inherent to nanotube manufacturing. This paper proposes to characterize the main CNTFET performances : on-current Ion, Ion/Ioff ratio and inverse sub-threshold slope S according to the dispersion on the nanotube diameter. For this purpose, we use a compact model suitable for testing several diameter values., Comment: Submitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions)

On the basis of acquired knowledge, the paper present a DC compact model designed for the conventional CNTFET (C-CNTFET) featuring a doping profile similar to n-MOSFET. The specific enhancement lies on the implementation of a physical based calculation of the minima of energy conduction subbands. This improvement allows a realistic analysis of the impact of CNT helicity and radius on the DC characteristics. The purpose is to enable the circuit designers to challenge CNTFET potentialities for performing logical or analogical functionalities within complex circuits

Carbon nanotubes (CNTs) have exceptional physical properties that make them one of the most promising building blocks for future nanotechnologies. They may in particular play an important role in the development of innovative electronic devices in the fields of flexible electronics, ultra-high sensitivity sensors, high frequency electronics, opto-electronics, energy sources and nano-electromechanical systems (NEMS). Proofs of concept of several high performance devices already exist, usually at the single device level, but there remain many serious scientific issues to be solved before the viability of such routes can be evaluated. In particular, the main concern regards the controlled synthesis and positioning of nanotubes. In our opinion, truly innovative use of these nano-objects will come from: i) the combination of some of their complementary physical properties, such as combining their electrical and mechanical properties, ii) the combination of their properties with additional benefits coming from other molecules grafted on the nanotubes, and iii) the use of chemically- or bio-directed self-assembly processes to allow the efficient combination of several devices into functional arrays or circuits. In this article, we outline the main issues concerning the development of carbon nanotubes based electronics applications and review our recent results in the field.