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1. Event-triggered control for discrete-time piecewise affine systems

Author

Leonardo B. Groff, João M. Gomes da Silva, Giorgio Valmorbida, Departamento de Engenharia Eletrica (UFRGS), Universidade Federal do Rio Grande do Sul [Porto Alegre] (UFRGS), Laboratoire des signaux et systèmes (L2S), CentraleSupélec-Université Paris-Saclay-Centre National de la Recherche Scientifique (CNRS), Dynamical Interconnected Systems in COmplex Environments (DISCO), Inria Saclay - Ile de France, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-Laboratoire des signaux et systèmes (L2S), CentraleSupélec-Université Paris-Saclay-Centre National de la Recherche Scientifique (CNRS)-CentraleSupélec-Université Paris-Saclay-Centre National de la Recherche Scientifique (CNRS), and ANR-18-CE40-0010,HANDY,Systèmes Dynamiques Hybrides et en Réseau(2018)

Subjects
piecewise affine systems, General Computer Science, Control and Systems Engineering, [INFO.INFO-AU]Computer Science [cs]/Automatic Control Engineering, Mechanical Engineering, stability, Electrical and Electronic Engineering, event-triggered control
Abstract

International audience; This work addresses the event-triggered control (ETC) of discrete-time piecewise affine systems. We propose a method to design a triggering strategy relying on an implicit representation of piecewise affine systems. Thanks to this implicit representation based on ramp functions, we propose a partition-dependent piecewise quadratic functions to define the trigger criterion and use a piecewise quadratic Lyapunov function candidate to derive conditions to certify the global exponential stability of the origin under the ETC strategy. Since the stability conditions can be expressed as linear matrix inequalities constraints, we propose a convex optimization solution to design the triggering function parameters and to compute the Lyapunov function to ensure the closed-loop stability and a reduction on the control updates. The approach is illustrated by numerical examples.

Published
2022
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2. Special Session: Operating Systems under test: an overview of the significance of the operating system in the resiliency of the computing continuum

Author

Gennaro S. Rodrigues, Oliver Sinnen, Maurizio Rebaudengo, Emmanuel Casseau, Stefano Di Carlo, Petr Dobias, Alberto Bosio, Fernanda Lima Kastensmidt, Alessandro Savino, Architectures matérielles spécialisées pour l’ère post loi-de-Moore (TARAN), Inria Rennes – Bretagne Atlantique, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-ARCHITECTURE (IRISA-D3), Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Bretagne Sud (UBS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National de Recherche en Informatique et en Automatique (Inria)-École normale supérieure - Rennes (ENS Rennes)-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-CentraleSupélec-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Bretagne Sud (UBS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-École normale supérieure - Rennes (ENS Rennes)-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes 1 (UR1), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT), Energy Efficient Computing ArchItectures with Embedded Reconfigurable Resources (CAIRN), ARCHITECTURE (IRISA-D3), Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-Télécom Bretagne-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes 1 (UR1), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-Télécom Bretagne-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-Télécom Bretagne-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-Inria Rennes – Bretagne Atlantique, Institut National de Recherche en Informatique et en Automatique (Inria), University of Auckland [Auckland], Departamento de Engenharia Eletrica (UFRGS), Universidade Federal do Rio Grande do Sul [Porto Alegre] (UFRGS), Politecnico di Torino = Polytechnic of Turin (Polito), École Centrale de Lyon (ECL), Université de Lyon, Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Rennes 1 (UR1), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique Bretagne-Pays de la Loire (IMT Atlantique), CentraleSupélec-Télécom Bretagne-Université de Rennes 1 (UR1), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-Institut National de Recherche en Informatique et en Automatique (Inria)-École normale supérieure - Rennes (ENS Rennes)-Université de Bretagne Sud (UBS)-Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-CentraleSupélec-Télécom Bretagne-Université de Rennes 1 (UR1), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Université de Rennes (UNIV-RENNES)-Université de Rennes (UNIV-RENNES)-École normale supérieure - Rennes (ENS Rennes)-Université de Bretagne Sud (UBS)-Centre National de la Recherche Scientifique (CNRS)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Université de Rennes (UNIV-RENNES)-Institut National des Sciences Appliquées (INSA), Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), Institut Mines-Télécom [Paris] (IMT)-Institut Mines-Télécom [Paris] (IMT)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-IMT Atlantique (IMT Atlantique), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-Télécom Bretagne-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-Université de Rennes (UR)-Institut National des Sciences Appliquées - Rennes (INSA Rennes), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Institut National de Recherche en Informatique et en Automatique (Inria)-Télécom Bretagne-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS)-Institut de Recherche en Informatique et Systèmes Aléatoires (IRISA), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Université de Bretagne Sud (UBS)-École normale supérieure - Rennes (ENS Rennes)-Télécom Bretagne-CentraleSupélec-Centre National de la Recherche Scientifique (CNRS), INL - Conception de Systèmes Hétérogènes (INL - CSH), Institut des Nanotechnologies de Lyon (INL), Université de Lyon-Université de Lyon-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-École Supérieure de Chimie Physique Électronique de Lyon (CPE)-Institut National des Sciences Appliquées de Lyon (INSA Lyon), Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)-École Centrale de Lyon (ECL), and Université de Lyon-Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Centre National de la Recherche Scientifique (CNRS)

Subjects
Very-large-scale integration, Computer science, Operating Systems, Reliability (computer networking), Fault Injection, Fault Tolerance, DIGITAL SYSTEM DESIGN TEST AND VERIFICATION, Fault tolerance, 02 engineering and technology, Reliability, computer.software_genre, Application layer, Task Scheduling, 020202 computer hardware & architecture, Scheduling (computing), Stack (abstract data type), RTOS, 0202 electrical engineering, electronic engineering, information engineering, Operating system, 020201 artificial intelligence & image processing, Session (computer science), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Layer (object-oriented design), computer
Abstract

International audience; The computing continuum's actual trend is facing a growth in terms of devices with any degree of computational capability. Those devices may or may not include a full-stack, including the Operating System layer and the Application layer, or just facing pure bare-metal solutions. In either case, the reliability of the full system stack has to be guaranteed. It is crucial to provide data regarding the impact of faults at all system stack levels and potential hardening solutions to design highly resilient systems. While most of the work usually concentrates on the application reliability, the special session aims to provide a deep comprehension of the impact on the reliability of an embedded system when faults in the hardware substrate of the system stack surface at the Operating System layer. For this reason, we will cover a comparison from an application perspective when hardware faults happen in bare metal vs. real-time OS vs. general-purpose OS. Then we will go deeper within a FreeRTOS to evaluate the contribution of all parts of the OS. Eventually, the Special Session will propose some hardening techniques at the Operating System level by exploiting the scheduling capabilities.

Published
2021
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3. Stabilisation of discrete‐time systems with finite‐level uniform and logarithmic quantisers

Author

Carlos Eduardo Pereira, Sophie Tarbouriech, Gustavo Cruz Campos, João Manoel Gomes da Silva, Departamento de Engenharia Eletrica (UFRGS), Universidade Federal do Rio Grande do Sul [Porto Alegre] (UFRGS), Équipe Méthodes et Algorithmes en Commande (LAAS-MAC), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), and Université de Toulouse (UT)

Subjects
0209 industrial biotechnology, Control and Optimization, Logarithm, 020208 electrical & electronic engineering, Linear system, Linear matrix inequality, Admissible set, 02 engineering and technology, State (functional analysis), [SPI.AUTO]Engineering Sciences [physics]/Automatic, Computer Science Applications, Human-Computer Interaction, 020901 industrial engineering & automation, Discrete time and continuous time, Control and Systems Engineering, Control theory, Attractor, Convergence (routing), 0202 electrical engineering, electronic engineering, information engineering, Electrical and Electronic Engineering, Mathematics
Abstract

International audience; This study deals with the stabilisation of discrete-time linear systems subject to static finite-level quantisation on thecontrol inputs. Two kinds of quantisers are considered: uniform and logarithmic. The modelling of the finite-level quantisation isobtained by the application of deadzone and saturation maps to an infinite-level quantiser. From this model, conditions for thesynthesis of state feedback control laws guaranteeing the convergence of the trajectories to an attractor around the originprovided that the initial state belongs to a certain admissible set are proposed. These conditions can thus be incorporated inlinear matrix inequality-based optimisation schemes to compute the stabilising gain while minimising the size of the attractor.

Published
2018
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4. Wave Equation With Cone-Bounded Control Laws

Author

Sophie Tarbouriech, João Manoel Gomes da Silva, Christophe Prieur, GIPSA - Systèmes non linéaires et complexité (GIPSA-SYSCO), Département Automatique (GIPSA-DA), Grenoble Images Parole Signal Automatique (GIPSA-lab ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut Polytechnique de Grenoble - Grenoble Institute of Technology-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut Polytechnique de Grenoble - Grenoble Institute of Technology-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Grenoble Images Parole Signal Automatique (GIPSA-lab ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut Polytechnique de Grenoble - Grenoble Institute of Technology-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut Polytechnique de Grenoble - Grenoble Institute of Technology-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Équipe Méthodes et Algorithmes en Commande (LAAS-MAC), Laboratoire d'analyse et d'architecture des systèmes (LAAS), Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées-Université Fédérale Toulouse Midi-Pyrénées-Centre National de la Recherche Scientifique (CNRS)-Université Toulouse III - Paul Sabatier (UT3), Université Fédérale Toulouse Midi-Pyrénées-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Institut National des Sciences Appliquées (INSA)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université Fédérale Toulouse Midi-Pyrénées-Université Toulouse - Jean Jaurès (UT2J)-Université Toulouse 1 Capitole (UT1), Université Fédérale Toulouse Midi-Pyrénées, Departamento de Engenharia Eletrica (UFRGS), Universidade Federal do Rio Grande do Sul [Porto Alegre] (UFRGS), Université Toulouse Capitole (UT Capitole), Université de Toulouse (UT)-Université de Toulouse (UT)-Institut National des Sciences Appliquées - Toulouse (INSA Toulouse), Institut National des Sciences Appliquées (INSA)-Université de Toulouse (UT)-Institut National des Sciences Appliquées (INSA)-Université Toulouse - Jean Jaurès (UT2J), Université de Toulouse (UT)-Université Toulouse III - Paul Sabatier (UT3), Université de Toulouse (UT)-Centre National de la Recherche Scientifique (CNRS)-Institut National Polytechnique (Toulouse) (Toulouse INP), Université de Toulouse (UT)-Université Toulouse Capitole (UT Capitole), and Université de Toulouse (UT)

Subjects
0209 industrial biotechnology, Partial differential equation, Differential equation, 010102 general mathematics, First-order partial differential equation, 02 engineering and technology, Delay differential equation, Nonlinear control, Wave equation, 01 natural sciences, [SPI.AUTO]Engineering Sciences [physics]/Automatic, Computer Science Applications, Nonlinear system, 020901 industrial engineering & automation, Control and Systems Engineering, Law, 0101 mathematics, Electrical and Electronic Engineering, Hyperbolic partial differential equation, Mathematics
Abstract

International audience; This paper deals with a wave equation with a one-dimensional space variable, which describes the dynamics of string deflection. Two kinds of control are considered: a distributed action and a boundary control. It is supposed that the control signal is subject to a cone-bounded nonlinearity. This kind of feedback laws includes (but is not restricted to) saturating inputs. By closing the loop with such a nonlinear control, it is thus obtained a nonlinear partial differential equation, which is the generalization of the classical 1D wave equation. The well-posedness is proven by using nonlinear semigroups techniques. Considering a sector condition to tackle the control nonlinearity and assuming that a tuning parameter has a suitable sign, the asymptotic stability of the closed-loop system is proven by Lyapunov techniques. Some numerical simulations illustrate the asymptotic stability of the closed-loop nonlinear partial differential equations.

Published
2016
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5. Applying the Oscillation Test Strategy to FPAA’s Configurable Analog Blocks

Author

Michel Renovell, Florence Azaïs, Marcelo Lubaszewski, Tiago R. Balen, A. Andrade, Departamento de Engenharia Eletrica (UFRGS), Universidade Federal do Rio Grande do Sul [Porto Alegre] (UFRGS), Conception et Test de Systèmes MICroélectroniques (SysMIC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)

Subjects
Engineering, business.industry, 020208 electrical & electronic engineering, Oscillation test, 02 engineering and technology, Signal, Field (computer science), Signature (logic), 020202 computer hardware & architecture, Amplitude, Field-programmable analog array, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Device under test, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electrical and Electronic Engineering, business, ComputingMilieux_MISCELLANEOUS, Parametric statistics
Abstract

This paper presents the application of the oscillation test methodology as an alternative to test configurable analog blocks of Field Programmable Analog Arrays. The blocks of the device under test are first configured to behave as oscillators. Then, the output frequency and amplitude are observed to obtain the signature of the fault-free circuit. During test, this signature is compared to the actual output signal. Experimental results show the effectiveness of the method in detecting parametric and large deviation faults of the tested components.

Published
2005
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6. A contextual resources use: a proof of concept through the APACHES' platform

Author

Thierry Gil, Gilles Sassatelli, Altamiro Amadeu Susin, A. Ngouangal, André Brugnara Soares, Lionel Torres, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Conception et Test de Systèmes MICroélectroniques (SysMIC), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Departamento de Engenharia Eletrica (UFRGS), and Universidade Federal do Rio Grande do Sul [Porto Alegre] (UFRGS)

Subjects
Computer science, business.industry, 020208 electrical & electronic engineering, Graph theory, 02 engineering and technology, Application software, computer.software_genre, 020202 computer hardware & architecture, Task (computing), Computer architecture, Proof of concept, Embedded system, 0202 electrical engineering, electronic engineering, information engineering, State (computer science), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Architecture, business, Field-programmable gate array, computer, Adaptive architecture
Abstract

International audience; A homogeneous architecture made of an array of so-called NPUs (network processing units) is presented in this paper. Those NPUs are endowed with elementary processing and communication capabilities, that for exploring the opportunity of finely adapting system behavior according to current system state. Applications considered in this work are described as task graphs, which are mapped at run-time taking into account the performance requirements, the number of available NPUs and their respective positions. The placement is performed using different algorithms. An adaptive architecture running several MJPEG streaming applications is used for experiments and comparisons.

Published
2006
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7. Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays

Author

A. Andrade, Florence Azaïs, G. Pereira, Michel Renovell, Marcelo Lubaszewski, Tiago R. Balen, Departamento de Engenharia Eletrica (UFRGS), Universidade Federal do Rio Grande do Sul [Porto Alegre] (UFRGS), Conception et Test de Systèmes MICroélectroniques (SysMIC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)

Subjects
Test strategy, Interconnection, Computer science, 020208 electrical & electronic engineering, 02 engineering and technology, Field (computer science), 020202 computer hardware & architecture, Set (abstract data type), Field-programmable analog array, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Adjacency list, Graph coloring, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Parametric statistics
Abstract

International audience; The test of field programmable analog arrays (FPAA) may be performed based on partitioning these devices in three main parts: I/O cells, interconnection networks and configurable analog blocks. In this work, a scheme for testing the I/O cells and the local and global interconnection networks of FPAAs is proposed, using an adjacency graph model to represent the programmable interconnection and I/O resources, and then devising a set of test configurations (TC) by solving graph coloring problems. The goal is to achieve a near minimum number of TCs ensuring all stuck-open and stuck-on faults in switches, as well as opens and shorts in wires, are covered. Large parametric faults in interconnects are implicitly covered in these TCs by judiciously choosing test stimuli and, in I/O buffers, by means of an oscillation-based test strategy.

Published
2005
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8. A Multi-Mode Signature Analyzer for Analog and Mixed Circuits

Author

Michel Renovell, Yves Bertrand, Marcelo Lubaszewski, Salvador Mir, Florence Azaïs, Conception et Test de Systèmes MICroélectroniques (SysMIC), Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Departamento de Engenharia Eletrica (UFRGS), Universidade Federal do Rio Grande do Sul [Porto Alegre] (UFRGS), Techniques of Informatics and Microelectronics for integrated systems Architecture (TIMA), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP)-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes (UGA), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), Techniques de l'Informatique et de la Microélectronique pour l'Architecture des systèmes intégrés (TIMA), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)

Subjects
Spectrum analyzer, Frequency response, Computer science, 020208 electrical & electronic engineering, Analyser, ComputerApplications_COMPUTERSINOTHERSYSTEMS, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, Signature (logic), 020202 computer hardware & architecture, PACS 8542, Integrator, 0202 electrical engineering, electronic engineering, information engineering, Electronic engineering, Transient response, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electronic circuit, Digital biquad filter
Abstract

International audience; In this paper a multi-mode signature analyser is proposed to be built into analog and mixed-signal integrated circuits. The analyser circuitry is based on analog integrators and can perform transient (with one integrator) and frequency (with two integrators) response compaction. The area overhead incurred can be very low, since the same signature analyser can be shared by several analog macros. Besides that, whenever integrators are available on-chip for functional purposes, they can be shared with the testing circuitry. Experiments carried on a Sallen-Key (transient response compaction) and on a biquad filter (frequency response compaction) showed that a very high coverage of catastrophic and pammetric faults can be obtained by using the proposed multi-mode signature analyser.

Published
1997
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