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This article presents a direct RF-to-digital converter (RDC) for polar receivers, in which the amplitude information of the received signal is detected by a reconfigurable analog-to-digital converter (ADC) and its phase is digitized using a time-to-digital converter (TDC). The RDC prototype also includes a multi-phase reference generator and an ADC sampling position adjustment unit realizing the sub-sampling technique. Unlike conventional direct-RF sampling receivers, the proposed RDC samples the input RF signal at the baseband rate. The RDC is capable of digitizing a variety of modulation waveforms, such as quadrature amplitude modulation (QAM), phase shift keying (PSK), and amplitude phase shift keying (APSK). When comparing QAM to APSK, the later has advantages of relaxed system requirements on phase noise and linearity. The proposed direct RF-to-digital polar converter IC achieves a maximum data rate of 1.94 GB/s with a 1024-APSK modulation at a carrier frequency of 6 GHz, while consumes only 3.8 mW power under 1.1 V supply.

Chronic Obstructive Pulmonary Disease (COPD) is a serious public health challenge in the world. According to the treatment instructions by Global Initiative for Chronic Obstructive Lung Disease (GOLD) 2020, bronchiectasis combine with inhaled corticosteroids and long-acting anti-muscarinic agents were recommended as the main prescription. However, this symptomatic treatment still has ineluctable limits because it ignored the most pathogenesis mechanism of COPD. As an alternative traditional Chinese medicine (TCM) for COPD, Bufei Jianpi granules (BJG) can reduce the frequency and duration of acute exacerbation in COPD patients and improve their quality of life. The evidence demonstrated BJG acts as therapeutics that retarding the airway remodeling process, eliminating phlegm, thrombolysis and improving mitochondrial function. However, the detailed molecular mechanism is still urgently revealed.In this study, we aim to find out the active pharmacodynamic ingredients and reveal the treatment mechanism of active pharmacodynamic ingredients.Based on the pharmacodynamic evaluation and chemomic profiling of BJG in COPD rats, an integrated multi-omics analysis was performed, including molecular networking, metabonomics, proteomics and bioinformatics. Moreover, focus on the active compounds, we verified the molecular core mechanism by molecular biology methods.Pachymic acid, shionone, peiminine and astragaloside A was verified as therapeutic agents for improving the condition of COPD by acting on the EGFR, ERK1, PAI-1 and p53 target, respectively.In this study, our findings indicated that some compounds in BJG alleviates the pathological process of COPD, which is related to regulating lung function, mucus production, pulmonary embolism and energy metabolism and this will be a benefit complementary to GOLD guidelines.

Software product forums is a platform filled with user feedback that utilises the sub-forum feature to categorise user discussion into themes. These sub-forums are very similar to classification labels that have been used to automatically classify user feedback on other platforms such as Troubleshooting and Feature Request. It would be very beneficial to the CrowdRE community if these sub-forum categories can be utilised in a research setting as it would reduce the effort required to label content for classification manually. However, no research has been done on the accuracy of these sub-forum categorisations in software product forums. In this exploratory study, we examined the accuracy of user categorised posts in two software product forums and discovered that users incorrectly categorise more than 20% of the posts during submission. Our discovery suggests that at the current stage, sub-forum categories should not be trusted as a label to classify feedback automatically.

CaIn this study, we explored the role of TMEM16A expression in human OSCC tissues using both TCGA dataset and immunohistochemistry. CCK-8 assay was applied to evaluate cell proliferation. Patch clamp technique was applied to record TMEM16A ClWe found that high TMEM16A expression is related with large tumor size, lymph node metastasis, and poor clinical outcome in patients with OSCC. In addition, TMEM16A overexpression could promote cell proliferation, and inhibition of TMEM16A channel activities could suppress cell proliferation in OSCC cells. Furthermore, simvastatin could suppress TMEM16A channel activities, and inhibited cell proliferation in OSCC cells via TMEM16A.Our findings identify a novel anti-tumor mechanism of simvastatin by targeting TMEM16A. Simvastatin may represent an innovative strategy for treating OSCC with high TMEM16A expression.

Chronic obstructive pulmonary disease (COPD) is a prevalent disease in China, especially among the elderly; and cost of medical treatment is known to be quite burdensome. This study aims to approximates the economic costs, by gender, attributable to COPD among elderly Chinese. Employ four multivariate linear and logistic regression models, methods to anticipate results based on relationship between different variants, on the data from China Health and Retirement Longitudinal Study (CHARLS), a nationwide survey began in 2011, to approximate the medical expenditure of outpatients and inpatients attributable to COPD among the study population. The result shows that medical expenditure has a positive correlation with COPD diagnosis irrespective of gender. Nevertheless, there is a significant difference in expenditure between the two genders. Government needs to focus on early diagnosis, promoting smoke-free lifestyles, popularizing public and private health insurance, while keeping in mind that males and females require different treatment due to physiological differences.

Recent advancements in performance, logic density, and power consumption of Field-Programmable Gate Arrays (FPGAs) have made them attractive for their widespread adoption into automotive, aircraft, space, military, and other safety-critical applications, in both embedded systems and cloud computing platforms. Every year, though, it becomes harder and harder to benefit from such advances in technology scaling due to smaller voltage margins, more aggressive clocking schemes, and greater device variability. FPGAs are often expected to last years or even decades in a variety of different environments before replacement. In some applications, they can be susceptible to soft and transient errors due to Single Event Upsets (SEUs), environment, and aging related effects. In this paper, we propose a simplified modular arithmetic technique based upon the concept of the digital root (DR) to monitor soft and transient errors, with low area overhead and high rates of detectability. The technique can be easily implemented at the register-transfer level (RTL) with no need to modify the underlying hardware of the FPGA. In one experiment, after dropping the supply voltage well below recommended design margins, we show in situ measurements on the instantaneous error rate in an Intel Arria 10 GX FPGA, which can be leveraged to optimize the power-performance trade-off of already deployed designs. We demonstrate this tradeoff, using an inherently error tolerant low-density parity-check (LDPC) decoder block, by either increasing the system clock beyond its synthesized target to achieve a 50% improvement in throughput, or by lowering the FPGA's supply voltage below synthesized design margins for a 65% reduction in power.

Integrated circuits, especially analog circuits, are highly sensitive to process, voltage, and temperature (PVT) variations. The information processed by analog circuits is often embedded in the amplitude of the waveforms, which requires circuits with high precision and high linearity. On the other hand, analog signal processing in time domain, such as (TDCs) and digital to-time converters (DTCs), was not widely adopted until the late 1990s when semiconductor technology advanced to the sub-micrometer region.

This paper presents an 8-bit 1.25-ps resolution reconfigurable Vernier time-to-digital converter (TDC) with a 2-D spiral comparator array and $\Delta \Sigma $ modulators for linearization. The proposed spiral 2-D comparator array improves both linearity and detection range of the TDC. The quantization errors introduced by digitally tuning delay cells are minimized by using a 2nd-order $\Delta \Sigma $ modulator. The folding point errors commonly seen in 2-D comparator arrays are randomized by using a reconfigurable comparator array controlled by the output of a 2nd-order $\Delta \Sigma $ modulator. The prototype TDC fabricated in a 45-nm silicon on insulator technology consumes 70- to 690- $\mu \text{W}$ power under a 1-V supply at 80-MHz conversion rate. The measured maximum differential nonlinearity/integral nonlinearity across its detectable range are 1.35/1.03 ps without the linearization techniques and 0.31/0.4 ps with the proposed linearization techniques, respectively.

A multifunctional integrated microfluidic biochip device was engineered to estimate the activity-toxicity and composition principle of medicine in a cell model in vitro. This biochip could be used for disease cells and healthy cells in two modules of “Yin-Yang” on the same chip for detecting the medicine efficacy-toxicity simultaneously, as well as adjust different gradient ratios of concentration through the Christmas tree structure in both “Yin-Yang” modules autonomously for detecting the best compatibility of medicine in maximum efficacy and minimal toxicity. In the applicability experiment, the best concentration of three chemical compounds including dinatin, diosmetin and cisplatin, were detected using the biochip and traditional 96-cell plate. Biochip assays showed perfect positive correlation compared with the results of traditional 96-cell plate, in addition presented advantages as less detection time and much lower price than the traditional 96-cell plate, which indicated the biochip is both convenient and feasible. Thus, the novel microfluidic chip-based multifunctional integrated system congregated the virtues of high throughput, rapid, sensitive, specific, cost-effective, and similar to the physical environment of the human body, which was especially suitable for the medicine efficacy-toxicity and compatibility evaluation.

Nonsteroidal anti-inflammatory drugs (NSAIDs), such as cyclooxygenase (Cox)-1/2 inhibitor, have emerged as potent antipyretics and analgesics. However, few herbs with Cox-1/2 inhibitory activity are commonly used for heat-clearing in China. Although these are known to have antipyretic activity, there is a lack of molecular data supporting their activity. Using the traditional Chinese medicine herb honeysuckle (Hon) as an example, we explored key antipyretic active compounds and their mechanisms of action by assessing their metabolites and metabolomics. Mitogen-activated protein kinase (MAPK) 3 and protein kinase B (AKT) 1 were suggested as key targets regulated primarily by chlorogenic acid (CA) and swertiamarin (SWE). CA and SWE synergistically inhibited the production of interleukin (IL)-1 and IL-6, alleviated generation of prostaglandin E2, and played an antipyretic role equivalent to honeysuckle extract at the same dose contents within 3 h. Collectively, these findings indicated that lipopolysaccharide-induced fever can be countered by CA with SWE synergistically, allowing the substitution of a crude extract of complex composition with active compounds. Our findings demonstrated that, unlike the traditional NSAIDs, the Hon extract showed a remote and indirect mechanism for alleviating fever that depended on the phosphatidylinositol-3-kinase–AKT and MAPK pathways by regulating the principal mediator of inflammation.

A fractional-N digital phase-locked loop (PLL) architecture with low fractional spur is presented in this paper. A 2-D Vernier time-to-digital convertor (TDC) is implemented to achieve wide detection range with fine resolution. The TDC is calibrated automatically utilizing the ramp signal generated from the fractional-N accumulator for optimal linearity. A digi-phase spur cancellation technique with automatic TDC gain tracking is also implemented to further suppress the fractional spurs. The chip also includes an improved multimodulus divider (MMD) structure that overcomes the glitch problem during division ratio toggling associated with the prior art MMDs, enabling carrier synthesis across wide frequency range continuously. As part of an 802.11a/b/g/n transceiver, the DPLL can provide coverage for both 2.4/5 G WiFi bands. The proposed fractional-N DPLL is implemented in a 55-nm CMOS technology. The DPLL achieves a largest fractional spur level of −55 dBc without using a sigma–delta modulator and an in-band phase noise of −107 dBc/Hz (0.55 ps integrated jitter) while consuming 9.9 mW.

The modern software landscape is highly competitive. Software companies need to quickly fix reported bugs and release requested new features, or they risk negative reviews and reduced market share. The amount of online user feedback prevents manual analysis. Past research has investigated automated requirement mining techniques on online platforms like App Stores and Twitter, but online product forums have not been studied. In this paper, we show that online product forums are a rich source of user feedback that may be used to elicit product requirements. The information contained in forum questions is different from what has been described in the related work on App Stores or Twitter. Users often provide detailed context to specific problems they encounter with a software product and other users respond with workarounds or to confirm the problem. Through the analysis of two large forums, we identify 18 different types of information (classifications) contained in forums that can be relevant to maintenance and evolution tasks. We show that a state-of-the-art App Store tool is unable to accurately classify forum data, which may be due to the differences in content. Thus, specific techniques are likely needed to mine requirements from product forums. In an exploratory study, we developed classifiers with forum specific features. Promising results are achieved for all classifiers with f-measure scores ranging from 70.3% to 89.8%.

This paper presents a direct RF-to-digital converter (RDC) for polar RX. It consists of a pair of TDCs, an ADC, and a precise sampling position control system. Unlike conventional direct-RF sampling receivers, the RDC samples the input RF signal at baseband rate. It is capable of directly digitizing the phase and amplitude of the received modulated RF signals. It is compatible with a variety of modulations and has advantages of relaxed system requirements on phase noise and linearity when APSK is used. The RDC achieves a max rate of 1.94 GB/s with 1024-APSK at a carrier of 6 GHz, consuming only 3.8mW.

This paper presents the design of a fully self-timed 8-bit 80-Ms/s single-core SAR ADC with interleaved comparators and a high order compensated opamp-less bandgap reference. A 3/2 interleaving algorithm was designed for better SFDR performance, where two of the three comparators are orderly chosen for interleaving in each conversion while offset calibration is applied to the idle comparator. Asynchronized SAR logic with a DAC settling timer is designed for fully self-timing of the ADC. The ADC was designed with a PVT stabilized on-chip reference source which promises a stable reference for the ADC at extreme temperature environments such as aerospace exploration or quantum computing. Technique for compensating the temperature coefficient (TC) of a bandgap reference (BGR) using temperature characteristics of transistor's current gain β is proposed. Measured results show 42.8dB SNDR, 56.8 dB SFDR and −53.3dBc THD for the proposed SAR ADC, drawing 1.07mW from a 1.1v supply. Measured average TC of the HBT proposed BGR is 23ppm/°C and 39 ppm/°C over the commercial (0∼70°C) and space (−260∼125°C) temperature ranges, respectively. The BGR reaches PSRR of −50dB at 1MHz, and −38dB at 1GHz. The entire chip was implemented on 0.13um 8HP SiGe process with an active area of 0.2952 mm2.

This paper presents a successive approximation register (SAR) assisted hybrid analog to digital converter (ADC) that uses a time domain quantizer for sub-range quantization. The proposed hybrid ADC utilizes an 8b 2bit-per-cycle SAR coarse ADC pipelined with a 6b 2-dimensional Vernier time-to-digital converter (TDC) as the fine quantizer for high-resolution and high conversion rate. Different from the conventional approach, the voltage residue is converted into time domain for fine quantization which greatly relaxes the power-to-noise requirement of the comparator for high-resolution. Moreover, the 8b coarse quantization stage greatly reduces the range of the residue signal and thus dramatically relieves the linearity requirement of the voltage-to-time (V-T) conversion. The LSB of the TDC is digitally calibrated thus the gain accuracy of the pipeline stage is relaxed. The prototype was fabricated in a 45nm CMOS process, and the ADC core dissipates 3.66 mA from a 1-V supply with an active area of 0.08 mm2. The prototype chip achieves a measured peak SNDR of 65.7dB and SFDR of 80.7dB at conversion rate up to 280MS/s. The calculated Walden and Schreier figures-of-merit (FoM) are 8.4fJ/conv.-step and 171.5dB, respectively.

A CMOS digital-bits-in/-out Terahertz (THz) nano-radio with 0.57mm2 chip area is presented in this paper. The THz operation and bidirectional transmitter/receiver (TX/RX) architecture lead to radio ultra-miniaturization for Internet-of-Things (IoT) and field-deployable sensor applications. The bidirectional THz radio is configured as a harmonic oscillator in the TX mode or as a super-harmonic super-regenerative RX in the RX mode. The TX harmonic oscillator is directly modulated by On-Off Keying (OOK) data for bits-to-THz transmitting, while an on-chip time-to-digital converter (TDC) with 25ps timing resolution measures RX oscillation start-up time for direct THz-to-bits receiving. The radio peak DC power is optimized based on link distance and data rate. It supports maximum 4.4Mb/s OOK over 50cm at 49.3mW peak DC power and 1Mb/s OOK over 17cm at 18.7mW peak DC power without using any Silicon lens.

This paper presents a time-to-digital (TDC) design with large detectable range and fine resolution, combining a ring TDC with a 2-dimentional (2D) Vernier TDC. The detectable range has been greatly increased to 14 bits with the ring structure. A 1-ps resolution was achieving with 2D Vernier architecture. Utilizing the 2nd order ΔΣ modulators (SDM) and a 2D spiral arbiter array, the proposed TDC greatly mitigates the quantization errors introduced by digitally controlled delay cells and the intrinsic arbiter line folding errors associated with the 2D array topology. The measured maximum DNL/INL are 0.41/0.79ps with ΔΣ linearization. A prototype TDC chip fabricated in 130nm CMOS technology achieves a conversion rate of 10 MS/s while consumes 2.4 mW power.

This work presents an 8-bit 1.25ps resolution Vernier TDC with 2D reconfigurable spiral arbiter array and ΔΣ linearization for ADPLL. The 2D spiral arbiter array improves both linearity and detection range. The quantization errors introduced by delay cells and 2D arbiter array folding points are minimized using a reconfigurable arbiter array with 2nd order ΔΣ modulators. The prototype in a 45nm CMOS technology consumes 0.3mW power under a 1V power supply with 80MHz conversion rate. The measured maximum DNL/INL are 0.31/0.4 ps with ΔΣ linearization and 1.35/1.03 ps without ΔΣ linearization, respectively.

This work presents a 1.9∼5.6 GHz fractional-N DPLL with digi-phase spur canceller. It utilizes a ramp signal generated from the fractional-N accumulator to automatically calibrate the TDC linearity. The chip also includes an MMD that overcomes the division ration skipping problem associated with the prior art MMDs. The ADPLL achieves a worst fractional spur level of −55 dBc and an in-band phase noise of −109 dBc/Hz (0.63 ps integrated jitter) while consuming 9.9 mW.