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We present a highly configurable, low-power, low-area, low-EVM, SAW-less transmitter (TX) architecture that is based on a dynamically biased power mixer. All FDD/TDD bands from 0.7 to 2.7 GHz for 4G LTE Rel-11 and 3G $\bf{HSPA} + $ are supported in addition to 2G quad bands. The power-mixer bias current is dynamically adjusted based on the instantaneous baseband signal swing using a fully-differential hybrid full-wave rectifier/envelope-detector circuit. Dynamic biasing leads to greater than 50% current savings when compared to fixed-biasing while providing a higher output power with better linearity. Implemented in 28 nm CMOS technology, the TX shows better than $- \bf{157}\;\bf{dBc}/\bf{Hz}$ RX-band noise emission and $- \bf{41}\;\bf{dBc}$ ACLR for output powers up-to $+ \bf{4}\;\bf{dBm}$ across all 3G/4G bands, while demonstrating above 80 dB of gain control range. In addition, the TX can be configured to provide better than $- \bf{65}\;\bf{dBc}$ CIM3, allowing it to meet stringent spurious emission specifications when transmitting 1 RB 4G LTE signals in B13/B26/B1.

BSIM6 is the latest industry-standard bulk MOSFET model from the BSIM group developed specially for accurate analog and RF circuit designs. The popular real-device effects have been brought from BSIM4. The model shows excellent source-drain symmetry during both dc and small signal analysis, thus giving excellent results during analog and RF circuit simulations, e.g., harmonic balance simulation. The model is fully scalable with geometry, biases, and temperature. The model has a physical charge-based capacitance model including polydepletion and quantum-mechanical effect thereby giving accurate results in small signal and transient simulations. The BSIM6 model has been extensively validated with industry data from 40-nm technology node.

We present a phenomenological compact model of the inversion charge centroid considering both the structural and electrical confinements in multigate FETs. The developed new model shows a good match with Technology-CAD (TCAD) data for both physical parameters such as fin thickness in FinFET and wire radius in cylindrical FET, channel doping, and electrical bias variation. With the introduction of fitting parameters, the model is capable of handling hole and electron carriers, various channel materials, and process variations, such as fin shape, etc.

Two turn-key surface potential-based compact models are developed to simulate multigate transistors for integrated circuit (IC) designs. The BSIM-CMG (common-multigate) model is developed to simulate double-, triple-, and all-around-gate FinFETs and it is selected as the world's first industry-standard compact model for the FinFET. The BSIM-IMG (independent-multigate) model is developed for independent double-gate, ultrathin body (UTB) transistors, capturing the dynamic threshold voltage adjustment with back gate bias. Starting from long-channel devices, the basic models are first obtained using a Poisson-carrier transport approach. The basic models agree with the results of numerical two-dimensional device simulators. The real-device effects then augment the basic models. All the important real-device effects, such as short-channel effects (SCEs), quantum mechanical confinement effects, mobility degradation, and parasitics are included in the models. BSIM-CMG and BSIM-IMG have been validated with hardware silicon-based data from multiple technologies. The developed models also meet the stringent quality assurance tests expected of production level models.

With aggressive technology scaling and heightened variability, circuits such as SRAMs and DRAMs have become vulnerable to random telegraph noise (RTN). The bias dependence (i.e., non-stationarity), bi-directional coupling, and high inter-device variability of RTN present significant challenges to understanding its circuit-level effects. In this paper, we present two computer-aided design (CAD) tools, SAMURAI and MUSTARD, for accurately estimating the impact of non-stationary RTN on SRAMs and DRAMs. While traditional (stationary) analysis is often overly pessimistic (e.g., it overestimates RTN-induced SRAM failure rates), the predictions made by SAMURAI and MUSTARD are more reliable by virtue of non-stationary analysis.

In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX.

A turnkey, production circuit simulation ready compact model for cylindrical/surround gate transistors has been developed. The core of the model contains an enhanced surface potential based description of the charge in the channel. Analytical expressions for channel current and terminal charges have been derived. A method to account for quantum confinement in the cylindrical structure in a compact model framework is described. For the first time we present calibration results of such a model to a cylindrical gate technology that also exhibits asymmetric I–V characteristics.

We present a highly-configurable, low-power, low-area, SAW-less TX architecture that is based on a dynamically-biased power mixer. All FDD/TDD bands for 4G LTE and 3G WCDMA/HSPA are supported in addition to 2G quad bands. The power-mixer bias current is dynamically adjusted based on the instantaneous baseband signal swing using a fully-differential hybrid full-wave rectifier / envelope detector circuit. Implemented in 28nm CMOS technology, the TX shows better than −157dBc/Hz RX-band noise emission and −41dBc ACLR for output powers up-to 4dBm across all 3G/4G bands. In addition, the TX can be configured to provide better than −65dBc CIM3, allowing it to meet stringent spurious emission specifications when transmitting 1RB 4G LTE signals in B13 / B26 / B1.

In this letter, we present a thermal network extraction methodology to characterize self-heating effect using two-port RF measurements. We show the technique of determining isothermal condition using only the self-heating (thermal) dominated range of the spectrum. We use a self-consistent self-heating extraction scheme using both the real and imaginary parts of drain port admittance parameters. Appropriate thermal network is investigated, and a large amount of temperature rise due to self-heating is confirmed for short channel silicon-on-insulator MOSFETs with ultrathin body and buried oxide.

A new model and a theory to capture the effects of halo (pocket) implants on the flicker noise of the advanced-node MOSFETs have been proposed and verified with measurements. The model can accurately capture the bias dependence of the drain-current flicker-noise (FN) power density. Also for the first time, we explain and model the unexpected channel-length dependence of FN power density in strong-halo devices.

Our study breaks down the dependence of SRAM read current (Iread) variability (σIread) into constituting pass-gate (PG) and pull down (PD) NMOS transistor variability. We report a bottoms-up model for σIread including feedback in stacked transistors and discuss its implications on SRAM performance.

A unified FinFET compact model is proposed for devices with complex fin cross-sections. It is represented in a normalized form, where only four different model parameters are needed. The proposed model accurately predicts the current-voltage characteristics of different FinFETs structures such as Double-Gate (DG), Cylindrical Gate-All-Around (Cy-GAA), or Rectangular Gate-All-Around (Re-GAA) FinFETs. In addition, for the first time, Trapezoidal Triple-Gate (T-TG) FinFETs are accurately modelled. Short-Channel-Effects (SCE) sub-models have been also implemented in the presented work. The model has been verified with TCAD data.

The aggressive downscaling of advanced bulk CMOS technologies demands MOSFET models that are able to describe accurately the behavior of devices accounting for all the physical phenomena. A reliable model should have the ability to handle all the different operating regions of the MOS transistor in the whole geometry range of one technology. Targeting to meet the aforementioned needs, the new charge-based compact model BSIM6 has been developed. In this article, as a first benchmarking of BSIM6, the model is evaluated for its scaling capabilities when a single set of parameters is used. The model is compared against a state-of-the-art 40nm CMOS technology. The results attest the model's scalability under all bias conditions, proving its reliability for nowadays complex IC designs.

We present a non-iterative and physical five-step RF SPICE model extraction procedure. This procedure is applicable to any MOSFET compact model with all necessary RF-related components in it. This methodology has been validated on silicon data from multiple technology nodes for a wide range of bias and frequency.

In latest CMOS technologies, Random Telegraph Noise (RTN) has emerged as an important challenge for SRAM design. Due to rapidly shrinking device sizes and heightened variability, analytical approaches are no longer applicable for characterising the circuit-level impact of non-stationary RTN. Accordingly, this paper presents SAMURAI, a computational method for accurate, trap-level, non-stationary analysis of RTN in SRAMs. The core of SAMURAI is a technique called Markov Uniformisation, which extends stochastic simulation ideas from the biological community and applies them to generate realistic traces of non-stationary RTN in SRAM cells. To the best of our knowledge, SAMURAI is the first computational approach that employs detailed trap-level stochastic RTN generation models to obtain accurate traces of non-stationary RTN at the circuit level. We have also developed a methodology that integrates SAMURAI and SPICE to achieve a simulation-driven approach to RTN characterisation in SRAM cells under (a) arbitrary trap populations, and (b) arbitrarily time-varying bias conditions. Our implementation of this methodology demonstrates that SAMURAI is capable of accurately predicting non-stationary RTN effects such as write errors in SRAM cells.

A global I-V parameter extraction methodology for multi-gate MOSFET compact model is presented for the first time. New L-dependent properties are proposed to enable the accurate modeling of transistors over a wide range of gate length using a single set of model parameters. The results are verified with FinFET experimental data with effective channel lengths from 30nm to 10um. For both n and p type devices, excellent agreement between the data and the model has been demonstrated.

A convenient test-bench for quickly assessing the degradation and stability of an organic electronic device is proposed. The extent of degradation is quantified by the decrease in the current flowing through the device at a particular bias. The three parameters considered to affect the degradation are time, charge fluence through the device and energy dissipation in the device. Data from experimental results on different organic devices, especially bulk heterojunction devices with a blend of poly (3-hexylthiopene) and [6,6]-phenyl-C61-buytric acid methyl ester (P3HT:PCBM) shows that the charge fluence has a direct bearing on the extent of degradation. The estimated parameters from measured data using the proposed model helps compare quantitatively the extent and cause of degradation for a given device as well as compare the robustness of under various operating condition, the devices fabricated with different material, device structure or processes.

In this paper, we discuss the recent enhancements made in the BSIM6 bulk MOSFET model. BSIM6 is the latest compact model of bulk MOSFET from BSIM group which have body referenced charge based core. Junction capacitance model is improved over BSIM4 and is infinitely continuous around Vbs=V bd=0V. Symmetry of the model is successfully validated by performing Gummel Symmetry Test (GST) in DC and symmetry test for capacitances in AC. Self heating model is also included in BSIM6 and test results are reported. Model capabilities are compared against an advanced 40nm CMOS technology and it is observed that simulated results are in excellent agreement with the measured data. © 2013 IEEE.