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Quantum confinements, especially quantum in narrow wells, have been investigated because of their controllability over electrical parameters. For example, quantum dots can emit a variety of photon wavelengths even for the same material depending on their particle size. More recently, the research into two-dimensional (2D) materials has shown the availability of several quantum mechanical phenomenon confined within a sheet of materials. Starting with the gapless semimetal properties of graphene, current research has begun into the excitons and their properties within 2D materials. Even for simple 2D systems, experimental results often offer surprising results, unexpected from traditional studies. We investigated a coupled quantum well system using 2D hexagonal boron nitride (hBN) barrier as well as 2D tungsten disulfide (WS2) semiconductor arranged in stacked structures to study the various 2D to 2D interactions. We determined that for hexagonal boron nitride-tungsten disulfide (hBN/WS2) quantum well stacks, the interaction between successive wells resulted in decreasing bandgap, and the effect was pronounced even over a large distance of up to four stacks. Additionally, we observed that a single layer of isolating hBN barriers significantly reduces interlayer interaction between WS2 layers, while still preserving the interwell interactions in the alternative hBN/WS2 structure. The methods we used for the study of coupled quantum wells here show a method for determining the respective exciton energy levels and trion energy levels within 2D materials and 2D materials-based structures. Renormalization energy levels are the key in understanding conductive and photonic properties of stacked 2D materials.

Quantum confinements, especially quantum in narrow wells, have been investigated because of their controllability over electrical parameters. For example, quantum dots can emit a variety of photon wavelengths even for the same material depending on their particle size. More recently, the research into two-dimensional (2D) materials has shown the availability of several quantum mechanical phenomenon confined within a sheet of materials. Starting with the gapless semimetal properties of graphene, current research has begun into the excitons and their properties within 2D materials. Even for simple 2D systems, experimental results often offer surprising results, unexpected from traditional studies. We investigated a coupled quantum well system using 2D hexagonal boron nitride (hBN) barrier as well as 2D tungsten disulfide (WS

Transition metal oxide-based memristors have widely been proposed for applications toward artificial synapses. In general, memristors have two or more electrically switchable stable resistance states that device researchers see as an analogue to the ion channels found in biological synapses. The mechanism behind resistive switching in metal oxides has been divided into electrochemical metallization models and valence change models. The stability of the resistance states in the memristor vary widely depending on: oxide material, electrode material, deposition conditions, film thickness, and programming conditions. So far, it has been extremely challenging to obtain reliable memristors with more than two stable multivalued states along with endurances greater than ∼1000 cycles for each of those states. Using an oxygen plasma-assisted sputter deposition method of noble metal electrodes, we found that the metal-oxide interface could be deposited with substantially lower interface roughness observable at the n...

Asymmetric sized single oxide diode (InZnOx/CuOx) with single resistor (Ti-doped NiO) device (1D-1R) was integrated into a crossbar array at room temperature to provide high current through the diode while keeping resistance switching localized in a small area. The Ti (0.1 wt %) doped NiO layer was fabricated inside an inverted cone-structure to localize switching and improve general device performance. We were able observe resistance switching up to around 100 cycles in the 1D-1R structure. In addition, the addition of the diode to the structure acted as an external resistance suppressing overflow current during Ti-doped NiO switching from a high resistance state to a low resistance state, thus improving switching distribution in both low (average = 3.2×10-5 Ω, standard deviation = 1.3×10-6) and high (average = 2.8×10-6 Ω, standard deviation = 6.7×10-7) resistance states.

Quantum dot light-emitting diodes (QLEDs) has been developed toward flexibility without sacrificing optical and electrical performances as in the case of organic light-emitting diodes (OLEDs) display. The biggest challenge is replacing the conventional rigid or brittle electrodes, which has not been successful in the QLEDs yet. In this study, the flexible QLEDs without degradation of both optical and electrical performances are demonstrated to exhibit excellent light-emitting properties (maximum luminance of 14,330 cd/m2 and maximum current efficiency of 20.77 cd/A) with a low turn-on voltage of 3.5 V. The double-layered graphene of stepwise-tuned workfunctions was developed as a flexible and transparent anode. The top layer of a graphene film is oxidized by the oxygen plasma, which promotes wettability of the hydrophilic hole injection layer (HIL) and enhances the rate of hole injection by mediating the workfunctions between HIL and the pristine graphene anode. The color shift as a function of brightness could be minimized due to the balanced charge injection through this new electrode. The flexibility of QLEDs could be accomplished with mixture of an Al film and Ag nanowires as a cathode. No significant degradation of flexible QLED performances could be observed through a bending test involving even 1,000 bends.

In order to fully utilize the excellent electrical properties of graphene as an electrode, it is essential to preserve the nature of pristine graphene. However, structural defects or polymer residues during the conventional fabrication steps are inevitable, severely limiting device performance. To overcome these issues, we used a seamless lateral graphene–graphene oxide (GO)-graphene layer fabricated by oxidation scanning probe lithography as electrodes of the MoS2 field-effect transistor. We demonstrated residue-free and flawless graphene surfaces and furthermore GO interlayer between the MoS2 and gate dielectric reduces interface roughness and screens interface traps, leading to improved electron injection and carrier mobility.

The wet transfer of graphene requires sacrificial layer, which can support graphene during the removal of metallic substrate and prevent mechanical damage of thin graphene. However, the used polymer layer leaves an amounts of debris or residue on the graphene surface. The typical amorphous thermoplastic resins that consist of macromolecular chains with no crosslinks between the chains have been investigated as sacrificial layers for transferring graphene grown on metallic substrate. We have observed that the strong interaction of graphene and polymer provides clean surface without a chuck of residues and largely diminishes wrinkles and folds of transferred graphene. In addition, due to the increased substrate coupling as well as uniform plausible covalent bonding, we have achieved significant amount of electron transfer from graphene. Thus, polymer-self-doped-graphene during the transfer process has no need for the additional doping process or annealing process in order to obtain clean and flat surface with reduced sheet resistance. No thermal budget makes graphene available towards flexible transparent device application.

Recently, attempts to overcome the physical limits of memory devices have led to the development of promising materials and architectures for next-generation memory technology. The selector device is one of the essential ingredients of high-density stacked memory systems. However, complicated constituent deposition conditions and thermal degradation are problematic, even with effective selector device materials. Herein, we demonstrate the highly stable and low-threshold voltages of vanadium pentoxide (V2O5) nanosheets synthesized by facile chemical vapor deposition, which have not been previously reported on the threshold switching (TS) properties. The electrons occupying trap sites in poly-crystalline V2O5 nanosheet contribute to the perfectly symmetric TS feature at the bias polarity and low-threshold voltages in V2O5, confirmed by high-resolution transmission electron microscopy measurements. Furthermore, we find an additional PdO interlayer in V2O5 nanodevices connected with a Pd/Au electrode after th...

Poly (methyl methacrylate) (PMMA) is commonly used during the transfer process of chemical vapor deposited (CVD) graphene. Since PMMA on graphene surfaces is removed by breaking polymerization backbone bonds (de-polymerization), using shorter polymer chains can be a self-solving method for PMMA residue removal. We report on graphene properties transferred with different average molecular weight poly (methyl methacrylate) (PMMA). We obtained enhanced field effect mobility and reduced hole doping without post-annealing for lower average molecular weight PMMA. Also, the graphene surfaces transferred by lower average molecular weight PMMA was free of polymer debris with clean morphology, which was confirmed by carbon 1s X-ray photoemission spectroscopy. This graphene transfer process can be used to avoid additional thermal budget which can cause degradation of device performance.

We investigated the drain avalanche hot carrier effect (DAHC) of p-type metal-oxide-semiconductor field effect transistor of 0.14 μm channel length (PMOSFET) with SiON gate dielectric. Using three different stress conditions of substrate maximum current, the changes to threshold voltage, maximum transconductance, saturation current and channel leakage current was monitored. Concurrently, the lateral distribution of interface trap density ( N it ) and bulk trapped charge density ( N ot ) with stress time has been extracted along the 70 nm half channels from gate edge to drain junction, which is the first endeavor in describing charge traps along sub 100 nm short channels. The degradation of the PMOSFET was described by combining electrical property with N it and N ot profiles. Hot electron punch through (HEIP) effect was evidenced by negative Not distribution near the drain junction while more severe hot carrier degradation was successfully demonstrated by the empirical power law dependence of the electrical parameters N it and N ot . We have studied the evolution of degradation behavior along highly scaled tens of nanometer channel, and N it and N ot profile offers systematic study and interpretation of degradation mechanism of hot carrier effect in MOSFET devices.

Transition metal oxide-based memristors have widely been proposed for applications toward artificial synapses. In general, memristors have two or more electrically switchable stable resistance states that device researchers see as an analogue to the ion channels found in biological synapses. The mechanism behind resistive switching in metal oxides has been divided into electrochemical metallization models and valence change models. The stability of the resistance states in the memristor vary widely depending on: oxide material, electrode material, deposition conditions, film thickness, and programming conditions. So far, it has been extremely challenging to obtain reliable memristors with more than two stable multivalued states along with endurances greater than ∼1000 cycles for each of those states. Using an oxygen plasma-assisted sputter deposition method of noble metal electrodes, we found that the metal-oxide interface could be deposited with substantially lower interface roughness observable at the nanometer scale. This markedly improved device reliability and function, allowing for a demonstration of memristors with four completely distinct levels from ∼6 × 10

On Si and sapphire substrates, 6–45 nm thick films of atomic layer-deposited Al $$_{2}$$ O $$_{3}$$ were grown. The thermal conductivity of ALD films has been determined from a linear relation between film thickness and thermal resistance measured by the 3 $$\omega $$ method. ALD films on Si and sapphire showed almost same thermal conductivity in the temperature range of 50–350 K. Residual thermal resistance was also obtained by extrapolation of the linear fit and was modeled as a sum of the thermal boundary resistances at heater–film and film–substrate interfaces. The total thermal resistance addenda for films on sapphire was close to independently measured thermal boundary resistance of heater–sapphire interface. From the result, it was deduced that the thermal boundary resistance at ALD Al $$_{2}$$ O $$_{3}$$ –sapphire interface was much lower than that of heater–film. By contrast, the films on Si showed significantly larger thermal boundary resistance than films on sapphire. Data of $$< 30$$ nm films on Si were excluded because an AC coupling of electrical heating voltage to semiconductive Si complicated the relation between 3 $$\omega $$ voltage and temperature.

LiF is a transparent polar dielectric with the highest band gap among known insulators. The introduction of a LiF/graphene stacked structure provides two significant advantages: mobility enhancement and the stability of the Fermi-level-modulated (doped) state without transmittance loss. The former arises from the increased screening of charged impurities by the high-dielectric environment of LiF, and the latter is due to the self-passivation effect on electron doping achieved by surface dipole interaction originating from high polarizability of LiF. Unlike unstable doping methods based on molecular adsorption or chemical bonding, the doping induced by a highly polar dielectric interface maintains stability and can be reliable method, which is compatible with the Si process.

The modulation of charge carrier concentration allows us to tune the Fermi level (E F) of graphene thanks to the low electronic density of states near the E F. The introduced metal oxide thin films as well as the modified transfer process can elaborately maneuver the amounts of charge carrier concentration in graphene. The self-encapsulation provides a solution to overcome the stability issues of metal oxide hole dopants. We have manipulated systematic graphene p-n junction structures for electronic or photonic application-compatible doping methods with current semiconducting process technology. We have demonstrated the anticipated transport properties on the designed heterojunction devices with non-destructive doping methods. This mitigates the device architecture limitation imposed in previously known doping methods. Furthermore, we employed E F-modulated graphene source/drain (S/D) electrodes in a low dimensional transition metal dichalcogenide field effect transistor (TMDFET). We have succeeded in fulfilling n-type, ambipolar, or p-type field effect transistors (FETs) by moving around only the graphene work function. Besides, the graphene/transition metal dichalcogenide (TMD) junction in either both p- and n-type transistor reveals linear voltage dependence with the enhanced contact resistance. We accomplished the complete conversion of p-/n-channel transistors with S/D tunable electrodes. The E F modulation using metal oxide facilitates graphene to access state-of-the-art complimentary-metal-oxide-semiconductor (CMOS) technology.

The electronic property of graphene was investigated by hydrazine treatment. Hydrazine (N₂H₄) highly increases electron concentrations and up-shifts Fermi level of graphene based on significant shift of Dirac point to the negative gate voltage. We have observed contact resistance and channel length dependent mobility of graphene in the back-gated device after hydrazine monohydrate treatment and continuously monitored electrical characteristics under Nitrogen or air exposure. The contact resistance increases with hydrazine-treated and subsequent Nitrogen-exposed devices and reduces down in successive Air-exposed device to the similar level of pristine one. The channel conductance curve as a function of gate voltage in hole conduction regime keeps analogous value and shape even after Nitrogen/Air exposure specially whereas, in electron conduction regime change rate of conductance along with the level of conductance with gate voltage are decreased. Hydrazine could be utilized as the highly effective donor without degradation of mobility but the stability issue to be solved for future application.

Polymer residue-free graphene nanoribbons (GNRs) of 200 nm width at 1 μm pitch were periodically generated in an area of 1 cm(2) via laser interference lithography using a chromium interlayer prior to photoresist coating. High-quality GNRs were evidenced by atomic force microscopy, micro-Raman spectroscopy, and X-ray photoelectron spectroscopy measurements. Palladium nanoparticles were then deposited on the GNRs as catalysts for sensing hydrogen gases, and the GNR array was utilized as an electrically conductive path with less electrical noise. The palladium-decorated GNR array exhibited a rectangular sensing curve with unprecedented rapid response and recovery properties: 90% response within 60 s at 1000 ppm and 80% recovery within 90 s in nitrogen ambient. In addition, reliable and repeatable sensing behaviors were revealed when the array was exposed to various gas concentrations even at 30 ppm.

Transistor size is constantly being reduced to improve performance as well as power consumption. For the channel length to be reduced, the corresponding gate dielectric thickness should also be reduced. Unfortunately, graphene devices are more complicated due to an extra capacitance called quantum capacitance (C Q) which limits the effective gate dielectric reduction. In this work, we analyzed the effect of C Q on device-scaling issues by extracting it from scaling of the channel length of devices. In contrast to previous reports for metal-insulator-metal structures, a practical device structure was used in conjunction with direct radio-frequency field-effect transistor measurements to describe the graphene channels. In order to precisely extract device parameters, we reassessed the equivalent circuit, and concluded that the on-state model should in fact be used. By careful consideration of the underlap region, our device modeling was shown to be in good agreement with the experimental data. C Q contributions to equivalent oxide thickness were analyzed in detail for varying impurity concentrations in graphene. Finally, we were able to demonstrate that despite contributions from C Q, grapheme’s high mobility and low-voltage operation allows for graphene channels suitable for next generation transistors.

We report on the fabrication of completely uniform monolayer graphene on a metal thin film over a 150 mm Si substrate at a low temperature of 600 °C by inductively coupled plasma-enhanced chemical vapor deposition (ICPCVD). Through novel use of bimetallic catalyst such as CuNi and AuNi alloys we were able to control catalytic reaction at the metal surface and grow complete monolayer graphene with a Ni content less than 20 at.%. We also found that the 2D/G intensity ratio in the Raman spectra was almost invariant with growth time and the C 1s peak in the XPS spectra was observed only at the metal surface. This implies that monolayer graphene was possibly grown on these Ni-doped copper and gold catalysts by a self-limiting surface reaction under our CVD condition. From DFT calculations, it was shown that the catalytic activity of normally inactive Cu and Au could be enhanced through the addition of Ni atoms at surface sites, providing graphene growth at lower temperatures than pure Cu or Au. The carrier mobility of graphene films grown on these CuNi and AuNi alloy catalyst was measured to be over 9000 cm2 V−1 s−1 at room temperature, which is comparable to that of CVD graphene film grown on Cu foil. Therefore, we suggest an efficient way in growing a complete monolayer graphene on thin films at low temperatures, which could be a key issue in the application of graphene devices.

In this work, compact current modeling of field-effect transistors (FETs) with transferred graphene channel grown by using chemical vapor deposition is presented. A highly-doped silicon substrate is used as a back gate, channels are defined by using electron-beam lithography, and the channel length of the transistor is scaled down to 20 nm. The DC characteristics of the scaled graphene transistors are observed by considering the source/drain series resistances. In compact modeling of graphene FETs, an electron-hole puddle existing near the charge-neutral region (Dirac point) is considered at a low carrier density while the velocity saturation effect due to surface polar phonon scattering is included at a high carrier density.

Graphene based low noise amplifier has been studied actively because the noise characteristics of graphene devices are known to be superior to those of silicon devices. However, 1/f noise characteristics of graphene grown by chemical vapor deposition (CVD) may increase by an order of magnitude when measured before the charge exchange reaction at the interface of the graphene and substrate is saturated. Based on the close correlation between the level of low frequency noise signal and fast charge exchange reaction (in milliseconds), the conductivity fluctuation of graphene caused by the interfacial charge exchange reaction may be the source of the increased low frequency noise. This result suggests that the current assessment of noise characteristics is too optimistic for graphene and that the defect density of CVD graphene needs to be further reduced to minimize the charge exchange reaction.

The thickness-dependent bipolar resistance-switching behavior was investigated for epitaxiallygrown Cr-doped SrTiO3 (Cr-STO). All the pristine devices of different thickness showed polarity-independent symmetric current-voltage characteristic and the same space-charge-limited conduction mechanism. However, after a forming process, the resultant conduction and switching phenomena were significantly different depending on the thickness of Cr-STO. The forming process itself was highly influenced by resistance value of each pristine device. Based on our results, we suggest that the resistance-switching mechanism in Cr-STO depends not only on the insulating material’s composition or the contact metal as previously reported but also on the initial resistance level determined by the geometry and the quality of the insulating material. The bipolar resistance-switching behaviors in oxide materials of different thicknesses exhibit mixed bulk and interface switching. This indicates that efforts in resistance-based memory research should be focused on scalability or process method to control a given oxide material in addition to material type and device structure.

Graphene-based non-volatile charge-trap memory devices were fabricated and characterized to investigate the implementation effect of both 2-dimensional graphene and the 3-dimensional memory structure. The single-layer-graphene (SLG) channel devices exhibit larger memory windows compared to the multi-layer-graphene (MLG) channel devices. This originates from the gate-coupling strength being larger in SLG devices than in MLG devices. Namely, the electrostatic charge screening effect becomes enhanced upon increasing the number of graphene layers; therefore, the gate tunability is reduced in MLG compared to SLG. The results suggest that SLG is more desirable for memory applications than MLG.

We report nanoscale domain boundaries on single layer graphene probed with conductive probe atomic force microscopy in ultrahigh vacuum. Graphene was prepared using the inductively coupled plasma chemical vapor deposition technique on a copper substrate. Current mapping revealed domains 50–100 nm in size on the single layer graphene. Stick slip images revealed a hexagonal structure of the graphene layer in the middle of the domain. The conductance on the domain boundary is lower than that inside the domain structure, which is associated with disorder on the boundary, while friction and adhesion measurements on the domain boundaries did not show any contrast. We found that the conductance contrast is prominent at high loads, suggesting the domain boundary plays a significant role in the charge transport properties of graphene under mechanical deformation. Copyright © 2012 John Wiley & Sons, Ltd.

We developed a scanning noise microscopy (SNM) method and demonstrated the nanoscale noise analysis of a graphene strip-based device. Here, a Pt tip made a direct contact on the surface of a nanodevice to measure the current noise spectrum through it. Then, the measured noise spectrum was analyzed by an empirical model to extract the noise characteristics only from the device channel. As a proof of concept, we demonstrated the scaling behavior analysis of the noise in graphene strips. Furthermore, we performed the nanoscale noise mapping on a graphene channel, allowing us to study the effect of structural defects on the noise of the graphene channel. The SNM method is a powerful tool for nanoscale noise analysis and should play a significant role in basic research on nanoscale devices.

Numerous candidates attempting to replace Si-based flash memory have failed for a variety of reasons over the years. Oxide-based resistance memory and the related memristor have succeeded in surpassing the specifications for a number of device requirements. However, a material or device structure that satisfies high-density, switching-speed, endurance, retention and most importantly power-consumption criteria has yet to be announced. In this work we demonstrate a TaO(x)-based asymmetric passive switching device with which we were able to localize resistance switching and satisfy all aforementioned requirements. In particular, the reduction of switching current drastically reduces power consumption and results in extreme cycling endurances of over 10(12). Along with the 10 ns switching times, this allows for possible applications to the working-memory space as well. Furthermore, by combining two such devices each with an intrinsic Schottky barrier we eliminate any need for a discrete transistor or diode in solving issues of stray leakage current paths in high-density crossbar arrays.

The existence of reversible resistance switching (RS) behaviors induced by electric stimulus has been known for some time, and these intriguing physical phenomena have been observed in numerous materials, including oxides. As conventional charge-based random access memory is expected to face a size limit in the near future, a surge of renewed interest has been developed in RS phenomena for possible applications in small nonvolatile memory devices called resistance random access memory (RRAM). Of particular interest is unipolar RS, which shows the RS at two values of applied voltage of the same polarity. The unipolar RS exhibits a much larger resistance change than other RS phenomena, and this greatly simplifies the process of reading the memory state. When fabricated with oxide p-n diodes, memory cells using unipolar RS can be stacked vertically, which has the potential for dramatically increasing memory density. Therefore, unipolar RRAM may be a good candidate for multi-stacked, high density, nonvolatile memory. The most important scientific and technical issues concerning unipolar RS are how it works and the identification of its controlling parameters. Some studies have reported that unipolar RS comes from a homogeneous/inhomogeneous transition of current distribution, while others maintain that it comes from the formation and rupture of conducting filaments. Even with recent extensive studies on unipolar RS, its basic origin is still far from being understood. In addition, no model exists that actually explains how the reversible switching can occur at two values of applied voltage. This lack of a quantitative model poses a major barrier for unipolar RRAM applications. In this study, we describe RS behavior in polycrystalline TiO2 film. To explain the basic mechanism of unipolar RS behavior, we propose a new percolation model based on a network of ‘‘circuit breakers’’ with two switchable metastable states. The random circuit breaker (RCB) network model can explain the long-standing material issue of how unipolar RS occurs. This simple percolation model is different from the conventional percolation models, which have dealt only with static or irreversible dynamic processes. In addition, the RCB network model provides an indication of how to overcome the substantial distribution of switching voltages, which is currently considered the most serious obstacle to practical unipolar RRAM applications. The unipolar RS phenomenon can be explained by the current (I)-voltage (V) curves in Figure 1a, which are derived from measurements of our polycrystalline TiO2 thin capacitors. At the pristine state (green dot), they are in an insulating state. As the external voltage Vext increases from zero and reaches a threshold voltage Vforming, a sudden increase occurs in the current. If the current is not limited to a certain value, here called the compliance current Icomp, the TiO2 capacitor would experience a dielectric breakdown and be destroyed. However, [*] Prof. T. W. Noh, S. C. Chae, S. B. Lee, S. H Chang, Dr. C. Liu ReCOE & FPRD, Department of Physics and Astronomy Seoul National University Seoul 151-747 (Korea) E-mail: twnoh@snu.ac.kr

while still retaining a selective switch (transistor or diode) asthe data storage element. Thus for high-density applications,crossbar structures are ideal, whereas for non-volatility, resis-tance-change materials showthe best promise. In orderto rea-lize the fabrication of universal memory elements, it is im-perative to develop a class of materials and structures thatcombine robust processibility, strong scalability, and rapidprogramming speed with non-volatility and low power con-sumption. In our work, we have focused on defining just thestorage node portion of the devices, which utilize the resis-tance change within the film to store information via two dif-ferent stable resistance states. Here, we have attempted to de-termine the properties of such structures and to study themechanisms behind resistance RAM (RRAM) storage. OurTi-doped (0.1 wt %) NiO samples deposited at room temper-ature show favorable node characteristics such as the lowestwrite current reported thus far for a unipolar switching resis-tance-change-based device (ca. 10 lA). In addition, the pro-gramming speed is comparable to the write time of SRAM(10 ns). By combining this node element with an appropriateselect switch, such as a high-performance diode, a thresholddevice, or a two-terminal non-ohmic device, it becomes possi-ble to fabricate high-density universal memory.Indeed, the fabrication of universal memory as the nextgeneration of non-volatile memory is the logical goal for re-search in this field. In comparison to Flash and dynamicRAM (DRAM), which are the current industry standards,next generation memories must combine the non-volatility ofFlash with the high-speed performance of SRAM.

Magnetic tunnel junction (MTJ) elements based magnetologic promises many advantages over conventional CMOS logic devices. MTJ elements can be configured by simple circuitry to compute various Boolean functions and store the results. Advantages of magnetologic include low power consumption, the possibility of high-speed operation, and high density. We have proposed a novel magnetologic structure comprising a single-layer MTJ and a current driver, which requires fewer processing steps and provides enhanced functional flexibility and uniformity. Here, we expand the computational capabilities of single-layer MTJs, using series connections. An algorithm that realizes complex Boolean functions with fewer magnetologic elements than previous papers is presented.

Correctness of Java programs is important because they are executed in distributed computing environments. The object initialization scheme in the Java programming language is complicated, and this complexity may lead to undesirable semantic bugs. Various tools have been developed for detecting program patterns that might cause errors during program execution. However, current tools cannot identify code patterns in which an uninitialized field is accessed when an object is initialized. We refer to such erroneous patterns as uninitialized field references. In this paper, we propose a static pattern detection algorithm for identifying uninitialized field references. We design a sound analysis for this problem and implement an analyzer using the Soot framework. In addition, we apply our algorithm to some real Java applications. From the experiments, we identify 12 suspicious field references in the applications, and among those we find two suspected errors by manual inspection.

A one-bit cell of a general nonvolatile memory consists of a memory element and a switch element. Several memory elements have been tried given that any bistable states, that is, two charging states, two spin states, or two resistance states, can be used for a memory element. On the other hand, silicon-based transistors have been the most popularly used switch element. However, silicon-based transistors do not conform to high-density, nonvolatile memories with three-dimensional (3D) stack structures due to their high processing temperatures and the difficulty of growing high-quality epitaxial silicon over metals. Here, we show a low-temperaturegrown oxide diode, Pt/p-NiOx/n-TiOx/Pt, applied as a switch element for high-density, nonvolatile memories. The diode exhibits good rectifying characteristics at room temperature: a rectifying ratio of 10 at ± 3 V, a forward current density of up to ∼ 5×10 A cm, an ideality factor of 4.3, and a turn-on voltage of 2 V. Furthermore, we verify its ability to allow and deny access to the Pt/NiO/Pt memory element with two stable resistance states. Under the forward-bias condition, we could access the memory element and change the resistance state, although access was denied under the reverse bias condition. This one-diode/one-resistor (1D/1R) structure could be a promising building block for high-density, nonvolatile random-access memories with 3D stack structures. A p–n diode, like a transistor, is a fundamental circuit element for thin-film electronics. Until now, epitaxial silicon was most frequently used to fabricate p–n diodes in electronic devices with planar structures. However, to increase device density further, we require p–n diodes that are applicable to devices with 3D stack structures. Epitaxial silicon-based p–n diodes cannot be fabricated with stack structures as it is difficult to grow on a metal layer and high processing temperatures are required. On the other hand, although amorphous silicon allows for lower processing temperatures, it does not provide the required semiconducting performance. Therefore, to realize high-density electronic devices with 3D stack structures, we need new p–n diodes composed of semiconducting materials with low processing temperatures and high performance. In particular, new p–n diodes with low processing temperatures and high performance are indispensable to high-density, nonvolatile random-access memory devices. By replacing a transistor with a simpler diode as a switch element, there exists the possibility of producing memory cells with cross-point structures composed of bit lines and word lines perpendicular to each other, with a memory element lying between them. Theoretically, by utilizing this cross-point structure, the cell size can be scaled down to 4F (F: feature size used for patterning the cell), which is the smallest cell size attainable in nonvolatile memories with planar structures. Furthermore, by fabricating 3D stacks of the cross-point structure, the effective cell size can be scaled down to 2F, 1F, and so on. A common issue in realizing a cross-point structure is the availability of a thin-film diode with the high rectifying ratio and current density required for the switch element to access the memory element. Oxide based p–n diodes are good candidates to provide solutions to the issues associated with Si-based diodes. Most oxides, such as TiO2, [4] ZrO2, [5] ZnO, and indium tin oxide (ITO), are well-known n-type semiconductors that are characterized by the electron-transport properties of oxygen vacancies. As NiOx is a well-known p-type semiconductor beC O M M U N IC A IO N

The electrical and micro-structural properties of polycrystalline nickel oxides grown by reactive direct current (DC) sputtering were investigated by current-voltage (I-V) measurements, X-ray diffraction (XRD), and scanning electron microscopy (SEM). The oxygen content in the gas mixture was found to be an important parameter affecting the electrical properties of NiO films. At partial pressures above 10%, increasing the oxygen content during sputtering decreased the resistivity. The mechanism of electrical conductivity for the NiO films is discussed from the viewpoint of Nickel or Oxygen vacancies, which generate holes and electrons respectively, vacancy concentration was confirmed by Rutherford backscattering spectrometry (RBS).

Graphene was used for a sensing part of bottom-gate field-effect transistor (FET)-type gas sensors, and the sensing performance of the sensors was studied. We investigated the effect of temperature (T) and relative humidity on the gas sensitivity of bottom-gate graphene FETs prepared by the inductively coupled plasma chemical vapor deposition method. The conductivity change of graphene exposed to nitrogen oxide (NO2) and ammonia (NH3) was increased with increasing temperature and humidity. For NO2 gas, the graphene FET shows increasing ID with increasing T and also increasing ID with increasing humidity. However, the FET shows an opposite trend with the T and humidity for NH3 gas.

Effects of forming gas annealing (FGA) were investigated on ferroelectric Bi3.25La0.75Ti3O12 (BLT) thin films fabricated by chemical solution deposition. In the case of low-temperature FGA below 350°C, the BLT films were found to have quite a high resistance against hydrogen-induced degradation compared to PbZr0.4Ti0.6O3 (PZT) films. After FGA at 300°C, the BLT capacitors showed only a small reduction of remanent polarization and no deformation of their hysteresis loops while the PZT capacitors showed a large polarization degradation and serious hysteresis loop deformations. Hydrogen depth profiles, analyzed by secondary ion mass spectroscopy after FGA, showed comparable amounts of hydrogen penetration for both BLT and PZT films. X-ray photoemission spectroscopy measurements suggested that, for BLT films, the chemical stability of BLT may be responsible in part for the observed hydrogen annealing resistance.

Short-time retention loss behaviors were investigated for fatigued Pt/PbZr0.4Ti0.6O3/Pt capacitors. In the short-time regime of t

Retention loss is an important issue for an application of ferroelectric thin films to nonvolatile memory devices. We investigated the polarization retention characteristics of ferroelectric Bi 3.25 La 0.75 Ti 3 O 12 (BLT) thin films fabricated on Pt/TiO 2 /SiO 2 /Si substrates by pulsed laser deposition. The polarization loss showed a power-law-like decay within the first second after writing. The retained polarization seemed to fall nearly into one curve irrespective of the write/read pulse fields when normalized with respect to the initial polarization measured at 250 w s. Thermally-accelerated retention failure tests showed that the BLT films retained 85% the initial polarization after baked at 120°C for 3.6 2 10 5 s.

There are several important reliability issues that have hindered the commercialization of ferroelectric random access memory (FRAM). SrBi 2 Ta 2 O 9 (SBT) thin films have attracted much attention due to their fatigue-free properties for the FRAM applications. Recently, in elucidating the origin of the fatigue-free properties, we found that Ladoping in Bi 4 Ti 3 O 12 films can increase the chemical stability of the oxygen ions, resulting in fatigue-free characteristics. In addition to the excellent characteristics, the (Bi,La) 4 Ti 3 O 12 (BLT) films were found to have good properties for FRAM applications, including a low processing temperature and a large remnant polarization value. More recently, we also found that the BLT films have good retention properties and high resistance against hydrogen damages below 350 °C. These properties suggest that the BLT films should be a new candidate material for FRAM.

Graphene has been considered as a candidate for interconnect metal due to its high carrier mobility and current drivability. In this letter, the breakdown mechanism of single-layer chemical-vapor-deposited (CVD) graphene and triple-layer CVD graphene has been investigated at three different conditions (air exposed, vacuum, and dielectric capped) to identify a failure mechanism. In vacuum, both single- and triple-layer graphenes demonstrated a breakdown current density as high as ~108 A/cm2, which is similar to that of exfoliated graphene. On the other hand, the breakdown current of graphene exposed to air was degraded by one order of magnitude from that of graphene tested in vacuum. Thus, oxidation initiated at the defect sites of CVD graphene was suggested as a major failure mechanism in air, while Joule heating was more dominant with dielectric capping and in vacuum.

We present experimental demonstration that the thermal unstability grows with reducing the width of Pt/CoFe/Pt nanowires on the way to the superparamagnetic transition. The magnetic hysteresis loops measured at room temperature using a magneto-optical Kerr effect system reveal that the coercive field decreases drastically when the nanowire width is reduced smaller than 160 nm. To understand the origin of the coercive field reduction, the coercive field is measured with varying the sweep rate of the external magnetic field and then, analyzed with a thermally-activated magnetization reversal model. It is revealed that the reduction of the coercive field is mainly ascribed to the decrement of the thermal stability parameter, which in turn induces the abrupt reduction of the retention time down to a few seconds.

We experimentally demonstrate the current-induced domain wall motion in [CoFe/Pt]5 nanowire with perpendicular magnetic anisotropy. By use of the scanning MOKE measurement, we observe that two domain walls are moved simultaneously by spin polarized current at the current density of 1.43 times 1012 A/m2. The domain wall speed is estimated to be about 1.5 m/s, determined by the domain wall displacement (750 nm) and the current pulse duration (500 ns). From in situ resistance measurement, the temperature of the nanowire rises up to 700 K when the domain wall moves at such the high current density.

In this paper, we experimentally characterize the domain-wall depinning mechanism at notches of ferromagnetic nanowires with perpendicular magnetic anisotropy. A time-resolved magneto-optical Kerr effect detection reveals that the depinning time is exponentially proportional to the strength of external magnetic field. From an analysis based on Neacuteel-Brown theory, the depinning field and the activation volume are quantitatively determined for several notches with different gap distances. Interestingly, both the depinning field and the activation volume are proportional to the inverse of the gap distance. This is explained by the sizeable extrinsic effect from geometric constrictions in contrast to the intrinsic properties of the films.

Critical scaling behavior of magnetic domain interfaces is experimentally investigated in Pt/CoFe/Pt single-layer film (type I) and (CoFe/Pt)4 multilayer film (type II). Even though both samples exhibit domain wall propagation with rare nucleation, the domain interface profile is found to be very contrasting. Typical overhanging interfaces, in contrast to smooth interfaces in type I film, are observed in type II film. Both types of the interface profiles obey power laws. In log-log scaling plot of the roughness with respect to the interface segment length, the slopes, i.e., the scaling exponents, are estimated to be 0.66 plusmn 0.02 and 0.98 plusmn 0.03 for type I and II films, respectively. These values of the scaling exponents correspond to two distinct criticality classes of the self-affine and self-similar regimes in random-field Ising model, respectively.

Resistive memory switching devices based on transition metal oxides are now emerging as a candidate for nonvolatile memories. To visualize nano-sized (10 nm to 30 nm in diameter) conducting filamentary paths in the surface of NiO thin films during repetitive switching, current sensing–atomic force microscopy and ultra-thin (

We report on studies of the resistance switching behaviors of Pt/NiO/Pt structures, whose 60-nm-thick NiO thin films were formed by the thermal oxidation of Ni films. X-ray diffraction studies showed that a single-phase NiO film was obtained and that its lattice constant was very close to that of the bulk. Current–voltage characteristics exhibited reproducible resistance switching under a unipolar bias voltage. The switching voltage and current for the thermally grown NiO thin films did not show large variation in the oxidation temperature range, 350–550 °C.

Reliability studies of localized oxide–nitride–oxide memory (LONOM) devices are presented. The observed reduction in channel threshold voltage as a result of the retention charge loss of a programmed cell is demonstrated in terms of vertical leakage paths. Despite the apparent controversy of charge transport with nitride read-only memory (NROM) devices, the vertical paths are evidently observed via the channel and junction threshold voltage changes, which were monitored using Ids–Vds curves and gate-induced drain leakage (GIDL) measurements, visualizing the internal status of interface charges and stored charges in a nitride layer.

The resistance switching behavior and switching mechanism of nonstoichiometric zirconium oxide thin films were investigated for nonvolatile memory application. The Pt/ZrO/sub x//p/sup +/-Si sandwich structure fabricated by reactive sputtering shows two stable resistance states. By applying proper bias, resistance switching from one to another state can be obtained. The composition in ZrO/sub x/ thin films were confirmed from X-ray photoelectron spectroscope (XPS) analysis, which showed three layers such as top stoichiometric ZrO/sub 2/ layer with high resistance, transition region with medium resistance, and conducting ZrO/sub x/ bulk layer. The resistance switching can be explained by electron trapping and detrapping of excess Zr/sup +/ ions in transition layer which control the distribution of electric field inside the oxide, and, hence the current flow.