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The safety of converters is key to the stable operation of AC/DC hybrid power grids after AC faults. Thyristor valve current is a direct manifestation of the converter observability, but there are no measuring elements inside the converter, so the thyristor valve current can be reflected only indirectly through external electrical quantities. This paper proposes a virtual measurement scheme based on the temporal features of the converter terminal current. First, under the action of the trigger pulse, the polarity characteristics of the AC current and temporal features between the valves are utilized to predictive estimate the valve state. Then, when commutation failures occur and the bypass paths form, the conduction state of valve is constructed based on the relationship between AC and DC current. Last, when the valve is to be shut-off in the bypass path, the blocking state of the valve is corrected based on the unidirectional conductance characteristics of the valve. According to the above analysis, combined with the topological current equation of the converter, the valve current can be calculated in the whole process. Through the simulation of the different valve states and bypass paths and analysis of the field record data, the results show that the valve current can still be accurately calculated based on the virtual measurement scheme. [ABSTRACT FROM AUTHOR]

Most microgrid protection schemes found in published literature suffer from a lack of generality in that they work well for the assumed topology, including type and placement of sources. Other generic protection schemes tend to be too complicated, too expensive, or both. To overcome these drawbacks, a topology-agnostic, scalable, and cost-aware protection based on fundamental principles that work in the presence of high penetration of inverter-based resources (IBRs) is developed and tested in this paper. The protection system also implements stable automatic reconfiguration of the healthy sections of the system after clearance of fault, thus increasing resilience by self-healing. To achieve this ambitious goal, stable inverter models are developed that operate in unbalanced networks in grid-connected and islanded modes, even with 100% IBRs, share power without conflicting controls, and can ride through faults while limiting fault currents. The scheme is tested for primary and backup protection and reconfiguration on the IEEE 123-node feeder in grid-connected and islanded modes with 15 IBRs connected to the system. [ABSTRACT FROM AUTHOR]

Miniaturization and low cost contribute to the development and popularization of wireless power transfer (WPT). Reducing the number of power conversion stages can reduce the volume and cost of the WPT converter, and even make it possible to improve the efficiency. A single-stage WPT converter with constant current (CC) and constant voltage (CV) output and its asymmetric modulation method are proposed in this paper. A direct AC-AC converter is applied to the primary side of the WPT converter to directly convert line-frequency AC to high-frequency AC. The applied direct AC-AC converter that can replace the commonly used multi-stage primary converter reduces the number of circuit devices, thereby reducing the volume and cost of primary converter. The proposed WPT converter can realize zero voltage switching (ZVS) and power factor correction (PFC). In order to achieve CC and CV output, a switchable hybrid compensation topology is applied to the proposed WPT converter. A 720-W experimental prototype was manufactured to verify the rationality of the proposed WPT converter and the correctness of the theoretical analysis. [ABSTRACT FROM AUTHOR]

This paper proposes a novel polygonal voltage space vector structure (SVS) having 30 sides, for a star-connected induction motor drive. The SVS eliminates the presence of harmonics up to 25th order from motor phase voltage throughout the entire modulation range, providing a torque profile devoid of lower order pulsations. Linear modulation is extended till 99.63% of base speed without exceeding the motor phase voltage rating. Topology consists of a dc-link fed primary inverter and two equal low voltage modular capacitor fed secondary inverters. Here the harmonics generated by the primary inverter is canceled by the secondary inverter which acts as a switched capacitive filter. Detailed description of the SVS generation and timing calculations are provided in this paper. Effectiveness of the proposed scheme is validated using experimental results, inverter loss calculations, and harmonic analysis. [ABSTRACT FROM AUTHOR]

Four-level hybrid-clamped inverter is a newly proposed topology that can operate under a wide voltage range without switches connected in series. However, when it is applied in medium voltage high power conversions, the flying capacitors in each phase will occupy a huge volume and a high switching frequency is required to restrain the voltage ripples. In order to overcome this drawback, a four-level active neutral-point clamped inverter is discussed in this paper, which consists of only six switches and no diodes or flying capacitors are required. In order to balance the neutral-point voltages under the full power factor and modulation index range, a capacitor voltage balance method based on carrier-overlapped pulsewidth modulation is proposed in this paper. The upper and lower dc-link capacitor voltages are balanced by zero-sequence voltage injection and the central dc-link capacitor voltage is balanced by adjusting the duty cycles of switching signals slightly. Simulation and experimental results are presented to confirm the validity of this method. [ABSTRACT FROM AUTHOR]

This paper presents a 5-level inverter topology for open-end induction motor drives by using a single dc source. The open stator windings of the drive are supplied with a 3-level flying capacitor inverter from one end and capacitor-fed 2-level inverter from another end. The voltage ratio of the dc link to the capacitor in 2-level inverter is maintained at 4:1 ratio to generate five-level voltage output. The capacitor in 2-level inverter is balanced by the switching redundant vector combinations from both the inverters while the floating capacitors in the 3-level inverter are balanced by using redundant switching states. The proposed topology gives 5-level operation with less number of floating capacitors and power semiconductor switches compared to other existing topologies. Also, the balancing of the capacitors is independent of load power factor and modulation index. Further, the generalization of the proposed dual inverter scheme for any n-level inverter is also included in this paper. The experimental results and required analysis are also presented to validate the inverter scheme. [ABSTRACT FROM AUTHOR]

In this paper, many impedance-source inverters with coupled inductors have been investigated to obtain a high step-up boost ratio. However, the leakage inductors in these topologies induce great voltage spikes at the dc link, which will increase the voltage stress of switches. Thus, the power level of inverters is limited. Furthermore, the efficiency of the inverters can be degraded by the losses associated with leakage inductors. To address abovementioned issues, this paper proposes a family of low-spike high-efficiency Y-source inverters. The proposed inverters have the ability of eliminating voltage spikes at the dc link and recycling the leakage energy via the additional diode and capacitor. In order to show the excellent characteristics of the proposed topologies, this paper compares the performances of the proposed inverters and the improved-Y-source inverter in many aspects. Simulation and experimental results have verified the abilities of the proposed inverters. [ABSTRACT FROM AUTHOR]

Multilevel inverters (MLIs) are playing a pivotal role in the power sector with potential applications, such as interfacing renewable energy sources with the grid and several industrial drive applications. MLIs with a smaller number of switching devices are more promising due to their compact size, reduced cost, and higher efficiency compared with their traditional counterparts. This paper, therefore, presents a new three-phase seven-level inverter. This topology is a combination of two cascade-connected two-level voltage-source inverters (VSIs) and H-bridge cells with flying capacitors (FCs). This paper presents the operating principle and the balancing technique for the dc-link capacitors and FCs. The generation of various output voltage levels and the limitation of the sinusoidal pulsewidth modulation control for FC voltage balancing is also presented. The number of components in the proposed circuit configuration and their voltage ratings are considerably lower compared with the recently proposed topologies. The behavior of the proposed circuit configuration is first assessed with simulation studies and is then tested with a laboratory prototype. The simulation and experimental results validate the effectiveness of the proposed topology and the voltage balancing technique. [ABSTRACT FROM AUTHOR]

This paper presents a novel seven-level inverter topology for medium-voltage high-power applications. It consists of eight active switches and two inner flying capacitor (FC) units forming a similar structure as in a conventional active neutral-point-clamped (ANPC) inverter. This unique arrangement reduces the number of active and passive components. A simple modulation technique reduces cost and complexity in the control system design without compromising reactive power capability. In addition, compared to major conventional seven-level inverter topologies, such as the neutral point clamped, FC, cascaded H-bridge, and ANPC topologies, the new topology reduces the dc-link voltage requirement by 50%. This recued dc-link voltage makes the new topology appealing for various industrial applications. Experimental results from a 2.2-kVA prototype are presented to support the theoretical analysis presented in this paper. The prototype demonstrates a conversion efficiency of around 97.2% ± 1% for a wide load range. [ABSTRACT FROM AUTHOR]

Multilevel inverters (MLIs) are being used in wide range of power electronic applications. These converters have attracted a lot of attention during recent years and exist in different topologies with similar basic concepts. This paper presents five main submodules (SMs) to be used as the basic structures of MLIs. The paper reviews the common MLI topologies from the structural point of view. The topologies are divided into the different SMs to show conventional MLI configurations and future topologies that can be created from the main SMs. A comparative study between different topologies is performed in detail. The MLIs are categorized and investigated with from different perspectives such as the number of components, the ability to create inherent negative voltage, working in regeneration mode and using single dc source. [ABSTRACT FROM AUTHOR]

Reduced switch active phase converters (APC) are cost-effective solutions for running three-phase loads from single-phase grids. This paper proposes a novel auxiliary-capacitor-based APC (AC-APC) for this application. The combination of the topological location of the auxiliary capacitor and the control of the AC-APC reduces current stress on the semiconductor devices. In this paper, a selection criterion for the optimal auxiliary capacitor value is formulated to reduce the device currents in such a way that the overall efficiency is enhanced. This paper presents a comparative analysis of converter volt-ampere (VA) rating and device power loss for conventional H-bridge active front-end and inverter-based topology, APC, and AC-APC. To evaluate the efficacy of the proposed AC-APC, an experimental study is conducted on the APC and the AC-APC feeding a 3-hp three-phase induction motor. At a full load of $\text{2.5}\,\text{kW}$ and $\text{0.8 } \text{power factor}$ , the measured maximum efficiency of the AC-APC is $2\%$ higher than that of the APC. Analytical evaluation of converter currents and device power loss are in close agreement with experimental observations. [ABSTRACT FROM AUTHOR]

In low-power applications of photovoltaic (PV) systems, the transformerless grid-connected inverters have been preferred to increase the efficiency and reduce the cost, size, and power losses when they are compared to the ones with the transformer. A transformerless single-phase inverter topology with a single dc-link capacitor for the grid-connected PV systems is proposed in this paper. The proposed inverter has been simulated by using a cooperation process of the MATLAB and SPICE package programs and it has been implemented for experimental verification. The proposed inverter reduces the high-frequency common-mode leakage current caused by parasitic capacitances of PV panels, whereas it is controlled with the unipolar sinusoidal pulsewidth modulation. Also, the results show that the common-mode voltage remains constant. The efficiency of the proposed inverter has been compared to that of the most common topologies having the dc-link decoupling during the zero voltage states. This paper is accompanied by a video file demonstrating the power loss distribution in the inverter. [ABSTRACT FROM AUTHOR]

This paper describes a dc-link voltage control method of a single-phase back-to-back cascaded H-bridge inverter (SBCI) for a medium-voltage motor drive system. The main advantage of the SBCI topology over the conventional regenerative cascaded H-bridge topology with a three-phase active front-end (AFE) is a simple system structure, which is composed of an input transformer, a power cell, a current sensor, etc. However, the challenging points of the SBCI are larger voltage ripple in the dc-link capacitor and imbalance of dc-link voltages of each phase. The asymmetric dc-link voltage of each power cells could cause unstable operation such as over-modulation due to the lack of the dc-link voltage of a particular phase and result in over-voltage or under-voltage faults. In this paper, the control strategy of the dc-link voltage for the SBCI that uses the negative-sequence voltage of the converter is described. The proposed control method is verified with a computer simulation whose target is a 6.6-kV–1.25-MW medium-voltage drive system. Also, through the experimental setup with the prototype SBCI whose power rating is 16.2 kVA, the dc-link voltage of each AFE has been controlled within a 0.5% error of its reference value at the full load. [ABSTRACT FROM AUTHOR]

This paper presents a new single-source three-phase seven-level inverter with an inherent three-time voltage boosting capability for medium-voltage applications. The proposed topology is comprised of series connection of two switched-capacitor (SC) networks with an added half-bridge module per phase. Each of such integrated SC networks requires a single capacitor associated with three active power switches. The three-time voltage boosting feature of the proposed topology can reduce the dc-link voltage requirements by 50% in comparison to the traditional neutral point clamped (NPC), flying capacitors, active NPC (ANPC), hybrid clamped ANPC, and cascaded H-bridge topologies, and 75% to advanced ANPC topologies. It can also reduce the number of required switches and capacitors as well as their voltage stresses compared to those state-of-the-art topologies reported in the literature. By integrating “n” number of added SC networks in the proposed seven-level basic topology, the number of output voltage levels can be extended to 2n+3 per phase. A finite control set model predictive control algorithm is also derived to control the converter in both the active and reactive power exchanges modes without distorting the generated grid current quality. The capacitor voltage balancing is inherent in the proposed topology, and thus, there is no need for any additional voltage balancing circuit, which further reduces the control complexity. The performance of the proposed topology and its control algorithm are validated by several measurement results. [ABSTRACT FROM AUTHOR]

Enhancement of dc bus voltage utilization for a five-level inverter with single dc source and capacitor-fed H-bridge (CHB) units is investigated in this paper. A carrier-based modulation technique is used for boosting the dc bus utilization, which is established by providing detailed mathematical analysis. The five-level inverter used here is realized by cascading a CHB unit to each phase of a three-level neutral point clamped inverter. The increase in dc bus voltage utilization owes to the pole voltage redundancies offered by CHB units. The floating capacitors of H-bridge units are balanced within a quarter fundamental cycle using the switching state redundancies of pole voltage levels. The aforementioned modulation technique allows the inverter to enhance the dc bus utilization from 0.577 $\text{V}_{\text{dc}}$ to 0.63 $\text{V}_{\text{dc}}$ under unity power factor. This enhancement is obtained in the linear modulation range without increasing the dc bus voltage, and thus, the inverter can operate without the presence of low-order harmonics in its phase voltages. The strength of this paper lies in its detailed mathematical analysis for finding out the limiting modulation index and power factor condition in the light of floating capacitor voltage balancing issue. Simulation as well as experimental verification of the modulation scheme is carried out on an induction motor drive under various operating conditions. It is shown that this carrier-based modulation technique is suitable for any single source inverter topology with one CHB unit per phase. [ABSTRACT FROM AUTHOR]

This paper proposes a novel method for instantaneous balancing of neutral-point (NP) voltages with stacked multilevel inverters (MLIs) for variable-speed drives. The stacked MLI uses series-connected dc sources and NPs (connecting points of dc sources) to obtain the desired levels. The balancing of NP voltages are obtained by using a low-voltage-capacitor-fed cascaded H-bridge (CHB) per phase of a symmetrical six-phase induction machine (IM), which ensures zero current drawn from NPs (at any given instant). Since no current is drawn from NPs, the single dc-link operation with stacked capacitors is also possible. The scheme is suitable for applications, where low-voltage dc sources and batteries are stacked to form a dc link. A variable-speed operation is done using a seven-level inverter scheme for a symmetrical six-phase IM, which is formed by three dc-link stacked capacitors cascaded with two low-voltage-capacitor-fed CHBs per phase. Furthermore, the method is extended for an open-end IM to obtain a seven-level common-mode eliminated space vector structure using a single dc link. The generalization of this method for any stacked $n$ -level inverter without NP voltage deviation is also presented in this paper. The experimental results and analysis are included to validate the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents a novel single-stage soft-switched high-frequency-link three-phase dc–ac converter topology. The topology supports unidirectional dc to ac power flow and is targeted for applications like grid integration of photovoltaic sources, fuel cell, etc. The high frequency magnetic isolation results in reduction of system volume, weight, and cost. Sine-wave pulsewidth modulation is implemented in dc-side converter. Though high-frequency switched, dc-side converter is soft switched for most part of the line cycle. The ac-side converter active switches are line frequency switched incurring negligible switching loss. The line frequency switching of ac-side converter facilitates use of high voltage blocking inherently slow semiconductor devices to generate high voltage ac output. In addition, a cascaded multilevel structure is presented in this paper for direct medium-voltage ac grid integration. A detailed circuit analysis considering nonidealities like transformer leakage and switch capacitances, is presented in this paper. A 6-kW three-phase laboratory prototype is built. The presented simulation and experimental results verify the operation of the proposed topologies. [ABSTRACT FROM AUTHOR]

This paper proposes a new dc–ac converter with a reduced number of semiconductor switches and gate drive and control circuit components. A salient feature of this inverter is its pure sinusoidal line-to-line voltages with no need for output filter. Also, the proposed inverter improves the voltage utilization factor of the input dc supply compared to the four-switch three-phase inverter (first best topology in the literature from the number of switches point of view) and standard six-switch inverter with sine pulsewidth modulation. The proposed inverter is capable of operating with a wide range of output voltages from zero to the full value of the dc input voltage by appropriately altering the instantaneous duty cycle. A three-phase universal inverter with only three power switch has been proposed in this paper for the first time ever, to our knowledge. For the purpose of providing a good compromise between fast transient response and stability, a model predictive controller is proposed. All the design expressions have been derived. A comparison with other dc–ac converters is given to show the merits of the proposed converter. Finally, satisfactory circuit operation is confirmed by experimental results from a laboratory prototype. [ABSTRACT FROM AUTHOR]

This paper presents the digital implementation of a boundary controller with unipolar switching characteristic for single-phase voltage source full-bridge inverters. This paper expands the application of a second-order switching surface-based control method to unipolar switching of single-phase voltage source inverters (VSIs) using a finite-state machine. The finite-state machine has been formulated considering four different states of the inverter; positive,zero1, negative, andzero2. The second-order boundary control governs the current state of the system and provides proper switching action to keep the system within the desired reference. The control law is implemented digitally in F28m35x digital control card. A full-bridge inverter topology is used to achieve the three-level voltage switching. Various simulations and experiments were performed in a 550 VA, 120 V, 60 Hz VSI with a digitally implemented controller to verify the theoretical predictions. A high-quality voltage output was obtained for various loading conditions. The transient performance of the controller was investigated using a reference and load changes. A comparison of the implementation was made with the existing classical controllers to verify the fast-dynamic response of the system. [ABSTRACT FROM AUTHOR]

This paper presents a unified framework for the modeling, analysis, and design of load-independent Class E and Class EF inverters and rectifiers. These circuits are able to maintain zero-voltage switching and, hence, high efficiency for a wide load range without requiring tuning or use of a feedback loop, and to simultaneously achieve a constant amplitude ac voltage or current in inversion and a constant dc output voltage or current in rectification. As switching frequencies are gradually stepping into the megahertz (MHz) region with the use of wide-bandgap (WBG) devices such as GaN and SiC, switching loss, implementing fast control loops, and current sensing become a challenge, which load-independent operation is able to address, thus allowing exploitation of the high-frequency capability of WBG devices. The traditional Class E and EF topologies are first presented, and the conditions for load-independent operation are derived mathematically; then, a thorough analytical characterization of the circuit performance is carried out in terms of voltage and current stresses and the power-output capability. From this, design contours and tables are presented to enable the rapid implementation of these converters given particular power and load requirements. Three different design examples are used to showcase the capability of these converters in typical MHz power conversion applications using the design equations and methods presented in this paper. The design examples are chosen toward enabling efficient and high-power-density MHz converters for wireless power transfer (WPT) applications and dc/dc conversion. Specifically, a 150-W 13.56-MHz Class EF inverter for WPT, a 150-W 10-MHz miniature Class E boost converter, and a lightweight wirelessly powered drone using a 20-W 13.56-MHz Class E synchronous rectifier have been designed and are presented here. [ABSTRACT FROM AUTHOR]

This paper proposes generation of a 15-level (14 concentric) dodecagonal voltage space vector structure (DVSVS) for a star connected induction motor drive. The proposed multilevel DVSVS is obtained by cascading two inverters, namely a primary and secondary inverter. The primary inverter is a five-level (5L) structure formed by stacking two three-level flying capacitors with individual reduced dc sources and the secondary inverter is also a 5L structure formed by cascading two capacitor-fed cascaded H-bridges (CHB). The active power is supplied by the primary inverter, while the secondary inverter acts as switched capacitor harmonics filter, and capacitors in the secondary inverter are balanced naturally irrespective of load power factor for entire modulation index. The high-voltage dc supply fed primary inverter is operated in quasi-square wave mode, while the high frequency switching is applied to low voltage CHBs, thus, reducing the overall switching loss. The proposed scheme gives the advantages of both DVSVS and multilevel structure, thus, making it one of the solutions for battery or stacked dc-fed applications. The paper also presents the experimental results as well as comparison study with the existing topologies to support the advantages of proposed scheme. [ABSTRACT FROM AUTHOR]

Fast-switching power converters are a key enabling technology for the more electric aircraft (MEA), but the generated electromagnetic interference (EMI) poses significant challenges to the electrification effort. To meet the stringent aerospace EMI standards, passive filters are commonly employed, despite the weight and size constraints imposed by the MEA. Alternatively, the EMI source, i.e., the high dv\text/ dt and di\text/ dt slew rates, can be addressed through waveform-shaping techniques. For example, while most soft-switching converters can reduce switching loss, they do so by switching the semiconductor devices in a slower and smoother manner, resulting in the attenuation of high-frequency harmonics. This paper examines the auxiliary commutated pole inverter (ACPI) topology, and its first contribution is the attenuation of the high-frequency content of its EMI source, that is, the output voltage, in a predictable manner, through the active control of the resonant circuit. This is achieved by first, discussing the time-domain characteristics of trapezoidal and S-shaped pulse-trains that lead to attenuated high-frequency harmonic content, and second, by analyzing the equivalent LC circuit of the ACPI. The design of the inverter is then focused on the active control of the resonant parameters, for a predetermined and enhanced output voltage high-frequency response. The second contribution of this paper is the comparison of the EMI performance of hard switching and of three soft-switching modes, fixed-timing control, variable-timing control, and capacitive turn-offs, and how this informs important metrics such as power efficiency, current stress, and implementation complexity. Finally, the third contribution is on the trade-offs that arise when the primary design goal is enhanced EMI performance as opposed to switching loss reduction. A 5-kW, 3-phase ACPI prototype is used for validating the high-frequency content attenuation at source. It is shown that the ACPI can achieve a 37 dB harmonic attenuation of its output voltage at 4 MHz, compared to a hard-switched inverter. [ABSTRACT FROM AUTHOR]

To support the development of high-frequency ac microgrids in terms of compact design, high-voltage gain and low total harmonic distortion (THD), a buck–boost dual-leg-integrated step-up inverter is proposed in this paper. The inverter is formed by integrating a buck–boost converter into a conventional single-phase full-bridge inverter by sharing the upper switch and the body diode of the lower switch in both bridge-legs. Consequently, the component count is significantly reduced over the step-up inverter counterparts. In addition, to address the drawbacks of hybrid modulation methods adopted by existing dual-leg-integrated inverters, such as double-variable control, and high THD of output voltage/current at high input voltage and heavy load conditions, unipolar frequency doubling sinusoidal pulse width modulation scheme is adopted in this inverter. As a result, the modulation ratio M becomes the only control variable to regulate the output voltage/current and the control is simplified. The THD of the proposed inverter output can remain low throughout the entire input voltage range and load power range. This paper presents the topology derivation procedure, operation principle, and steady-state characteristics of the proposed inverter. To validate the effectiveness of theory, experimental results of a 400 W hardware prototype, where the output voltage frequency is at 500 Hz, are reported. [ABSTRACT FROM PUBLISHER]

In this paper, two structures are proposed for the switched-inductor quasi-Z-source inverter. In the proposed structures to extend the voltage gain of inverter, two new switched-inductor structures are used. In the proposed structures, voltage across the capacitors in the Z-source network and in the switched-inductor is symmetric and small. The other advantage of proposed inverters is known as achieving higher voltage gain per smaller duty cycle ratio (of shoot-through). Compared with a conventional continuous input current switched-inductor quasi-Z-source inverter at the same gain voltage, there is less of a ripple of input current in the proposed inverters. In this paper, at first the both the conventional and the proposed switched-inductor Z-source inventers are thoroughly investigated to find out their governing relations. Then, the proposed Z-source inverters are compared with the conventional ones by simulating them to assess their performance efficiency. Next, applying the simple boost pulse width modulation the simulation is carried out with PSCAD/EMTDC software. After that, to evaluate the obtained results, the prototypes of the proposed inverters with 48 Vdc input voltage are used. [ABSTRACT FROM PUBLISHER]

This paper analyzes the combination in a cascaded H-bridge multilevel inverter (CHBI) based on transformers with the different turn ratios for increasing the voltage level and proposes the switching method for achieving the output voltage distribution among H-bridge cells (HBCs). The transformers used in this paper are connected to the output of the respective HBCs, and the secondary sides of all the transformers are connected in series for generating the final output voltage. Only one of the transformers, in particular, has a different turn ratio for increasing the output voltage level. In this paper, the possible turn ratio of the special transformer with a different turn ratio is discussed in detail, and a switching method based on the level-shifted switching method for the topology used in this paper is proposed. To verify the effectiveness of the proposed method, a three-phase 21-level CHBI is experimentally tested. [ABSTRACT FROM PUBLISHER]

This paper presents the tradeoff study of heat sink and output filter volume of a GaN HEMT based single-phase inverter. The selected topology is three-level active neutral point clamped (ANPC) inverter, and the main aim is to explore the benefits of the GaN HEMTs at 600 V blocking class on the system level efficiency, and power density under the wide range of operating conditions. The paper starts by introducing the inverter topology, selected pulse width modulation scheme and followed by the device features, static, and dynamic characterization and continues with presenting and discussing the results of extensive experimental and analytical characterization. After this, the impact of GaN HEMTs on inverter volume is discussed in terms of heat sink and output filter volume analysis under different switching frequency and heat sink temperature conditions. The calculation of heat sink volume and single stage LC output filter volume are presented with respect to experimental results of the single phase prototype. The findings from static, dynamic characterization, and single phase prototype results clearly show that GaN HEMT has excellent switching performance under wide load current and heat sink temperature conditions. The high performance of the inverter leads to reduction of the combined total volume, including output filter and heat sink volume. [ABSTRACT FROM AUTHOR]

This paper presents a new multilevel converter topology based on a variable or multilevel dc-link stage. This stage is shared by all inverter output phases, thus increasing the number of output voltage levels while reducing the overall number of active devices compared to traditional topologies; therefore, it is called a reduced multilevel converter (RMC). The converter is not capable of reducing the blocking voltage of the devices; hence, unlike other multilevel converters aimed at medium-voltage applications, this converter is interesting for low-voltage- and high-power-quality-demanding applications such as photovoltaic inverters, wind energy conversion systems, and uninterruptible power supplies. The main novelty behind the proposed concept is the basic dc cell used to generate the variable dc-link voltage, which includes a controlled path through the floating capacitors to provide the necessary degree of control to enable a shared multilevel dc link for all the output phases of the converter. The dc cells are connected in a multicell structure to increase the number of levels of the converter. A five-level version of the RMC topology is briefly compared to other five-level converters such as the five-level active neutral-point-clamped converter and the five-level flying capacitor converter. This paper presents the structure of the new topology with its operating principle, switching states, main characteristics, and experimental validation using finite-control-set model-predictive control. [ABSTRACT FROM PUBLISHER]

This paper proposes a current-fed single-phase inverter without constant intermediate DC link. It eliminates electrolytic capacitor from the DC-link and introduces an intermediate pulsating DC bus. The proposed topology is modular with three full-bridges making it scalable for high-power applications. New pulsating-DC-modulation for back-end pulsating DC-link inverter and secondary modulation (SM) for front-end DC-to-pulsating DC converter is proposed. Soft-switching and device voltage clamping of both primary side and secondary side devices of front-end current-fed full-bridge converter is realized. A rotating partial hybrid pulsewidth modulation has been introduced. One leg of inverter is commutated at a low switching frequency, while the other leg is operated at a high switching frequency for partial period of a line frequency cycle. Thus, switching losses of the back-end inverter are considerably reduced. Rotating mechanism is used to equalize the switching losses of four switches of the inverter. This paper presents detailed operation and analysis of the topology with a proposed modulation scheme. Simulation and experimental results validate the effectiveness and accuracy of the proposed modulation scheme as well as soft-switching and performance of the converter. [ABSTRACT FROM PUBLISHER]

In this paper, new half-bridge and full-bridge topologies for a switched-boost inverter are proposed. These topologies have a high boost factor in comparison with conventional types. In addition, the proposed topologies have continuous input current and can generate zero-voltage level in output. In this paper, the operation of the proposed inverters in different operating modes is analyzed. Then, the values of inductors and capacitors are designed. Moreover, the used switching pattern and its logical diagram are introduced. A comprehensive comparison between the proposed and conventional topologies in terms of the boost factor, the number of elements, and the efficiency shows the good features of the proposed inverters. Finally, to verify correct operation of the proposed topologies and derived equations, simulation and experimental results are presented. [ABSTRACT FROM AUTHOR]

In this paper, direct torque control (DTC) of five-phase induction motor (FPIM) is implemented using three-level neutral point clamped (TL-NPC) inverter. One of the advantages of three-level inverter over two-level one for DTC operation is the low torque ripple. Also TL-NPC inverter through space vector modulation technique gives low $ dv/dt$ transition with better voltage waveform. By applying conventional lookup table for DTC, the TL-NPC inverter does not ensures lower $dv/dt$ transition. In this paper, a novel switching scheme for DTC of FPIM using TL-NPC inverter is proposed that ensures the low $ dv/dt$ transition and balancing of dc-link capacitor voltages of TL-NPC inverter. To form the lookup table for DTC operation, instead of using voltage vectors directly, virtual vectors (VVs) are utilized. Two switching states are used in one sample time to generate a VV in $\alpha \beta$ plane, which gives zero resultant voltage in $ xy$ plane. The switching strategy ensures low number of transitions to reduce the switching losses. The switching state redundancies are used in a novel way to balance the dc-link capacitor voltages without using any additional hardware. The proposed technique to balance the dc-link capacitor voltage gives lower switching frequency. The MATLAB/Simulink environment is used for the simulation and the results are validated through experiments. [ABSTRACT FROM AUTHOR]

This paper proposes and validates model predictive control as an alternative control strategy for H-bridgeneutral-point-clamped (H-NPC) converters for single-phase grid-tied string photovoltaic (PV) systems. The presented control scheme achieves good quality current waveforms with unity power factor, dc-link voltage control, and neutral-point voltage minimization. Furthermore, the predictive controller has been further enhanced by including an average device switching frequency restriction and a $dv/dt$ mitigation. The main contribution of this paper is the avoidance of the potential leakage current due to parasitic capacitance of the PV modules by using a predictive model based control technique instead of modulated schemes and eliminating high-frequency common-mode voltage components. Experimental results during steady state and dynamic operation are presented to illustrate the behavior of the H-NPC converter commanded by the proposed control scheme. [ABSTRACT FROM AUTHOR]

Finite state model predictive control (MPC) has been recently applied to several converter topologies, as it can provide many advantages over other MPC techniques. The advantages of MPC include fast dynamics, multitarget control capability, and relatively easy implementation on digital control platforms. However, its inherent variable switching frequency and lower steady-state waveform quality with respect to standard control, which includes an appropriate modulation technique, represent a limitation to its applicability. Modulated model predictive control (M2 PC) combines all the advantages of MPC with the fixed switching frequency characteristic of pulse-width modulation algorithms. The work presented in this paper focuses on the indirect matrix converter (IMC), where the tight coupling between rectifier stage and inverter stage has to be taken into account in the M2PC design. This paper proposes an M2PC solution, suitable for IMC, with a switching pattern that emulates the desired waveform quality features of space vector modulation for matrix converters. The switching sequences of the rectifier stage and inverter stage are rearranged in order to always achieve zero-current switching on the rectifier stage, thus simplifying the current commutation strategy. [ABSTRACT FROM AUTHOR]

In this paper, it is described how the circulating current flows between inverters that have isolated dc link such as cascaded H-bridge (CHB) topology when they are operating in parallel. In this case, zero sequence circulating current, which normally flows through shared dc link, cannot flow between inverters in parallel. However, circulating current is provoked by asynchronous switching instant of devices, difference of dc-link voltages of parallel inverters, and unbalanced impedance. The circulating current should be suppressed by a sharing inductor that is inserted between inverters. Generally, all of the inverters should synthesize the same output voltage reference for load current control to minimize the size of this sharing reactor. However, this conventional method cannot guarantee diminishing circulating current in the transient state and even in the steady state. In this paper, in order to reduce sharing reactance, after deriving circulating current model from general case of n-parallel operation, circulating current control method is devised based on the model. This proposed algorithm is applied to active front end five-level-CHB inverter system for medium voltage drive. Simulation and experimental results are provided to verify the effectiveness of the proposed control scheme. [ABSTRACT FROM AUTHOR]

In this paper, two topologies are presented for the enhanced-boost quasi-Z-source inverters (qZSI), namely continuous input current configuration and discontinuous input current configuration of enhanced-boost qZSI with two-switched impedance networks. Similar to enhanced-boost impedance-source inverters (ZSIs), these proposed inverter topologies possess very high boost voltage inversion at low shoot-through duty ratio and high modulation index to provide an improved quality output voltage. Compared to enhanced-boost ZSIs with two-switched Z-source impedance networks, these proposed inverter topologies share common ground with source and bridge inverter, overcome the starting inrush problem, and draw continuous input current and the lower voltage across the capacitors. Moreover, the input ripple current is negligible. This paper presents the operating principles and analysis of continuous input current configuration enhanced-boost qZSI with two-switched impedance networks and compares with ZSI, switched inductor ZSI, DA/CA-qZSI, and enhanced-boost ZSIs. The theoretical analysis is done and is validated through simulation and experimental results. [ABSTRACT FROM PUBLISHER]

This paper proposes an effective sliding mode controller (SMC) for a grid-connected 7-level packed U-cell (PUC7) inverter. The aim is to design a simple controller that deals effectively with the complex control problem of the PUC7 inverter (multiobjective control problem). The selection of the control actions is achieved according to the system state error at every sampling time, regardless of the previous values, which makes the control technique model-independent. The control algorithm evaluates online two cost functions (one for each state error), which are derived on the basis of sliding mode theory, and it selects the optimal control input in order to satisfy the reaching conditions of the two cost functions. Compared with the existing solutions, the proposed SMC technique ensures lower average switching frequency by tuning the hysteresis bandwidth of the capacitor-voltage error. The fast implementation, needless of gains tuning, and simple design procedure are the main features of the proposed algorithm. Simulation and experimental results are presented to prove the effectiveness of the proposed technique in controlling the PUC7 inverter with high dynamic performance and robustness against disturbances and parameters mismatch. [ABSTRACT FROM AUTHOR]

This paper proposes a new multilevel inverter (MLI) topology that utilizes trinary sequence for the dc sources. It gives maximum output voltage level with minimum dc source and switch count when compared to other sequences, such as symmetric, natural, binary, and quasi-linear. This is due to the fact that the trinary sequence generates of all additive and subtractive combinations of input dc levels in the output voltage waveform. The concept is implemented on a 9-level asymmetric MLI using only four active devices. Multicarrier unipolar pulsewidth modulation technique is adopted to create the switching pulses. Theoretical calculation of total harmonic distortion in both voltage and current waveforms has been performed using asymptotic time domain formula. These values are compared with simulation and experimental values for different modulation indices. Power loss calculation for proposed topology is discussed with appropriate mathematical equations. [ABSTRACT FROM AUTHOR]

The conventional three-level inverter only has voltage buck capability. The quasi-Z-source three-level T-type inverter (QZS 3LT $^2$ I) has been proposed to realize voltage buck–boost operation. In this paper, we further propose a novel modulation scheme for the QZS 3LT $^2$ I to realize voltage boosting, reduce the common-mode voltage (CMV), and control the neutral-point voltage balance simultaneously. The proposed scheme adopts a large vector, a medium vector, a small vector with low CMV magnitude, a zero vector, and a shoot-through vector to generate the output voltage. According to sector number and neutral-point voltage difference, a p-type or n-type small vector with low CMV magnitude is properly selected to balance the neutral-point voltage. Shoot-through states are inserted within zero vector to boost the dc input voltage without affecting the ac output voltage. Dwell times of basic vectors are calculated through the revised volt–second balance equation. Furthermore, a coordinate control strategy between neutral-point voltage balance and voltage boosting is proposed. Doing so, the CMV magnitude can be restricted within one-sixth of dc-link voltage and neutral-point voltage imbalance can be effectively mitigated. The effectiveness of the proposed scheme is verified by simulations and experiments. [ABSTRACT FROM AUTHOR]

A novel nine-level inverter topology for low-voltage applications is proposed in this paper. Each phase of the inverter is composed of a T-type three‐level cell and an active neutral point clamp three‐level cell. The operation principles and current conduction paths are analyzed in detail and phase-disposition sinusoidal pulsewidth modulation is used to balance voltages of flying capacitors and neutral point. The mathematical relationship between the capacitance and the desired ripple in the inverter output is established to select the intermediate capacitance value. Compared with other nine-level inverters suitable for low-voltage applications, the proposed inverter has advantages in a number of gate drivers, a number of dc sources, and efficiency. Simulation and experimental results under different settings of modulation index, power factor, output frequency, and load are presented to verify the effectiveness and performances of the proposed inverter. [ABSTRACT FROM AUTHOR]

This paper presents a reduced component count five-level inverter topology based on the stacked cell approach to multilevel inverters. The proposed topology utilizes the fundamental properties of three-phase voltages to reduce the number of switches and flying capacitors to cut size, weight and costs while facilitating higher reliability, simpler wiring and lesser electromagnetic interference. The operational aspects of the topology such as circuit structure, modulation and capacitor balancing are explained, followed by an account of device stresses and reliability. A discussion of certain additional features such as fault tolerant operation, loss steering and common-mode elimination addresses the usefulness of the topology in practical situations. A comparison of the proposed topology with existing methods in terms of several parameters is then used to highlight its merits and features. Finally, experimental results obtained using an induction motor drive incorporating the topology are given, so as to validate the feasibility of the proposed approach. [ABSTRACT FROM AUTHOR]

T-type multilevel (T2ML) inverters feature low total harmonic distortion and high efficiency. Reliability improvement is particularly important for T2ML inverters because they have high power device count. Methods that provide T2ML inverters with the ability to tolerate simultaneous failures of multiple switches in several legs have not been addressed in the existing literature. This paper proposes a redundant unit that can be shared across phases in a T-type three-level inverter topology to manage open-circuit faults in multiple legs. The redundant unit includes two switches and six diodes, with the extra active switches connected by diodes to each middle switch of the base inverter. Under fault conditions, a standby parallel leg consisting of middle switches and the added redundant devices can be formed in each phase of the inverter to provide an extra current path connecting the dc bus and loads. The middle switches can share the redundant unit simultaneously to replace faulted half-bridge switches. By these means, open-circuit faults in multiple legs can be tolerated simultaneously and the rated output capacity can be maintained during faulted operation. Experimental tests are given to verify the effectiveness and feasibility of this proposed fault-tolerant method. [ABSTRACT FROM AUTHOR]

A multilevel drive can be realized by using an open-ended machine, fed from dual two-level inverters. The topology supplied from isolated dc sources is suitable for transportation electrification. In vehicular systems, it is essential that the isolated dc sources, comprising of battery packs, should discharge uniformly and maintain balanced dc voltage at the dc-link terminal. A simple carrier-based pulsewidth modulation (PWM) technique is presented in this paper, which can effectively regulate the power drawn between the two two-level inverters while maintaining the multilevel operation of the drive. The modulation technique can balance the instantaneous state of charge of independent battery packs and dynamically equalize the power flow from the two inverters, based on drive requirement. This will enhance the reliability of the propulsion system in electric vehicles. The operation of the proposed PWM technique has been validated through detailed simulation and experimental tests. [ABSTRACT FROM AUTHOR]

This paper proposes a new inverter topology based on the active neutral-point-clamped (ANPC) converter with capability to integrate one energy storage system (ESS) per inverter leg with an independent state of charge control, so that each inverter leg has two dc ports and one ac port. The primary dc port is common to all inverter legs and it is connected to the main power source. The secondary dc port is suitable for ESS connection because of its two-quadrant operation, with bidirectional current capability, so that the ESS can be charged and discharged with regulated current. Integration of a secondary dc port with independent control also allows the use of different ESS technologies for each inverter leg to compose a hybrid ESS. Redundant switching states of the proposed structure are used to balance the energy exchanged between the secondary dc port and the dc bus capacitors. Theoretical propositions were experimentally validated through a 1-kW single-phase inverter with a secondary dc port connected to a 230-V ESS and ac port connected to an LC filter feeding a linear load. Low total harmonic distortion (THD) sinusoidal current is generated at the ac port while charging or discharging the ESS with a constant current. [ABSTRACT FROM AUTHOR]

Transformerless inverters are getting popular in distributed photovoltaic power generation (PVPG) system due to its light weight, low cost, and higher efficiency in power conversion. However, the production of leakage current leads to severe electromagnetic interference and operational insecurity, which declines the reliability and efficiency of the overall system. Besides that many of the topologies have been addressed with real power injection capabilities in the literature. Therefore, in this paper, an improved hybrid-bridge (IH-B) inverter for transformerless PVPG system is proposed with 1) reduced leakage current by abolishing the fluctuations in common-mode voltage (CMV) due to switch junction capacitances and 2) reactive power capability with a modified sinusoidal pulsewidth modulation technique. This topology is constructed with the combination of bidirectional clamping branch and hybrid-bridge (H-B) inverter topology to maintain CMV at half of the dc-link voltage and ensure better quality of output waveforms at different power factors of the grid. Further, MATLAB simulation results of the IH-B and H-B topologies are presented and compared to prove the potential benefits of the proposed topology. Finally, a 500W prototype model is built and tested to validate the effectiveness of the IH-B topology in reduction of leakage current and reactive power capability. [ABSTRACT FROM AUTHOR]

Unipolar-pulsewidth modulation (UP-PWM) inverter takes advantages of high power efficiency and small output chokes which is widely used in the industry. However, UP-PWM inverters cannot be used in parallel operation due to a current unbalance problem. This paper studies the current unbalance problem of paralleled UP-PWM inverters with common dc bus and ac bus. First, the problem of unbalanced inductor current is defined and analyzed. Second, a technique to eliminate unbalanced currents is proposed. The proposed current balancing technique only requires one more current sensor in an inverter module rather than changing converter topology or modulation method, which makes it possible to apply UP-PWM inverters in parallel-operation while keeping the advantages of unipolar switching. The proposed current balancing method is verified by both simulation and hardware experiment. Experimental verification is performed on two 1 kW, 400 V input, and 120 V/60 Hz output prototypes, which shows a good agreement to the analytical study. [ABSTRACT FROM AUTHOR]

The integration of switched-capacitor techniques into multilevel inverters (MLIs) with a dc source string contributes to the boosting of voltage gain, renders it particularly attractive in reducing the number of input dc sources in the series string. However, the recent two-stage MLI topologies suffer from high voltage stress across the backend H-bridge. Addressing this concern, an improved topology, namely the one-switched-capacitor integrated MLI (1SCI-MLI) is proposed in this paper. An extended topology of 1SC-MLI is also established by appropriate incorporation of another switched-capacitor circuit. The two proposed topologies are endowed with voltage boosting capability. They also feature low switch count and low number of dc sources. More importantly, they resolve the high voltage stress problem in the existing counterparts. Their corresponding operational analysis and comparisons with recent MLI topologies are discussed. Simulation and experimental results from a laboratory prototype are presented to validate the effectiveness of the proposed topologies. [ABSTRACT FROM AUTHOR]

This paper deals with the analysis of the input dc-link voltage ripple in multilevel inverter based on H-bridge and level doubling network (LDN). The LDN is basically a half-bridge fed by a floating capacitor, with voltage self-balancing capability, recalling the concept of a flying capacitor configuration. The amplitude of the LDN voltage ripple is analytically determined considering both the low-order and the switching harmonic components. In particular, peak-to-peak distributions of voltage ripples over the fundamental period are analytically determined, making possible the design of dc-link capacitor relying only on the dc-voltage ripple requirements. The case study makes reference to negligible switching ripple in the output current. It well represents either grid connection or passive load having almost sinusoidal currents. Numerical simulations carried out by MATLAB/Simulink and a complete set of experimental verifications are given to confirm the theoretical developments. [ABSTRACT FROM AUTHOR]

In this paper, a novel structure of switched capacitor converter (SCC) is proposed. First, the basic unit of the proposed SCC is presented. After that, a generalized structure of the proposed SCC is discussed. The presented SCC uses one dc source, several switches, diodes, and capacitors to produce multistep dc boosted output voltage. The capacitors in the SCC can be charged in trinary asymmetrical pattern. A detailed comparative study between the proposed and other recently developed SCC structures is presented. It is shown that the proposed SCC can produce an output voltage level with lower total standing voltage and lower maximum switch stress voltage as compared to most of the suggested SCC structures. Further, a switched capacitor multilevel inverter (SCMLI) based on cross-switched multilevel inverter has been developed and analyzed for symmetric and asymmetric dc source configurations. For fair comparison with the existing SCMLI structures, the overall cost of the structures is compared based on a cost function (CF). The proposed SCMLI provides lower cost function/output voltage level (CF/NL) in comparison with most of the other SCMLI structures for both symmetric and asymmetric dc source configurations. Extensive experimental studies validate the operation and performance of the proposed SCMLI structure. [ABSTRACT FROM AUTHOR]

This paper presents the topology and modulation technique of a three-phase three-level modified Z-source neutral-point-clamped (MZS-NPC) inverter, which combines a modified Z-source impedance network and a three-phase three-level NPC inverter. The boost factor of the proposed MZS-NPC inverter is twice as high as the three existing representative topologies combing an impedance network with a three-level NPC inverter. A modulation scheme for the proposed topology, based on a maximum boost control method, is designed to achieve the maximum voltage gain with simple implementation and to balance the dc-link neutral-point voltage. A closed-loop control of the ac load voltage in the fuel-cell or photovoltaic applications based on the proposed inverter is realized, in order to supply a desired voltage to the critical load in islanding mode of a microgrid. The boosting ability and operation validity of the proposed topology and modulation technique are demonstrated with simulation and experimental results. [ABSTRACT FROM AUTHOR]

A pulsewidth-modulation bidirectional ac–dc converter (i.e., active rectifier) with dc-fault-blocking and self-pre-charge capabilities is proposed in this paper for low voltage dc (LVdc) applications. The proposed converter, which is named as “H5 + converter,” consists of an H4 bridge, a bidirectional switch, and a transient-voltage-surge (TVS) diode. The bidirectional switch and the TVS diode enable the dc fault blocking and dc bus self-pre-charge, while preserving the low common-mode voltage noise and low leakage current of the converter. Additionally, the proposed H5+ converter has advanced features under a dc-side short-circuit fault, such as fault diagnosis and fault recovery. Operation principles of the proposed converter are presented and analyzed. A down-scaled prototype is built. Experiment results are shown and analyzed, including steady-state waveforms, common-mode performance, start-up dynamics, as well as dc fault blocking, fault diagnosis, and fault recovery. Moreover, the proposed converter is compared with other two dc-fault-blocking converters for LVdc applications, in terms of converter capabilities, required devices, and power switch losses. [ABSTRACT FROM AUTHOR]

This paper proposes a new family of multilevel inverter topology that is able to generate seven voltage levels by utilizing one or two floating capacitors and 10 power switches. This novel boost switched-capacitor seven-level inverter possesses voltage boosting capability with an achievable maximum voltage level 1.5 times the input direct current (dc) voltage. The generation of higher output voltage does not incur high-voltage stress on any power switch in this topology, as the peak inverse voltages of all power switches do not exceed the input source voltage. In addition, capacitor voltage balancing is not essential since the floating capacitors are effectively balanced during the charging and discharging processes. Furthermore, the proposed topology eliminates the need for multiple isolated dc sources, and a single dc source is sufficient in both its single-phase and three-phase topologies. The operating principle and steady-state analysis of the proposed topology are elaborated. Experimental results from a single-phase prototype are then presented to verify the validity of the proposed topology. [ABSTRACT FROM AUTHOR]