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A new space vector modulation, i.e., ZSVM3, for three-phase quasi-Z-source rectifier (qZSR) is proposed. All switches in the three-phase bridge can be turned on and turned off with zero current or zero voltage using the proposed ZSVM3 with no auxiliary circuit. The current through the inductors of the quasi-Z-source network operates in a boundary conduction mode or discontinuous conduction mode to achieve all freewheeling diodes turned off with zero-current switching (ZCS). At the same time, the switch in the quasi-Z-source network can be turned on with ZCS. Besides, the voltage stress of all switches is equal to dc-link voltage. The operation principle of the qZSR is analyzed in detail, and the calculated value of the quasi-Z-source inductor is given. The proposed theory in this paper is verified by a 2-kW prototype. [ABSTRACT FROM PUBLISHER]

In trasformerless grid-connected photovoltaic (PV) systems, common-mode voltage (CMV) fluctuations cause leakage current flow through the stray capacitance of the PV panels. Shoot-through states in a quasi-Z-source inverter (q-ZSI) increase the amplitude of high-order harmonics of CMV. In this paper, by using the modulation technique based on odd pulse width modulation and minor change in the Z network of the three-phase q-ZSI, the leakage current is blocked. No extra semiconductor element is added. By the proposed technique, CMV is kept nearly constant during switching cycles. The experimental results for CMV analysis in a \text1\;\textkW prototype are presented to verify the theoretical analysis. [ABSTRACT FROM PUBLISHER]

Cascaded H-bridge (CHB) multilevel inverters (MLIs) have been widely used for power electronics systems. While high-voltage blocking across power switches is not a constraint for low voltage applications, the research trend has been oriented to the design of more compact module topologies as an alternative for CHB. Despite the generation of more voltage levels with reduced switch count, the existing module topologies in recent literature take no account of the freewheeling current path during dead-time, thus, inducing multistep jumps in voltage levels and giving rise to undesirable voltage spikes. Addressing this concern, this paper proposes two symmetrical compact-module topologies for cascaded MLI, where freewheeling current path during dead-time is provided for smooth transition between voltage levels to prevent voltage spikes. The proposed 7-level and 13-level compact-modules demonstrated low number of conducting switches for all voltage levels. Comprehensive analysis and comparison with the latest module topologies are conducted. To validate the operation of the proposed compact-module topologies, simulation and experimental results are presented. [ABSTRACT FROM PUBLISHER]

Multilevel inverters (MLIs) have replaced conventional two-level inverters for medium-voltage high-power industrial applications. One of the best modulation techniques for MLIs is the space vector modulation (SVM). Although SVM has its own advantages, it has been overlooked for much simpler carrier-based modulation schemes in the industry. Nearest level modulation (NLM) is a simple alternative, which is functionally similar to SVM. In this paper, a new generalized SVM algorithm is presented, in which the SVM is achieved using the concept of NLM. A generalized switch matrix is introduced to derive gate pulses for the inverter, which further simplifies the algorithm. The algorithm is tested and verified for a three-phase, three-level, and five-level neutral-point-clamped inverters in both simulation and hardware. [ABSTRACT FROM PUBLISHER]

In this paper, two switched-capacitor quasi-switched boost inverters (qSBIs) are proposed. By adding one capacitor and one diode to the qSBIs, the proposed inverters achieve high voltage gain with low voltage stress on active switches, capacitors, and diodes. The proposed inverters can extend to n-cell for voltage gain improvement. The operating principle, steady-state analysis, and impedance parameter selections of the proposed inverter are presented. A full comparison between the proposed inverter and other impedance-source inverters is addressed. A 500-W prototype is built to verify the operating theory of the proposed inverter in both the standalone mode and the grid-connected mode. Simulation and experimental results validate the theoretical analysis. [ABSTRACT FROM PUBLISHER]

This paper proposes a multiloop framework for current control of grid-connected voltage source inverters (VSIs) with LCL output filter. The discrete-time model is of third-order with a nonminimum phase zero when controlling the grid side current. This poses some difficulties on the design of most types of controllers. Motivated by this problem, the inner loop is implemented by a discrete-time sliding mode control law to ensure the tracking of the converter side current. This can be achieved regardless the grid impedance and voltage, making the converter to behave like a current source inverter with a capacitive+inductive (CL) filter. Thus, the problem of current control falls from a third-order system to a second-order system. Several types of controllers can be designed to implement the outer loop based on the equivalent CL circuit. In this work, a resonant controller with a virtual resistor was applied. Simulations and experimental results are presented to validate the proposal. [ABSTRACT FROM PUBLISHER]

In this paper, a method is proposed to investigate the dc-link current and voltage ripple calculations in voltage source inverters by considering the reverse recovery of the antiparallel diodes. The impact of the diode reverse recovery transient on the dc-link current and voltage within the switching period is first analyzed. The analysis indicates that the current ripple rms value is affected by the value of inverter switching frequency, diode reverse recovery time, and current. However, the diode reverse recovery shows negligible impact on the dc-link voltage ripple calculation, since the difference between the voltage ripples calculated by the proposed and existing method is less than 1%. To evaluate the estimation accuracy of the dc-link current ripple rms value by the proposed method, the experiments are implemented and the comprehensive analysis is done under different operating conditions, including various power factors, modulation indexes, inverter output currents, and inverter switching frequencies. Experimental results show that the accuracy of dc-link rms current ripple calculation by the proposed method is in the range of $\pm$5% and increased by up to 7% compared with the existing method neglecting the antiparallel diode reverse recovery. [ABSTRACT FROM AUTHOR]

Shunt active power filter (SAPF) is the preeminent solution against nonlinear loads, current harmonics, and power quality problems. APF topologies for harmonic compensation use numerous high-power rating components and are therefore disadvantageous. Hybrid topologies combining low-power rating APF with passive filters are used to reduce the power rating of voltage source inverter (VSI). Hybrid APF topologies for high-power rating systems use a transformer with large numbers of passive components. In this paper, a novel four-switch two-leg VSI topology for a three-phase SAPF is proposed for reducing the system cost and size. The proposed topology comprises a two-arm bridge structure, four switches, coupling inductors, and sets of LC PFs. The third leg of the three-phase VSI is removed by eliminating the set of power switching devices, thereby directly connecting the phase with the negative terminals of the dc-link capacitor. The proposed topology enhances the harmonic compensation capability and provides complete reactive power compensation compared with conventional APF topologies. The new experimental prototype is tested in the laboratory to verify the results in terms of total harmonic distortion, balanced supply current, and harmonic compensation, following the IEEE-519 standard. [ABSTRACT FROM AUTHOR]

In this paper, the direct torque control (DTC) for a three-level five-phase inverter-fed five-phase induction motor is proposed to improve the low-speed performance. The classical DTC scheme (DTC-I) is modified in order to minimize the demagnetization effect during a low-speed operation. According to the modification, the voltage vector space plane is divided into 20 sectors, each of sector 18°. For odd number of sectors, ${{\pm 36^\circ }}$ displaced intermediate voltage vectors, and for even number of sectors, ${{\pm 36^\circ }}$ displaced main voltage vectors are selected instead of classic ${{\pm 72^\circ }}$ displaced voltage vectors. The zero voltage vectors are omitted in the proposed DTC scheme (DTC-II) for the low-speed operation. The DTC-II scheme reduces the demagnetization effect during a low-speed region at the cost of increase in the torque ripple due to avoiding zero voltage vectors. As the speed ramps up, the ${{\pm 72^\circ }}$ displaced voltage vectors are selected through a seven-level torque comparator and are divided into ten sectors. Therefore, in the medium and the higher speed region, the torque ripple is reduced by using the seven-level torque comparator. Simulation and experimental results are presented in order to validate the DTC-II method. [ABSTRACT FROM PUBLISHER]

This paper discusses the use of a cascaded multilevel converter for flexible power conditioning in smart-grid applications. The main feature of the proposed scheme is the use of independent dc links with reduced voltages, which makes such a topology an ideal candidate for medium- and high-power applications with increased reliability. The developed control strategy regulates independent dc-link voltages in each H-bridge cell, and allows the selective and flexible compensation of disturbing currents under a variety of voltage conditions without requiring any reference frame transformation. The selective control strategies are based on the decompositions proposed in the conservative power theory, which result in several current-related terms associated with specific load characteristics. These current components are independent of each other and may be used to define different compensation strategies, which can be selective in minimizing particular effects of disturbing loads. Experimental results are provided to validate the possibilities and performance of the proposed control strategies, considering ideal and deteriorated voltage conditions. [ABSTRACT FROM PUBLISHER]

This paper proposes a new high-gain soft-switching dc–dc topology based on a switched inductor boost converter (SIBC). A conventional SIBC as a high gain boost topology has the issues of high conduction loss in switching diodes and high switching loss in the main switches. Also, it has severe electromagnetic interference (EMI) issue due to high-frequency ringing formed by parasitic inductance and diode junction capacitors. The new topology is derived with the objective of achieving zero voltage switching (ZVS) turn on of the main switch. Instead of adding extra active clamp zero voltage transition (ZVT) path at the switching node, the proposed topology augments the auxiliary ZVT path to the switching diode path. This is achieved by replacing the switching diodes with synchronous switches. The new topology can achieve soft switching for all the switches and alleviate the EMI issue. All the diodes achieve zero current switching (ZCS) turn off without reverse recovery. Auxiliary switches have ZCS turn on and ZVS turn off, and the main switches have ZVS turn on. The soft-switching SIBC also reduces the conduction loss in the switching diodes. A numerical simulation in PLECS and a prototype hardware are built corresponding to a micro-inverter application with 100 kHz switching frequency. Peak power conversion efficiency of 94.76% is achieved in the hardware prototype with Si devices. [ABSTRACT FROM PUBLISHER]

This paper presents a reverse mapping based space vector pulse-width modulation strategy for five- and seven-level diode-clamped multilevel inverters. In this method, the space vector is expressed as a sum of a contender vector and an error vector. Here, the actual sector, which contains the tip of the reference space vector, needs not to be found. The vector nearest to the reference space vector is the contender vector. By calculating the vector difference of the contender vector from the reference vector, the error vector is determined. Using translation method, the error vector is translated to the origin of space vector diagram. There will be (n–1) steps in space vector diagram for an n-level inverter. As the error vector amplitude will be less than one step of the space vector diagram, the two-level space vector method can be applied. To obtain a vector that is very close to the reference vector, the determined switching states can be added to the contender vector. This technique can be extended to any n-level multilevel inverter. The performance of five-level and seven-level diode-clamped multilevel inverters is presented using MATLAB/Simulink. The performance of inverters is evaluated by using induction motor load. The experimental results using field programmable gate array are presented for seven-level diode-clamped multilevel inverter. [ABSTRACT FROM PUBLISHER]

Space vector modulation (SVM) is a widely used method for multilevel inverters. Most of the SVM methods are nearest three vector (N3V) based schemes. Therefore, several researchers have proposed advanced implementation algorithms with reduced complexity for N3V methods. However, topologies like neutral point (NP) clamped inverter (NPCI) require some distinctive methods (called as non-N3V methods) to balance NP voltage for high modulation index and low power factor operations. Currently, the existing non-N3V methods exercise highly complex algorithms for duty ratio calculation and subtriangle identification. This paper presents a new approach, suitable for both N3V and non-N3V methods, with reduced implementation complexity. The proposed algorithm is based on an equivalent two-level space vector diagram and does not require any trigonometry, coordinate transformation, or volt-second balance solution. Unlike other carrier-based methods, it can change the switching sequence as well as the duration of redundant vectors. Moreover, the proposed approach does not require extra steps for implementing hybrid modulation and it can also be extended to multilevel topologies. One N3V, two non-N3V, and hybrid methods are developed using the proposed modulation algorithm, and are compared in detail. Simulation and experimentation on a three-level NPCI verify the validity of the proposed algorithm. [ABSTRACT FROM PUBLISHER]

This paper proposes an interleaved hybrid converter (IHC) with simultaneous dc and ac outputs for dc microgrid applications. The IHC is realized by interleaving two conventional boost converters and replacing the active switch of lower boost converter by an H-bridge voltage source inverter. This arrangement enables the proposed IHC to operate at the condition where the sum of duty ratio (\boldsymbolD ) and modulation index (\boldsymbolM ) can be more than or equal to one, i.e., \boldsymbolD + \boldsymbolM \geq 1, unlike the conventional hybrid converters. The proposed IHC is capable of giving dc with high voltage gain and improved ac with reduced harmonic distortion. Due to interleaving nature of the IHC, input current is shared between the power converters and thus enables the use of low current rated switching devices and lower values of inductors. This results in reduced power losses and increased efficiency as compared to the conventional hybrid converters. The IHC also has inherent shoot-through protection capability, better electromagnetic interference immunity, and reliability. A modified unipolar sinusoidal pulse width modulation technique is used to control the power flow of the IHC. Detailed mathematical modeling of the proposed IHC is carried out and its steady-state behavior is validated through experimental results on a 500 W laboratory prototype. [ABSTRACT FROM PUBLISHER]

In this paper, finite-set model-predictive control (FS-MPC) methodologies for a grid-connected three-level neutral-point-clamped converter are investigated. The proposed control strategies produce fixed switching frequency, maintaining all the advantages of predictive control such as fast dynamic response, inclusion of nonlinearities and restrictions, and multivariable control using a single control loop. The first of the proposed FS-MPC strategies is based on a multiobjective cost function, designed to regulate both the inverter currents and the balancing of the dc-link capacitor voltages. The second FS-MPC strategy is derived from the first one, and it is based on a cost function that regulates only the grid current, with the balancing of the capacitor voltages being realized by controlling the duty cycles of the redundant vectors. The proposed control systems are experimentally validated using a 5-kW prototype. The experimental results show a good performance for both strategies, in steady-state and transient response, with a total harmonic distortion lower than \text2\% for the currents supplied to the grid. [ABSTRACT FROM PUBLISHER]

The hybrid modulation strategy using both low-frequency square-wave modulation and high-frequency pulse-width modulation can extend the stable operating region of a cascaded H-bridge converter. However, it does not control accurately dc voltages of converter but balances them by charging or discharging dc capacitors based on the state of system, which could aggravate fluctuation of dc voltages. If cascaded H-bridge converter is used in photovoltaic field, the aggravated fluctuation on dc capacitor voltages will result in further losses in energy harvesting of solar cells. To address this issue, a modified hybrid modulation strategy is presented in this paper. When dc-bus measured voltages are close to their reference voltages, these H-bridges operate in a zero mode. Adding appropriate zero state can prevent grid current charging or discharging the dc capacitors whose voltages have already reached their control goals. Therefore, the proposed technique is capable of suppressing dc voltage fluctuation, and, thus, improving the output power of solar cells. Simulation and experimental results validate the effectiveness and feasibility of the proposed method. [ABSTRACT FROM PUBLISHER]

Microinverters for grid-connected photovoltaic (PV) power conversion systems often require voltage boost due to the low dc voltage of the PV panels. A high-frequency (HF) transformer-isolated differential-mode Ćuk inverter (DMCI) is an attractive topology due to its inherent voltage boost capability and high power density. One of the significant operational issue of the DMCI addressed in this paper is the presence of lower order harmonic distortion in the injected grid current. It is shown that lower order odd and even harmonic voltages are generated with this topology. This problem is accentuated due to the low damping offered by the grid to harmonic voltages. A systematic low-complexity control design is proposed to address this issue. It is shown experimentally that the DMCI operates stably with effective attenuation of the lower order harmonics using the proposed design. Practical operational issues of the DMCI with fast switching GaN field-effect transistor (FET) devices are analyzed and solutions are proposed. It is shown that there can be significant HF noise generation in the DMCI with a frequency range higher than the switching frequency. Practical solutions for resolving HF issues using a combination of circuit layout design and additional passive components are proposed and validated. All of the experimental results are demonstrated on a 500-W GaN-FET-based microinverter prototype. [ABSTRACT FROM PUBLISHER]

This paper presents a variable structure control in natural frame for a three-phase gird-connected voltage-source inverter with LCL filter. The proposed control method is based on modifying the converter model in natural reference frame, preserving the low-frequency state-space variables dynamics. Using this model in a Kalman filter (KF), the system state-space variables are estimated allowing us to design three independent current sliding-mode controllers. The main closed-loop features of the proposed method are: first, robustness against grid inductance variations because the proposed model is independent of the grid inductance; second, the power losses are reduced since physical damping resistors are avoided; third, the control bandwidth can be increased due to the combination of a variable hysteresis comparator with the KF; and fourth, the grid-side current is directly controlled providing high robustness against harmonics in the grid. To complete the control scheme, a theoretical stability analysis is developed. Finally, selected experimental results validate the proposed control strategy and permit illustrating all its appealing features. [ABSTRACT FROM PUBLISHER]

Several single-stage topologies have been introduced since kicking off the three-phase Z-source inverter (ZSI), and among these topologies, the quasi-ZSI (qZSI) is the most common one due to its simple structure and continuous input current. Furthermore, different modulation strategies, utilizing multiple reference signals, have been developed as well. However, prior art modulation methods have some demerits, such as the complexity of generating the gate signals, the increased number of switch commutations with continuous commutation at high current level during the entire fundamental cycle, and the multiple commutations at a time. Hence, this paper proposes two modified space vector modulation strategies, aimed at the reduction of the qZSI number of switch commutations at high current level for shorter periods during the fundamental cycle, i.e., reducing the switching loss, simplifying the generation of the gate signals by utilizing only three reference signals, and achieving a single-switch commutation at a time. These modulation strategies are analyzed and compared to the conventional ones, where a reduced-scale 1-kVA three-phase qZSI is designed and simulated using these different modulation strategies. Finally, the 1-kVA three-phase qZSI is implemented experimentally to validate the performance of the proposed modulation strategies and verify the reported analysis. [ABSTRACT FROM PUBLISHER]

A single-switch quadratic buck–boost converter with continuous input port current and continuous output port current is proposed in this paper. Compared with the traditional buck-boost converter, the proposed converter can obtain a wider range of the voltage conversion ratio with the same duty cycle. Moreover, the proposed converter can operate with continuous input port current and continuous output port current compared to the existing counterparts with inherently discontinuous input port current and discontinuous output port current. The operating principle and steady-state performance of the proposed converter under continuous inductor current mode is analyzed in detail. Then, the comparison between the proposed converter and the existing quadratic buck–boost converters has been conducted to demonstrate the unique features of the proposed one. Finally, experimental results from a prototype built in the lab are recorded to verify the effectiveness and validity of the proposed quadratic buck–boost converter. [ABSTRACT FROM PUBLISHER]

Open-circuit (OC) fault diagnosis of voltage source inverters on trains still has two problems to be improved. First, it is usually forbidden to change the system structures of trains or to add any extra sensor. Therefore, diagnostic methods which need pulse width modulation control signals or extra output voltage sensors are no longer suitable for trains. Second, loads on the train vary in a wide range and have significant influence on output currents. In order to solve these problems and increase the maintenance efficiency, an online diagnostic method for single switch OC (SSOC) faults and double switches OC (DSOC) faults is proposed. Supposing that three phases are balanced, it is proved that the trajectory of two output currents is an ellipse in the Cartesian coordination, and each OC fault has a unique trajectory. SSOC faults and DSOC faults can be isolated by detecting abnormal slopes and directions of several consecutive points on the trajectory. The fastest diagnostic process takes less than half a period. Load variation has impact on the size and shape of the trajectory but does not affect the diagnostic method. Experimental tests are carried out on dSPACE platform. Results show the accuracy of the mathematical model and the effectiveness of the online diagnostic method proposed in this paper. [ABSTRACT FROM PUBLISHER]

This paper introduces series work of common-mode (CM) voltage reduction for the paralleled inverters. The paralleled inverters’ phase-legs are connected through coupling inductors and the combined three-phase currents are provided to the load. Interleaving is an approach to reduce the CM voltage for the paralleled inverters but it cannot eliminate CM voltage. A novel pulse-width-modulation (PWM) method for paralleled inverters which can theoretically achieve zero CM voltage is developed. Considering the basic voltage vectors in each inverter, novel paralleled voltage vectors which have zero CM voltage are proposed to combine the reference voltage vector. The action time's distribution and voltage vectors’ sending sequence for each inverter are also introduced. The proposed PWM method can make sure the voltage of the two inverters are balanced in each switching cycle and limits the circulating current through small coupling inductors. Similar to interleaving space vector PWM, the proposed zero CM PWM also has the ability to reduce the output current ripple and electromagnetic interference (EMI). Simulation and experimental results are provided to show the advantage of paralleled inverters in CM voltage reduction and validate the proposed method has good performance to reduce CM current and CM EMI noise. [ABSTRACT FROM PUBLISHER]

This paper presents an optimized topology of 3-$\phi$ , multilevel inverter (MLI) configuration for five or higher level operation with reduced switch count. The proposed solution consists of two basic units (BUs) of multilevel converter and a T-structured 3-level inverter (3-LI). Both BUs are equally shared by the three phases maintaining symmetry among the phases. Moreover, for a higher level operation of the proposed MLI, the modifications required are at two BUs only and not at three legs of the inverter. It further helps in reducing the requirement of extra components for higher level operation compared to the conventional solutions. Furthermore, the topology also has the benefits of reduced switching and conduction loss. An algorithm is also devised to generate the switching pulses for the BUs and the 3-LI, using a carrier-based space vector modulation technique. Presented topology is compared with other existing topologies to prove its advantage. All the details regarding the operating modes and pulse width modulation techniques employed for the proposed system are given and supported by the simulation and experimental results. [ABSTRACT FROM AUTHOR]

A modified scheme for reactive power compensation using static VAr compensators (SVCs) has been proposed in this paper for unbalanced four-wire system. The conventional SVC-based scheme requires both delta ( $\Delta $ $)$ - and star (Y)-connected SVCs for the same purpose. The proposed scheme uses a single-equivalent delta-connected thyristor controlled reactor (TCR) along with a combination of Y- and $\Delta $- connected thyristor switched capacitors for this purpose. The single-equivalent $\Delta $ -TCR in the present scheme is the result of a virtual Y-TCR and the conventional $\Delta $-TCR. This can reduces effective number of switching devices, cost, complexity, and space requirement compared to the conventional SVC-based schemes. Moreover, the proposed scheme can have various advantageous features compared to newly used DSTATCOM. The proposed scheme can also prevent injection of triplen harmonics in to the line, which is injected by Y-TCR in the conventional scheme. An optimized switching function is adopted in the proposed scheme for reduction of additional injected harmonics by TCR. The optimized switching angles are computed offline using gravitational search algorithm and stored in the processor memory for online application. The viability of the proposed scheme is simulated using MATLAB/Simulink and verified by suitable experimental results on a practical system. [ABSTRACT FROM AUTHOR]

Adding the auxiliary switches to the conventional H-bridge inverter is an effective way to eliminate the leakage current for transformerless PV systems, such as H5, H6, etc. Inspired by the newly developed embedded-switch H6 topology, a novel embedded-switch inverter (ESI) is proposed in this paper for three-phase transformerless PV systems. First, the operation principle and characteristics of the proposed ESI are analyzed. Second, the common-mode model of the three-phase ESI is established, based on which the main factors that affect the leakage current are discussed. The finding reveals that the switching states with conventional modulation strategy result in high-frequency common-mode voltage, which is the source of leakage current. In order to solve the problem, a new modulation strategy is presented for ESI to eliminate the high-frequency leakage current. Finally, the time-domain simulation and the experimental tests are carried out. The results verify the effectiveness of the proposed solution. [ABSTRACT FROM AUTHOR]

This paper aims to investigate a disturbance-rejection-based model predictive control (MPC) with two flexible modes (i.e., unconstrained mode and constrained mode) for three-phase inverters with an $LC$ filter. A disturbance observer (DOB) is designed to both simplify the prediction model and achieve the robustness against uncertain parameters. First, the unconstrained mode is designed with a simple horizon-one MPC control law to precisely regulate the output voltage in the steady state. Next, the constrained mode is designed with long-horizon MPC to quickly drive the system to the unconstrained mode by further optimizing the modulation stage. Also, the proposed MPC ensures the robustness and optimality in all operating modes. Especially, the overall closed-loop stability with DOB dynamics is proven by using Lyapunov function. Unlike other MPC methods, the long-horizon MPC in the constrained mode is specialized by finite switching sequences of the sector-based space vector modulation. Comparative studies with the conventional linear quadratic regulator are conducted on a prototype test bed with a TI TMS320F28335 DSP. Then, the proposed MPC method verifies fast dynamic response and advanced voltage regulation (i.e., small steady-state errors and low total harmonic distortion) under various load conditions and uncertain parameters. [ABSTRACT FROM AUTHOR]

In this paper, dual-buck structured single-stage buck–boost inverters that use power MOSFETs to achieve high efficiency are presented. The proposed inverters require fewer switches, and half of the switches have reduced current stresses. They have no shoot-through problem; therefore, high system reliability can be obtained. The dead-time in PWM signals can be minimized or eliminated, which improving the quality of the output ac voltages and increasing the efficiency. In the proposed inverters, MOSFETs can be used without reverse-recovery issues of their body diodes to boost the efficiency and increase the switching frequency. To further improve the efficiency and stability of the proposed single-phase inverter, PWM strategies combining high- and low-frequency modulation are presented. A hardware prototype of the single-phase inverter was built and tested using resistive, inductive, and nonlinear loads. Experimental results for a 300-W prototype inverter show a 97.4% peak efficiency with a 25 kHz switching frequency. [ABSTRACT FROM AUTHOR]

Traditional model predictive control cost functions, when utilizing long prediction horizons ( $N\geq 10$) in power inverter applications, have demonstrated harmonic performances approaching that of schemes based on offline-generated optimal pulse patterns. However, long prediction horizons often prohibitively increase computational load. A different approach to maximizing harmonic performance is taken in this paper. It is shown that shaping the output voltage spectra using a simple feedback mechanism can significantly reduce the length of the required prediction horizon, facilitating a feasible computational load. When a short-horizon cost function is augmented by the feedback mechanism an excellent tradeoff between harmonic performance and switching loss is achieved, even with a prediction horizon of one. It is also shown that the feedback mechanism can be used to improve input reference tracking. Experimental verification of the proposed modulator is performed on a two-level three-phase inverter. [ABSTRACT FROM AUTHOR]

Compared with multilevel space vector modulation, level-shifted multicarrier sinusoidal pulsewidth modulation (SPWM) for nested neutral point-clamped (NNPC) inverters requires much less calculations and implementation efforts, but the existing conventional SPWM cannot suppress the severe flying-capacitor (FC) voltage ripples under low output-frequency conditions. In order to solve this problem, a multicarrier-based PWM strategy with complete voltage balance control (VBC) capacity is proposed in this paper. For NNPC inverters operating under low output-frequency conditions, two preprocessing steps, the zero-sequence injection and the modulation-signal rearrangement, are proposed before the comparisons between level-shifted carriers and modulating signals. These preprocessing steps make the average currents flowing through FCs zero, which is beneficial to greatly reduce the FC voltage ripples under low output-frequency conditions. Together with additional VBC, the proposed modulation can assure the FC voltages balanced under the entire output-frequency conditions. Principles and implementation processes of proposed modulation techniques and VBC methodsare elaborated in detail and compared with conventional modulation methods. Both simulation results from a 5-MVA system and experimental results based on a 5-kVA platform are presented to verify the effectiveness. [ABSTRACT FROM AUTHOR]

A dual-buck inverter (DBI) possesses no shoot-through worries and can boost efficiency by using power mosfet s. The main drawback of a DBI is the use of more inductors than in a traditional full-bridge inverter. This greater number of inductors decreases the power density and increases system cost. In this paper, a modified cascaded full-bridge DBI is proposed. It retains all the advantages of the conventional cascaded full-bridge DBI, possesses no shoot-through issues, and can be operated with no pulse-width-modulation dead-times. It can be implemented with power mosfet without reverse recovery issues of a body diode to boost efficiency. The cascaded modules in the proposed inverter share current limiting inductors. Therefore, the number of inductors and inductor footprints, the complexity of the circuit layout, required inductance, and magnetic volume can all be decreased. To show the advantages of the proposed inverter, detailed theoretical analysis and experimental results are provided. [ABSTRACT FROM PUBLISHER]

In this paper, an ultralow inductance power cell is designed for a three-level active neutral point clamped (3L-ANPC) based on 650-V gallium nitride (GaN) high electron mobility transistor (HEMT) devices. The 3L-ANPC topology with GaN HEMT devices and the selected modulation scheme suitable for wide-bandgap devices are presented. The commutation loops, which mainly contribute to voltage overshoots and increase of switching losses, are discussed. The ultralow inductance power cell design based on a four-layer printed circuit board with the aim to maximize the switching performance of GaN HEMTs is explained. The design of gate drivers for the GaN HEMT devices is presented. Parasitic inductance and resistance of the proposed design are extracted with finite-element analysis and is discussed. Common-mode behaviors based on the simulation program with integrated circuit emphasis (SPICE) model of the converter are analyzed. Experimental results on the designed 3L-ANPC with output power of up to 1 kW are presented, which verifies the performance of the proposed design in terms of ultralow inductance. [ABSTRACT FROM AUTHOR]

The effect of inverter dead time on the inverter output voltage is well studied in the literature. This paper studies the effect of the dead time on the inverter input current. An expression for the switching-cycle-averaged inverter input current including the dead time effect is derived, which shows the dead time effect to primarily result in a reduction in the average value of the inverter dc input current. The effect of dead time on the input current is incorporated into the dc-link dynamic model of a diode-bridge-rectifier (DBR) fed voltage source inverter (VSI). A switching-cycle-average model of a DBR-VSI-fed induction motor is proposed, which considers the effect of dead time on both the ac output voltage and dc input current of the VSI. The proposed average model is used to study the light-load instability phenomenon in a 100-kW open-loop motor drive. The proposed model is shown to predict the region of oscillatory behavior (i.e., region exhibiting light-load instability) with better accuracy than existing average models. The proposed model also accurately predicts the dc-link voltage swing at such oscillatory operating points. While being comparable in accuracy in predicting the system dynamics, the proposed model is much more computationally efficient than the state-of-the-art switching model. The validity of the proposed average model is also confirmed by experimental measurements on a 100-kW induction motor drive. [ABSTRACT FROM AUTHOR]

This paper proposes an improved offset selection method for discontinuous-pulse-width-modulation (DPWM)-based back-to-back converters to reduce dc-link current ripple. DPWM is introduced to power converters to diminish the stress on power transistors and prolong their lifespan. However, when using the DPWM method, the dc-link current ripple is increased in nonswitching regions of the power transistors. Moreover, in DPWM-based back-to-back converters, the dc-link current ripple reaches its maximum when the two transistors of both inverters are clamped in opposite directions. Therefore, the dc-link capacitors endure more stress, resulting in decreased life duration. To overcome this issue, the switching method should consider the clamping periods, when the current ripple increases. This can be achieved by modifying the DPWM offset, so that the clamping states of both converters are matched. The effectiveness of the proposed method is confirmed by both simulation and experimental results. [ABSTRACT FROM PUBLISHER]

This paper proposes a high-efficiency two-stage three-level grid-connected photovoltaic (PV) inverter. The proposed two-stage inverter comprises a three-level step-up converter and a three-level inverter. The three-level step-up converter not only improves the power-conversion efficiency by lowering the voltage stress but also guarantees the balancing of the dc-link capacitor voltages using a simple control algorithm; it also enables the proposed inverter to satisfy the VDE 0126-1-1 standard of leakage current. The three-level inverter minimizes the overall power losses with zero reverse-recovery loss. Furthermore, it reduces harmonic distortion, the voltage ratings of the semiconductor device, and the electromagnetic interference by using a three-level circuit configuration; it also enables the use of small and low-cost filters. To control the grid current effectively, we have used a feed-forward nominal voltage compensator with a mode selector; this compensator improves the control environment by presetting the operating point. The proposed high-efficiency two-stage three-level grid-connected PV inverter overcomes the low efficiency problem of conventional two-stage inverters, and it provides high-power quality with maximum efficiency of 97.4%. Using a 3-kW prototype of the inverter, we have evaluated the performance of the model and proved its feasibility. [ABSTRACT FROM PUBLISHER]

This paper proposes a family of novel flying capacitor transformerless inverters for single-phase photovoltaic (PV) systems. Each of the new topologies proposed is based on a flying capacitor principle and requires only four power switches and/or diodes, one capacitor, and a small filter at the output stage. A simple unipolar sinusoidal pulse width modulation technique is used to modulate the inverter to minimize the switching loss, output current ripple, and the filter requirements. In general, the main advantages of the new inverter topologies are: 1) the negative polarity of the PV is directly connected to the grid, and therefore, no leakage current; 2) reactive power compensation capability; and 3) the output ac voltage peak is equal to the input dc voltage (unlike neutral-point-clamped and derivative topologies, which requires twice the magnitude of the peak ac voltage). A complete description of the operating principle with modulation techniques, design guidelines, and comprehensive comparisons is presented to reveal the properties and limitations of each topology in detail. Finally, experimental results of 1-kVA prototypes are presented to prove the concept and theoretical analysis of the proposed inverter family for practical applications. [ABSTRACT FROM PUBLISHER]

This paper proposes a repetitive controller with phase-lead compensation for an unfolding-type Cuk continuous conduction mode (CCM) inverter operating in the CCM. The Cuk CCM inverter features medium power capacity, step up/down ability, and low input/output current ripples, so it is well suited to distributed power generation systems. To achieve accurate tracking of the reference output current, we make the use of the repetitive controller coupled with a conventional proportional-integral controller and a nominal duty ratio. In developing the proposed controller, we use the average model of the Cuk CCM inverter in the grid-connected case. The two right-half plane (RHP) zeros in the transfer function of the Cuk CCM inverter cause phase lag of the closed-loop system; to compensate for the phase lag, we implement a phase-lead compensation algorithm in the repetitive control scheme. We also provide detailed and practical design guidelines of the control parameters to develop a stable Cuk CCM inverter. Experimental tests using a 500-W Cuk CCM inverter demonstrate the desirable performance of the proposed control approach. [ABSTRACT FROM PUBLISHER]

This paper discusses the operation of a single-stage, isolated, high-frequency ac-link-based single-phase dc–ac converter, suitable for photovoltaic microinverter applications, controlled using phase modulation of the secondary-side cycloconverter devices. A detailed analysis is presented explaining the impact of prominent circuit nonidealities such as device capacitance and transformer leakage inductance on circuit behavior. The proposed extended-dead-time based modulation scheme helps in achieving zero-voltage-switching of the primary devices over the entire line cycle of the ac output and also offers the benefit of reduced transformer rms current due to absence of circulating current in the zero state. A flyback-based regenerative clamp circuit is used for mitigating voltage spikes on the secondary devices arising due to leakage inductance induced oscillations. A generic commutation strategy is also discussed, which makes operation with nonunity power factor loads also possible. Experimental results on a 260-W laboratory prototype under different load conditions are presented to illustrate the discussed principles and highlight the performance improvements. [ABSTRACT FROM PUBLISHER]

Four-level nested neutral-point clamped (NNPC) inverters experience severe voltage balancing problems under low output-frequency conditions when the conventional four-level space vector modulation (4L-SVM) technique is applied, which limits their wider application. In order to get a complete control of the flying-capacitor voltages, and to alleviate the calculation burden of conventional 4L-SVM, a simplified but effective 4L-SVM technique along with the voltage balance control (VBC) function is proposed in this paper. For low modulation indexes, zero and small vectors are selectively utilized and distributed to force the average charging and discharging time of flying capacitors to be equal to each other during every switching period, so that voltage ripples are greatly reduced to be within an acceptable level under low output-frequency conditions. For high modulation indexes, the simplification of conventional 4L-SVM for NNPC inverters into two-level SVM is proposed to reduce the computation complexity. Principles of the proposed 4L-SVM and VBC are elaborated in detail. The steady-state, transient-state, and VBC performances are investigated and compared with the case where the conventional 4L-SVM is applied. Simulation results of a 5 MVA inverter system and experimental results of a scaled-down 5 kVA inverter system are presented to validate the proposed method. [ABSTRACT FROM PUBLISHER]

An open-end winding machine configuration and a suitable control strategy for medium-voltage ac motor drives applications are proposed in this paper in order to reduce the distortion of phase voltages in multilevel inverters (MLIs). Differently than standard open-end winding configurations, where two inverters provide active power to both sides of the stator winding, a main MLI supplies in this case the machine on one side, while an auxiliary two-level inverter acts as active power filter on the other side. A high efficiency step modulation manages the MLI, while the auxiliary unit is pulse width modulation (PWM) operated. As the phase current harmonic content is improved, the torque ripple is reduced and the drive efficiency is increased. By exploiting the proposed approach, the apparent switching frequency of the system is that typical of a PWM inverter, although the main unit is operated according to a voltage step modulation strategy. Simulation and experimental results confirm the consistency of the proposed methodology. [ABSTRACT FROM PUBLISHER]

This paper presents a model-based open-circuit fault diagnosis approach for single-phase three-level neutral-point-clamped (3LNPC) converters in electric railway application. The diagnosis algorithm, which only requires the signals existing in the control system, not only detects open-circuit faults but also identifies the faulty device among the transistors and clamping diodes. The mixed logical dynamic (MLD) model of the converter is built to estimate the grid current. The residual generated from the measured current subtracting the estimated one is analyzed under different open-circuit faults. According to the characteristics of the residual changing rate, the proposed approach allows fault localization. The proposed method is effective both in traction and regenerative braking operation and has fast diagnosis speed. Hardware-in-the-loop (HIL) experiments are carried out to verify the effectiveness of the proposed fault diagnosis algorithm. [ABSTRACT FROM PUBLISHER]

In this paper, a fault-tolerant multiphase multilevel inverter (MPMLI) configuration is proposed based on the dual inverter concept. This configuration helps to improve the performance of pole–phase modulated multiphase induction motor (PPMMIM) drive in both normal and switch failure conditions. Comparing to the existing multilevel inverter topologies for multiphase induction motor (MIM) drives, the proposed MPMLI configuration requires less number of dc sources and power electronic devices. The proposed MPMLI configuration is able to sustain under various faulty conditions, which can improve the reliability of the system. In addition, dc-link utilization (DLU) in low-pole mode is improved by using space vector pulsewidth modulation (SVPWM). In high-pole mode, carrier-phase-shifted 3-Φ SVPWM is used for reducing the torque ripple. This MPMLI configuration produces a multilevel voltage profile across the effective phase in 3-phase 12-pole mode. By maintaining the V/f ratio constant, the proposed MPMLI-fed MIM drive facilitates a wide range of load torque with half of the rated speed in faulty condition. This advantage makes it suitable for traction and electric vehicle applications where reliability and wide range of torque–speed are the major concerns. The performance of proposed MPMLI-fed 5 hp, 9-φ PPMMIM drive is simulated by finite-element method (FEM) in ANSYS Maxwell 2-D and experimentally verified by laboratory prototype under normal and faulty conditions. [ABSTRACT FROM PUBLISHER]

In this paper, a new carrier-based pulse width modulation (PWM) strategy providing common-mode voltage (CMV) elimination and reduced current ripple in a three-level neutral-point-clamped inverter is introduced. The employed switching sequences are made up of the three zero CMV (ZCMV) vectors, and one among the three vec-tors is applied at two ends of a half-carrier cycle. The output current ripple characteristics pertaining to those switching sequences are investigated. In a carrier cycle, the root-mean-square current ripple minimization is analyzed and an optimal sequence is derived accordingly. The presented PWM scheme results in a considerably reduced current harmonic distortion in a wide modulation region as compared to the two existing ZCMV schemes on the same average switching frequency. Also, an implementation of sawtooth-carrier-based PWM patterns is proposed for further improvement of the harmonic performance. The algorithm requires small computational burden and is straightforward for an online implementation. Simulation and experimental results are both provided to validate the good performance of the proposed PWM method. [ABSTRACT FROM PUBLISHER]

This paper introduces a new concept of common mode voltage cancellation for pulse width modulated motor drives, aiming at solving issues such as ground leakage current, common mode electromagnetic interference, and bearing current. The balanced inverter topology and dual-winding stator configuration are proposed as a practical realization. Implementation considerations on the influence of circuit asymmetry are also investigated. Finally, a gallium nitride HEMT based induction motor drive prototype is built and tested to evaluate the performance of the cancellation concept in a practical situation. [ABSTRACT FROM AUTHOR]

The injected grid current of the voltage-controlled grid-connected inverter has serious distortion due to the low frequency harmonic components in the output voltage, which is resulted by the dead time of the drive signals of the power switches, and the distortion cannot be eliminated even when an output voltage closed loop is incorporated. This paper introduces a virtual series impedance to increase the output impedance of the grid-connected inverter only at the dominated lower harmonic frequencies; thus, the injected grid current quality can be improved and the dynamic performance of the grid-connected inverter is not deteriorated. Experimental results from a 6-kW single-phase grid-connected inverter confirm the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

This paper introduces a new module for asymmetrical multilevel inverters with a low number of components. The module is a square combination of two back-to-back T-type inverters and some other switches. A square T-type module produces 17 levels by 12 switches and 4 unequal dc sources (two 3VDC and two 1V DC). Also, it can be extended as a cascade connection in two strategies to achieve more levels. The module and its cascade connection are suitable for the applications in several dc sources systems such as photovoltaic farms, which lead to a modular topology with more voltage levels at higher voltages. Inherent creation of the negative voltage levels without any additional circuit (such as H-bridge circuit) is one of the main features of the proposed module. The low total harmonic distortion of the output voltage/current and low number of semiconductors are among the other advantages of the proposed module. A nearest level control method as a switching technique is used to produce high quality output voltage with lower harmonic contents. Simulations have been performed in MATLAB/Simulink and a prototype is implemented in the Power Electronics Laboratory; both the simulation and experimental results show a good performance. [ABSTRACT FROM AUTHOR]

In this paper, an improved transformerless single-phase single-stage grid-tied flying inductor inverter is presented. The negative terminal of the photovoltaic (PV) array is grounded in the improved topology, which increases reliability and suppresses the leakage current. The proposed topology has buck–boost capability without increasing the number of required components and has a high efficiency. An improved control algorithm for proper operation of the proposed topology which decreases switching losses has been investigated. Moreover, a perturbation and observation maximum power point tracking (MPPT) algorithm has been adapted to the proposed inverter, which does not utilize proportional–integral (PI) controllers, for the purpose of the MPPT. Furthermore, a design procedure of the passive elements of the converter based on the corresponding operating has been demonstrated. Simulation in MATLAB Simulink plus an experimental prototype is developed to reconfirm the designed results. Finally, a comparison study has been investigated for better clarification of the advantages and disadvantages of the proposed inverter. [ABSTRACT FROM PUBLISHER]

For three-phase dual-output dc–ac conversion systems, the nine-switch inverter is one of the most versatile available topologies. Despite some disadvantages, recent studies show that the nine-switch inverter achieves efficiency values equivalent to or higher than its 12-switch counterpart, when operating in certain ranges of the modulation index and displacement angles. The use of proper pulse width modulation techniques is able to increase the efficiency even more, as well as to equalize the loss distribution among the switches, favoring an effective and low-cost thermal design. The available pulse width modulation techniques are complex and do not explore the full capacity of the nine-switch inverter to reduce its losses. For this reason, this paper proposes an unrestricted generalized scalar pulse width modulation for nine-switch inverters. Based on this new generalization, a current peak tracking technique is also proposed, achieving small average number of switchings and the highest overall efficiency when compared with other techniques, likewise a more balanced loss distribution among the switches. Experimental results are carried out to demonstrate the validity of the new generalization and the effectiveness of the proposed technique in reducing the switching losses. [ABSTRACT FROM PUBLISHER]

To achieve precise voltage value for modern model-based motor control strategies, an accurate voltage distortion compensation method for voltage source inverters is proposed in this paper. The voltage distortion principles of a mosfet-based inverter and an IGBT-based inverter are analyzed and compared. A graphical solution of compensating voltage error is proposed, all the voltage distortion factors are considered. A current observer is designed to overcome time delay, achieve precise current in each switching period for compensation. The proposed method is of high precision, intuitive, and easy to implement. The effectiveness of the proposed method is verified by experiments. [ABSTRACT FROM PUBLISHER]

This paper presents a new power converter topology to suppress the torque ripple due to the phase current commutation of a brushless dc motor (BLDCM) drive system. A combination of a three-level diode clamped multilevel inverter (3-level DCMLI), a modified single-ended primary-inductor converter (SEPIC), and a dc-bus voltage selector circuit is employed in the proposed torque ripple suppression circuit. For efficient suppression of torque pulsation, the dc-bus voltage selector circuit is used to apply the regulated dc-bus voltage from the modified SEPIC during the commutation interval. In order to further mitigate the torque ripple pulsation, the 3-level DCMLI is used in the proposed circuit. Finally, simulation and experimental results show that the proposed topology is an attractive option to reduce the commutation torque ripple significantly at low- and high-speed applications. [ABSTRACT FROM PUBLISHER]

In this paper, a dc to ac converter with the ability of voltage increasing is presented. This inverter is designed in a way that just one dc source is used. Also, by using power storage technique and with combining charged capacitors and dc source in series form, output voltage levels can be increased. This inverter is in a modular structure and has the ability of capacitor's voltage self-balancing. H-bridge inverter was not used at the end of the proposed converter and all elements tolerate a voltage stress equal to the amount of input dc source. This leads to remarkable decrease of total standing voltage and peak inverse voltage. Other advantage of the proposed inverter is its potentiality of performance in high-frequency applications. The modular form of the proposed inverter provides the potentiality of extension to higher voltage levels and eases the maintenance. Moreover, considering to the fact that the stress of all components of the suggested inverter is equal to the input source, the performance in high voltage is added to the characteristics of the proposed inverter. The nine-level structure of the proposed inverter is simulated and laboratory test is carried out for the verification of its performance. [ABSTRACT FROM PUBLISHER]