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This paper describes a flow control of the dye in the paper mill with the quasi-Z-source indirect matrix converter (QZSIMC) fed induction motor drive. More than a decade the voltage-source inverter (VSI) and current-source inverter (CSI) have been used to control the speed of the induction motor, which in turns controls the flow of dye. Recently, the matrix converter (MC) has been an excellent competitor for the VSI or CSI for its compactness. The voltage transfer ratio of the VSI, CSI, and MC has been limited to 0.866. Thus, the efficiency of these converters is less. To improve the voltage transfer ratio the quasi-Z-source network (QZSN) is to be used between voltage source and indirect MC (IMC). The modification in the shoot-through duty ratio of the QZSN varies the voltage transfer ratio greater than 0.866. Different voltage transfer ratios are needed for different voltage sag conditions. For a variation of the duty ratio of the QZSN, the fuzzy logic controller has been presented. To control the IMC vector control with space vector modulation has been presented. This paper proposes the implementation of QZSIMC adjustable speed drive for the flow control of dye in paper mill during different voltage sag conditions. A 4-kW prototype has been built and the effectiveness of the proposed system is verified with simulation results and experimental setup. Simulation is done in MATLAB, Simulink platform. Experimental setup is done with the aid of a TMS320F2812 (Texas Instrument) processor. The experimental results validate the maintenance of the speed of an induction motor at the set condition, thus controlling the perfect flow of dye in paper manufacturing technology. [ABSTRACT FROM AUTHOR]

A new multi gain SC inverter topology with fewer switching components and lower voltage stress is presented in this paper. It comprises eight switches and two capacitors, which raise the output voltage by three times the supply voltage. The capacitors voltages are automatically balanced to ensure proper operation. The circuit constructional, operation, and parameter optimisation techniques are discussed in details. A simple logic-based multicarrier Level Shift Pulse Width Modulation (LS-PWM) is employed to control the switching operation that reduces the complexity of the control circuit. Furthermore, a comparative analysis with other recent topologies has been presented to demonstrate the virtues of this approach. Finally, the proposed topology (PT) verification, feasibility, and effectiveness have been demonstrated both in simulation and experimentation. [ABSTRACT FROM AUTHOR]

Summary: This paper proposes a new floor function single carrier‐based modulated model predictive current control technique (FF‐SC‐M2PC2T) by considering conventional nine‐level T‐type packed U‐cell (9L‐TPUC) inverter topology. To get desired peak value of load current with low harmonic distortion, the finite control set‐based model predictive control technique (FCS‐MPCT) has been reported in the literature considering load dynamics and minimization of the cost function. However, inherently it suffers from variable switching frequency (VSF) of operation. To diminish this issue, an M2PC2T has been implemented and it provides a constant switching frequency (CSF) of operation. Especially coming to the modulation stage, most authors generally use level‐shifted pulse width modulation (PWM) techniques which inherently require more carriers, if‐else conditions, and additional logical gate blocks to generate particular level output. Hence, the control complexity increases as going to higher‐level inverter topologies. In this manuscript, a new simple floor function single carrier‐based pulse width modulation (FF‐SC‐PWM) technique has been proposed which applies to any single‐phase switched capacitor type multilevel inverter topology and it can be easily integrated with a predictive control algorithm to regulate the inverter output current (IOC). Finally, to check the effectiveness of the proposed control technique (PCT) in a closed loop, a laboratory prototype has been employed on 9L‐TPUC inverter topology with different static and dynamic case studies considering RL‐Load. [ABSTRACT FROM AUTHOR]

Summary: In this paper, a new floor function (F2) single‐carrier (SC)‐based modulated model predictive current control technique (M2PC2T) has been proposed by considering the conventional single‐phase five‐level packed U‐cell (PUC5) inverter topology. Generally, to regulate the output current, the finite control set‐based MPC technique without a modulator inherently operates with variable switching frequency, and it is unsuitable for industrial applications. To alleviate this, authors have implemented M2PC2T, which provides constant switching frequency of operation. In this technique, generally, the predictive algorithm has been integrated with any modulation stage. However, while the implementation of pulse width modulation (PWM) techniques, most authors have used conventional PWM techniques which further increases the control complexity as the level number increases. In this manuscript, a simple and generalized F2‐SC‐PWM technique has been proposed and integrated with the predictive algorithm. This PWM technique implementation process is very simple as compared with all conventional PWM techniques since even if the level number increases, the number of modulating and carrier signals is always only one. Finally, the complete closed‐loop control technique is called a generalized F2‐SC‐M2PC2T which is suitable for all stiff direct current (dc) sources and switched capacitor‐type multilevel inverter (MLI) topologies. The proposed control technique (PCT) has been experimentally verified with different transient and steady‐state case studies by considering resistive‐inductive load. [ABSTRACT FROM AUTHOR]

Summary: A new floor function single carrier‐based modulated model predictive current control (F2‐SCM2PC2) technique has been proposed in this paper by considering traditional single‐phase quadruple boost switched capacitor‐based multilevel inverter (QB‐SCMLI) topology. Conventionally, the implementation process of single modulating and single carrier‐based pulse width modulation (PWM) techniques are very much complex and finite control set‐based model predictive control (FCS‐MPC) technique inherently operates with variable switching frequency (VSF) operation, which is not suitable for industrial applications. To alleviate the aforementioned issues, a new generalized closed‐loop F2‐SCM2PC2 technique has been proposed. It consists of a simple PWM implementation process and can easily be integrated with a predictive algorithm, thereby providing a constant switching frequency (CSF) of operation. The particular single modulating and single carrier‐based PWM technique with floor function is also suitable for low and high switching frequency (LSF‐HSF) operations. The validation of floor function‐based PWM technique in open‐loop and closed‐loop F2‐SCM2PC2 techniques has been effectively verified through experimentation on QB‐SCMLI topology with consideration of resistive–inductive load. [ABSTRACT FROM AUTHOR]

In this proposed paper, multicarrier sinusoidal pulse width modulation (M-SPWM) method is implemented for design of 15 level reduced switches inverter topology. This inverter topology generates 15 level output-voltage with suitablelswitching pulse production using M-SPWM and altered level of voltages are attained with distinction of modulationlindex. The split inductor is used to diminish the harmoniclcontent and flatted output current. This type of system which contains different range of different range of voltage supplies. As a result, this inverter reduces the difficulty in gating time calculation and there is no neutral point fluctuation issue. This paper illuminates the modes of switching and minimization of stress in voltage and harmonic diminution are examined. The grades of the projected multilevel inverter (MLI) system are verified using Matlab/Simulink and dsPIC controller respectively. [ABSTRACT FROM AUTHOR]

Purpose: Multilevel inverters become very popular in medium voltage applications owing to their inherent capability of reconciling stepped voltage waveform with reduced harmonic distortion and electromagnetic interference. They have several disadvantages like more number of switching devices required and devices with high voltage blocking and need additional dc sources count to engender particular voltage. So this paper aims to propose a novel tri-source symmetric cascaded multilevel inverter topology with reduced number of switching components and dc sources. Design/methodology/approach: A novel multilevel inverter has been suggested in this study, offering minimal switch count in the conduction channel for the desired voltage level under symmetric and asymmetric configurations. This novel topology is optimized to prompt enormous output voltage levels by employing constant power switches count and/or dc sources of voltage. The topology claims its advantages in generating higher voltage levels with lesser number of voltage sources, gate drivers and dc voltage sources. Findings: The consummation of the proposed arrangement is verified in Matlab/Simulink R2015b, and an experimental prototype for 7-level, 13-level, 21-level, 29-level, 25-level and 49-level operation modes is constructed to validate the simulation results. Originality/value: The proposed topology operated with six new algorithms for asymmetrical configuration to propel increased number of voltage levels with reduced power components. [ABSTRACT FROM AUTHOR]

Multilevel inverters (MLIs) have recently received a lot of attention in the power conditioning of photovoltaic (PV) applications. For a photovoltaic system, one of the indispensable necessities is reliability. This becomes even more vital in distant and isolated areas inaccessible for maintenance. The reliability of multilevel inverters used in photovoltaic systems is very low or vulnerable due to the high failure rate of power devices. Therefore, a new single-phase 9-level fault-tolerant topology multilevel inverter is proposed in this paper. The proposed 9-level fault-tolerant topology is able to tolerate single switch and multiple switch failures. Verification of fault-tolerance and source utilization is carried out from the experimental results and reliability evaluation is done mathematically. The process employs the analysis of failure rates of the switches and diodes of the multilevel inverter circuitry and estimation of reliability and mean time to failure (MTTF) is carried out before and after the employment of the proposed scheme using the Markov process. The sinusoidal pulse width modulation (SPWM) control method has been used as a modulation strategy to control the output voltage. The experimental results validate the effectiveness of the proposed 9-level fault-tolerant MLI topology during healthy, faulty and post-fault conditions is presented. In addition, the total harmonic distortion (THD) of the proposed 9-level fault-tolerant MLI topology during healthy and post-fault conditions is presented in the paper. Finally, the proposed 9-level fault-tolerant topology is a lesser device count compared with the existing topologies. [ABSTRACT FROM AUTHOR]

This paper presents a switched-capacitor topology with fewer switching components and reduced voltage stresses. The circuit contains eight switches and two capacitors to generate a five-level voltage waveform. This paper provides in-depth descriptions of the structural design, operation, and loss analysis. Inherently self-balanced capacitors are utilized in the proposed topology, which eliminates the need for additional charge balancing circuits and sensors. The control action was implemented using a simple logic-based multicarrier pulse width modulation (PWM) strategy. A brief comparative analysis with state-of-the-art topologies has been presented to demonstrate the merits of the developed topology. Finally, the feasibility and efficacy of the suggested topology have been evaluated using simulation and experimental testing to ensure that it is both feasible and effective. [ABSTRACT FROM AUTHOR]

In this paper, a reduced‐component switched‐capacitor boost multilevel inverter (SC‐BMLI) topology is proposed for off‐grid and on‐grid applications. Recently, switched‐capacitor‐based multilevel inverter (MLI) topologies have been employed to avoid the need for multiple isolated direct current (DC) sources when compared with traditional cascaded MLIs. To generate a nine‐level stepped‐up voltage across the load, the SC‐BMLI needs only eight power switches and two capacitors. To get the appropriate nine‐level switching pattern, phase disposition pulse width modulation (PD‐PWM) has been used. An extended 13‐level boost multilevel inverter (BMLI) is also discussed in this paper. The proposed topology is connected to the grid to control the grid current using synchronous reference frame‐based proportional–integral controller. A small‐signal modeling and analysis has been discussed in detail for the phase‐locked‐loop (PLL). Moreover, to prove the superior performance of the SC‐BMLI, comparative analysis with an existing single DC source MLI has also been performed. The feasibility of the 9‐level and 13‐level proposed topologies, with and without the grid‐connection, is evaluated by Matlab/Simulink simulation and verified by an experimental study using the OPAL‐RT 4510 real‐time platform. Further, prototype model of nine‐level BMLI has been developed in the laboratory using DSpace 1103 controller and results are compared with simulation. [ABSTRACT FROM AUTHOR]

This paper presents a new DC to AC Modular Multilevel Converter (MMC) topology. The proposed topology requires less number of arms than the traditional MMC to generate equal magnitude and excellent quality of output AC voltage. The positive arm of the proposed converter is having submodules similar to traditional MMC. In contrast, passive tuned LC filters are present in the place of the negative arms in the proposed MMC topology. This helps to generate an equal magnitude of output AC voltage as traditional MMC with half of the input DC bus voltage magnitude. Additionally, traditional MMC requires large number of submodules to generate many voltage levels and hence create small steps in the output voltage matching close to a sine wave. The passive tuned LC filters in the proposed circuit topology are designed to absorb the switching harmonics generated from the positive arms. This makes the output AC voltage very close to a pure sine wave, with highly reduced higher order switching harmonics. This paper explains the operational principle along with the pre-charging of the submodule capacitors at start-up of the new converter. Simulation and experimental studies confirm the operation of the new converter topology. [ABSTRACT FROM AUTHOR]

Modular multilevel converters (MMCs) have been conceived as an alternative in front-end converter applications to enhance the converter system's reliability, minimize total harmonic distortion, and improve power quality. These converters utilize several DC-link capacitors and power electronic switches, along with switches operating with high switching frequencies, to attain the desired characteristics. Thereby, this paper systematically proposes a novel three-phase asymmetric hybrid modular multilevel converter (AHMMC) for front-end converters used in lower-medium-voltage applications. The AHMMC configuration is based on a three-phase converter connected to a per-phase series arrangement with a cascaded converter module (CCM). The study investigates the AHMMC and proposes a control scheme, which minimizes the voltage range on switches and maintains the current to its reference value. Furthermore, the study also introduces an active balancing of voltage across DC-link capacitors based on the phase opposition disposition PWM (POD-PWM) method. Our new configuration has features such as low switching loss, reduced DC-link voltage, a wider modulation range for the unity power factor (PF), and low voltage and current harmonic distortion. The simulation results are added to verify the performance of the new AHMMC topology and the usefulness of the modular control scheme. In addition, a low-voltage laboratory prototype based on customized control and power boards is built to validate the proposed converter and its control scheme in practice. [ABSTRACT FROM AUTHOR]

In this paper, a new active impedance source inverter with a suitable control method based on the pulse‐width modulation (PWM) technique is proposed. Based on the proposed control method, the analysis of the proposed inverter in different operating modes is given, and its boost factor is calculated. Then, the fundamental equations to design the values of inductors and capacitors are presented. Also, comparative analysis from different points of view, such as boost factor, voltage stresses on capacitors, and total voltage blocked by diodes and switches, between the proposed topology and conventional structures to examine the advantage and disadvantages is done. Comparison results show that the proposed topology has fewer voltage stresses on capacitors and total voltage blocked by diodes and switches. Also, it has fewer elements and continues input current and a more straightforward structure. The proposed topology's losses and efficiency at different loads are fully calculated. Finally, a prototype of the proposed topology is designed, and its experimental results along with simulation results by PSCAD to check the proposed topology's good performance and correctness of the obtained equations in different operating modes are provided. [ABSTRACT FROM AUTHOR]

In this paper, some recently proposed multilevel power converters are investigated for their fault-tolerant capabilities and improved reliability. These reported topologies are generally reduced device multilevel inverter (RD-MLIs) configurations that cannot tolerate switch failures due to absence of redundant states. Present work therefore aims to incorporate open-circuit fault-tolerant capability by adding few redundant states in switching sequences of existing topologies. The work in this paper objectively presents two existing topologies of five-level and seven-level Multi-Level Inverters (MLIs) modified for fault-tolerant (FT) capability against single switch open-circuit (OC) faults. The modification for fault-tolerant feature (FT-MLI) has intrinsic self-voltage balancing capability, low cost and control simplicity. The modified FT-MLI uses multi-carrier sinusoidal pulse-width modulation (SPWM) technique to generate control switching pulses as per desired switching sequences. Simulation and experimental results of these modified FT-MLI topologies under healthy, faulty and post-fault mode are presented and discussed. Experimental results verify the feasibility and effectiveness of these modified FT-MLI topologies which are suitable for safety-critical applications. [ABSTRACT FROM AUTHOR]

The multilevel inverter is widely used for medium voltage and high power applications. However, the application is limited due to the need for more number of switches, diodes and the system complexity. The proposed inverter is a hybrid topology with two-level and three-level diode clamped multilevel inverter structure with a reduced number of switches, diodes and gate driver circuits for dual output, which reduces system cost and complexity. In general, diode clamped multilevel inverter needs 24 switches to control dual output. In this paper, it was reduced as 15 switches and 12 switches by sharing of middle switches. The simulation was carried out by MATLAB Simulink and the hardware results were compared with simulation results. Also, modulation index, switching frequency and different topology with R, and RL loads were discussed and compared. The experimental plan was developed as per the Box–Behnken method and the experiments were carried out. The results were statistically analyzed and its significance was tested. [ABSTRACT FROM AUTHOR]

This paper presents a novel topology called the capacitor-assisted active-switched quasi Z-source inverter (CA/AS-qZSI). The proposed CA/AS-qZSI topology has a high ac voltage gain and low voltage and current stresses on the diodes and extra switch in the Z-network. The design guide of the passive elements used in the proposed topology and a comparative study of the proposed CA/AS-qZSI and four other topologies with an active-switched impedance network are addressed. A new pulse-width modulation (PWM) technique using a sawtooth carrier signal is also suggested to reduce the switching losses of the diodes and switches. Compared with the traditional simple boost control method, the efficiency of CA/AS-qZSI using the new PWM technique is improved by 4–4.6%. The experimental results utilizing a prototype made in the laboratory demonstrate the performance of the proposed CA/AS-qZSI and PWM technique. [ABSTRACT FROM AUTHOR]

Multilevel inverters (MLI) consist of a wide range of power converters. They have many designs and have been introduced with different circuit topologies such as neutral point clamped, diode clamped, cascaded H-bridges, and flying capacitors. Some of these MLIs have disadvantages, including design complexity, size, and losses due to the large number of switching devices required when they produce many output voltage levels. They are also bulky in size and may require several DC power sources. This paper presents a review of the various topologies of single-phase T-Type MLIs (T-MLIs). These MLIs are used to convert DC power from renewable energy sources (RES)" into AC with a near-sine waveform and low total harmonic distortion (THD). Simple and complex MLI designs are discussed. The major types of modulation techniques are discussed, including sinusoidal pulse width modulation (SPWM), selective harmonic elimination (SHE), and preprogrammed PWM. Various methods of output voltage control are taken into consideration as well. The aim of this comprehensive survey is to identify T-MLIs for researchers and those interested in the power conversion field, as well as to discuss the many topologies, identifying designs with superior characteristics that can be efficiently implemented with RESs to obtain better AC voltage with enhanced power quality. [ABSTRACT FROM AUTHOR]

With the continuous development of new energy power generation and smart grid, Power Electronic Transformer (PET) has a good prospect for development because of its remarkable advantages. Based on the topology of AC/DC/AC, the modulation strategy with dual-PWM (Pulse Width Modulation) is adopted to control the operation of power electronic transformers in this paper. The PET structure consists of three units: importation portion, isolation portion and output portion. Model building and analyzing both at the input and output terminals are achieved step by step. And the simulation of the whole PET system with dual-PWM is accomplished with MATLAB/ Simulink. The simulation results show the control system stability and output voltage regulation precision are improved with feed-forward voltage decoupling vector control system. The correctness and effectiveness of the control strategy are demonstrated through the simulation. PETs play an important role in enhancing power supply reliability for Power Grid and promoting the new energy power generation development. [ABSTRACT FROM AUTHOR]

In order to meet the operation requirements of the beam supply with multi-working conditions, multi-modes and high efficiency, a dual-mode hybrid output control method combining phase-shifting and pulse-width dual-mode modulation technology with secondary side series-parallel operation is proposed. In this paper, the structure and working mode of the new dual full-bridge topology are firstly analyzed. Secondly, the main circuit parameters are designed according to the power performance indicators, and the losses under two control modes of phase shift and pulse width are calculated. Finally, comparing the losses of these two control methods, and combining the series-parallel operation mode of the secondary side of the transformer, a dual-mode switching control method of the beam supply is designed. In order to verify the rationality of the dual-mode mixed output control method, a principle prototype with a rated capacity of 2 kW, a rated voltage of 1 800 V and a switching frequency of 50 kHz was used for verification. Experiments show the effectiveness and superiority of the dual-mode hybrid output control method. [ABSTRACT FROM AUTHOR]

This paper proposes a novel dual input nine-level inverter (DINLI) topology which requires only seven controllable devices. The dual inputs are un-identical DC voltage sources in the ratio 1:3. A simple control scheme is derived by appropriately modifying the phase disposition pulse width modulation technique to generate high-quality 9-level output from the DINLI topology. At any given instant, a maximum of four switches conduct out of which only a maximum of two switches operate at high frequency, bringing down the switching and conduction losses significantly and improving the overall system efficiency. The bidirectional DINLI (BDINLI) topology with reactive power capability can be realized by replacing the unidirectional devices with the controlled switches (i.e., total nine switches). In addition, the proposed DINLI topology does not require extra voltage balancing circuits which further improves the efficiency. The DINLI operation is verified through MATLAB simulations for grid-connected applications and its extension to an n-level, 3-phase application is also investigated. Experiments performed on a 1KVA laboratory prototype to validate the theoretical claims. [ABSTRACT FROM AUTHOR]

Purpose: This paper aims to propose a new MLI topology with reduced number of switches for photovoltaic applications. Multilevel inverters (MLIs) have been found to be prospective for renewable energy applications like photovoltaic cell, as they produce output voltage from numerous separate DC sources or capacitor banks with reduced total harmonic distortion (THD) because of a staircase like waveform. However, they endure from serious setbacks including larger number of capacitors, isolated DC sources, associated gate drivers and increased control difficulty for higher number of voltage levels. Design/methodology/approach: This paper proposes a new three-phase multilevel DC-link inverter topology overpowering the previously mentioned problems. The proposed topology is designed for five and seven levels in Matlab/Simulink with gating pulse using multicarrier pulse width modulation. The hardware results are shown for a five-level MLI to witness the viability of the proposed MLI for medium voltage applications. Findings: The comparison of the proposed topology with other conventional and other topologies in terms of switch count, DC sources and power loss has been made in this paper. The reduction of switches in proposed topology results in reduced power loss. The simulation and hardware show that the output voltage yields a very close sinusoidal voltage and lesser THD. Originality/value: The proposed topology can be extended for any level of output voltage which is helpful for sustainable source application. [ABSTRACT FROM AUTHOR]

In this paper, two (series and parallel versions) quasi Z source inverter (qZSI)-based multioutput series-parallel topologies capable of supplying multiple three-phase AC and single boost DC outputs simultaneously are presented. The proposed parallel version topology can supply n number of AC outputs along with one boost DC with constant voltage and variable current. Similarly, the series version topology can give n number of AC including one boost DC output with constant current and variable voltage. The outputs of the proposed topologies can feed directly to DC/AC microgrids and multiple residential loads simultaneously without using any extra adapter/regulator and thereby avoiding local power conversion to meet the load demand. A hybrid pulse width modulation technique with constant frequency is used to operate the proposed topologies. The performance of the proposed topologies is verified by developing the prototypes of 2.18 kW (for parallel version) and 2.02 kW (for series version) for two three-phase AC outputs and one boost DC output. The developed prototypes show measured efficiency of 90.01% for the parallel and 89.95% for the series version topology. [ABSTRACT FROM AUTHOR]

The Reduced Asymmetric Neutral Point Clamped converter topology for unipolar driven, multiphase switched reluctance machines is proposed in this paper. This topology shares similarities with the conventional NPC and Asymmetric-NPC topologies, however it is unique in that the components for the capacitor string and outer semiconductor switches are shared among all the phases for a reduced component count. Some switching state combinations are not possible during commutation overlap between motor phases, resulting in minor torque transients during regenerative braking. A custom modulation scheme is implemented with fixed frequency, phase-shifted carrier waveforms that allow for automatic balancing of the neutral point voltage and interleaved switching of the semiconductor switches. A simple torque observer control architecture is used with minor adjustments for arbitrating torque contribution priorities between phases during handover. [ABSTRACT FROM AUTHOR]

In this paper, two (series and parallel versions) quasi Z source inverter (qZSI)-based multioutput series-parallel topologies capable of supplying multiple three-phase AC and single boost DC outputs simultaneously are presented. The proposed parallel version topology can supply n number of AC outputs along with one boost DC with constant voltage and variable current. Similarly, the series version topology can give n number of AC including one boost DC output with constant current and variable voltage. The outputs of the proposed topologies can feed directly to DC/AC microgrids and multiple residential loads simultaneously without using any extra adapter/regulator and thereby avoiding local power conversion to meet the load demand. A hybrid pulse width modulation technique with constant frequency is used to operate the proposed topologies. The performance of the proposed topologies is verified by developing the prototypes of 2.18 kW (for parallel version) and 2.02 kW (for series version) for two three-phase AC outputs and one boost DC output. The developed prototypes show measured efficiency of 90.01% for the parallel and 89.95% for the series version topology. [ABSTRACT FROM AUTHOR]

In this paper, two (series and parallel versions) quasi Z source inverter (qZSI)-based multioutput series-parallel topologies capable of supplying multiple three-phase AC and single boost DC outputs simultaneously are presented. The proposed parallel version topology can supply n number of AC outputs along with one boost DC with constant voltage and variable current. Similarly, the series version topology can give n number of AC including one boost DC output with constant current and variable voltage. The outputs of the proposed topologies can feed directly to DC/AC microgrids and multiple residential loads simultaneously without using any extra adapter/regulator and thereby avoiding local power conversion to meet the load demand. A hybrid pulse width modulation technique with constant frequency is used to operate the proposed topologies. The performance of the proposed topologies is verified by developing the prototypes of 2.18 kW (for parallel version) and 2.02 kW (for series version) for two three-phase AC outputs and one boost DC output. The developed prototypes show measured efficiency of 90.01% for the parallel and 89.95% for the series version topology. [ABSTRACT FROM AUTHOR]

In this paper, two (series and parallel versions) quasi Z source inverter (qZSI)-based multioutput series-parallel topologies capable of supplying multiple three-phase AC and single boost DC outputs simultaneously are presented. The proposed parallel version topology can supply n number of AC outputs along with one boost DC with constant voltage and variable current. Similarly, the series version topology can give n number of AC including one boost DC output with constant current and variable voltage. The outputs of the proposed topologies can feed directly to DC/AC microgrids and multiple residential loads simultaneously without using any extra adapter/regulator and thereby avoiding local power conversion to meet the load demand. A hybrid pulse width modulation technique with constant frequency is used to operate the proposed topologies. The performance of the proposed topologies is verified by developing the prototypes of 2.18 kW (for parallel version) and 2.02 kW (for series version) for two three-phase AC outputs and one boost DC output. The developed prototypes show measured efficiency of 90.01% for the parallel and 89.95% for the series version topology. [ABSTRACT FROM AUTHOR]

Four-level hybrid-clamped inverter is a newly proposed topology that can operate under a wide voltage range without switches connected in series. However, when it is applied in medium voltage high power conversions, the flying capacitors in each phase will occupy a huge volume and a high switching frequency is required to restrain the voltage ripples. In order to overcome this drawback, a four-level active neutral-point clamped inverter is discussed in this paper, which consists of only six switches and no diodes or flying capacitors are required. In order to balance the neutral-point voltages under the full power factor and modulation index range, a capacitor voltage balance method based on carrier-overlapped pulsewidth modulation is proposed in this paper. The upper and lower dc-link capacitor voltages are balanced by zero-sequence voltage injection and the central dc-link capacitor voltage is balanced by adjusting the duty cycles of switching signals slightly. Simulation and experimental results are presented to confirm the validity of this method. [ABSTRACT FROM AUTHOR]

The development of wide band-gap semiconductor devices is rapidly promoting the development of power electronics technology, especially in high frequency (HF) power converter region. A category of HF power converter is switch-mode power amplifier (PA). This paper focuses on the implementation of a multiphase dc–dc PA with high bandwidth and high power rate. When naturally sampled phase-shifted carrier modulation is implemented in the practical digital control system to control this HF power converter, the pulsewidth error problem caused by limited domain frequency of control chip becomes much severer. As a result, dc voltage component of each phase becomes different under several conditions, leading to current imbalance among phase inductors. This paper analyzes this problem and proposes a sensorless control method to solve it, based on the injection of random sequence in reference wave. A four-phase prototype employing GaN devices is fabricated, switching at 1 MHz. Current imbalance and effectiveness of the proposed control method are verified by experimental results. The prototype is capable of uniformly amplifying sine signal within 200 kHz and a 350 kHz bandwidth random signal, with peak output power up to 810 W. [ABSTRACT FROM AUTHOR]

This paper presents a 5-level inverter topology for open-end induction motor drives by using a single dc source. The open stator windings of the drive are supplied with a 3-level flying capacitor inverter from one end and capacitor-fed 2-level inverter from another end. The voltage ratio of the dc link to the capacitor in 2-level inverter is maintained at 4:1 ratio to generate five-level voltage output. The capacitor in 2-level inverter is balanced by the switching redundant vector combinations from both the inverters while the floating capacitors in the 3-level inverter are balanced by using redundant switching states. The proposed topology gives 5-level operation with less number of floating capacitors and power semiconductor switches compared to other existing topologies. Also, the balancing of the capacitors is independent of load power factor and modulation index. Further, the generalization of the proposed dual inverter scheme for any n-level inverter is also included in this paper. The experimental results and required analysis are also presented to validate the inverter scheme. [ABSTRACT FROM AUTHOR]

This paper proposes a generalized 3-phase cascaded multilevel inverter (CMLI) along with a simplified space vector pulse width modulation (SVPWM) based on 2-level inverter (2LI) topology. While conventional cascaded H-bridge inverters (CHBIs) call for a number of DC sources which increase the cost and complexity of their implementation, the proposed CMLI requires one DC source only. On the other hand, the complexity of SVPWM lies in the switching diagram that consists of a large number of triangles comprising uneven numbers of switching vectors. The generalized 3-phase CMLI proposed in this paper is aimed at reducing the number of switching vectors of each triangle. The hypothesis of the proposed CMLI-SVPWM is firstly illustrated through extensive simulation analysis using MATLAB/SIMULINK software. Feasibility of the proposed inverter is then validated through experimental measurements on a hardware prototype. Results reveal the superiority of the proposed inverter over existing ones in terms of the quality of the output voltage and current waveforms and the overall efficiency. [ABSTRACT FROM AUTHOR]

This paper presents a novel seven-level inverter topology for medium-voltage high-power applications. It consists of eight active switches and two inner flying capacitor (FC) units forming a similar structure as in a conventional active neutral-point-clamped (ANPC) inverter. This unique arrangement reduces the number of active and passive components. A simple modulation technique reduces cost and complexity in the control system design without compromising reactive power capability. In addition, compared to major conventional seven-level inverter topologies, such as the neutral point clamped, FC, cascaded H-bridge, and ANPC topologies, the new topology reduces the dc-link voltage requirement by 50%. This recued dc-link voltage makes the new topology appealing for various industrial applications. Experimental results from a 2.2-kVA prototype are presented to support the theoretical analysis presented in this paper. The prototype demonstrates a conversion efficiency of around 97.2% ± 1% for a wide load range. [ABSTRACT FROM AUTHOR]

A novel pulsewidth modulation (PWM) scheme for the decoupled and coordinated control of two parallel connected split-phase induction machines is discussed in this paper for the first time. Both the motors are operated from a single six-phase voltage source inverter which acts as a power source, and two switched capacitor-fed auxiliary inverters to limit the flow of nontorque producing currents in each motor. Both the motors can be operated at its full rated power with low switching frequency, and decoupled control for full power range can be achieved with the proposed topology. This is possible because the individual machines do not carry the load/harmonic currents of other machine (unlike the conventional series or parallel connected systems). The converters can be modulated using sine-triangle PWM or space vector pulsewidth modulation (SVPWM). Furthermore, two different schemes of SVPWM techniques are proposed and compared in this paper. Exhaustive experimental results for all the modulation schemes are provided for steady state and transient operating conditions including start-up to validate the proposed topology and modulation schemes. [ABSTRACT FROM AUTHOR]

The number of applicable carrier-based pulsewidth modulation (PWM) patterns increases with the growth of output levels in scalable multilevel topologies, such as active-neutral-point-clamped (ANPC) converters. Therefore, it is hard to optimize PWM for such topology, especially with large output levels. In this paper, a simplified and modular carrier-based PWM design approach for multilevel ANPC converters is proposed. Inspired by the decomposition theory, the topology decomposition is introduced in this paper to decompose an N-level ANPC converter into low-level subtopologies. Then, the complete set of applicable PWM patterns is derived based on ANPC operation principles, which makes it possible to optimize the performance based on the various requirements in applications. Meanwhile, the carrier-based PWM is implemented through the utilization of subtopologies with low-level modulation schemes, such that the design process of carrier-based PWM is greatly simplified and modularly realized. Both the complete PWM patterns and PWM design examples with experimental results of several ANPC converters are provided to show the feasibility and modularity of the proposed method. [ABSTRACT FROM AUTHOR]

This paper proposes a new class of topologies of single-stage high-frequency ac-link power converters, which is capable of providing both voltage step up/down within a wide frequency and voltage ranges. The proposed family, which supports bidirectional power flow, can interface various single/multi-port dc and/or single/multi-phase ac systems to provide dc–dc, dc–ac, ac–dc, or ac–ac power conversion. In this family of converter, which offers a very modular structure, a small inductor that forms the link exchanges power entirely or partially between the source and load. The proposed family can function in buck, boost, and/or buck–boost modes of operation, and a combination of these modes of operation is also feasible. In comparison to the parallel inductive four-quadrant link converters, the proposed family features a significantly reduced link peak current, reduced switch ratings, and reduced total number of power switches. These features enhance the efficiency, reduce the total cost, and increase the power density of the system. In order to further improve the overall efficiency of the system, minimize the current/voltage stress over all utilized semiconductor devices, and lower electromagnetic interference (EMI), a small capacitor is placed in parallel with the link inductor to realize soft-switching operation for the proposed configurations. Moreover, the proposed converters have the potential to incorporate a lightweight single-phase high-frequency transformer for electrical isolation. The proposed circuit topologies prevent reverse recovery issues and eliminate losses corresponding to body diodes of power switching devices via utilizing power switches in conjunction with external fast recovery diodes. The proposed family offers a very high level of reliability owing to its immunity from short circuit of input and output terminals and open circuit of the link inductor, which may occur in other power converters due to commutation problem resulting from a short deadtime or an overlap time between switches, unwanted control command, delay in electronic circuits, or EMI noise's misgating on or off, in addition to the absence of electrolytic capacitors in the power circuit. A control approach is also developed to regulate input and output currents in one stage of power conversion. A detailed theoretical analysis, operation, design methodology, and control strategy of the proposed family are provided in this paper, and the effectiveness and performance of the proposed converter family are verified via simulation results and experimentally. [ABSTRACT FROM AUTHOR]

In this paper, a new class of bidirectional partial-resonance power converters is presented. The proposed family can be configured to interface single- or multi-port dc, single- or multi-phase ac systems at input-side and/or output-side. The proposed family offers a very modular structure, which can lead to cost reduction from a common designed module. In this converter, which accomplishes power conversion in a single stage, a small inductor placed in series with the input and output switch-bridges forms the link. This small link inductor is responsible for transferring power between different ports of the system. The proposed topologies can operate in buck, boost, and buck–boost modes of operation to step up and/or step down the voltage. In buck–boost mode of operation, the converter is controlled such that the power is entirely transferred through the link inductor; whereas, in buck or boost modes of operation only a fraction of the power is transferred through the link inductor, and the remaining power is directly transferred from input phases to the output phases. Galvanic isolation, which is typically a prominent factor contributing to power density of a converter, can be provided by means of a compact and lightweight single-phase high-frequency transformer added to the link. In comparison with earlier generations of partial-resonance inductive-link power converters, in the proposed converter, the level of link peak current and consequently power-loss, as well as voltage and current stress of switches are dramatically decreased. A very small film capacitor can be placed in parallel with the link inductor to facilitate zero-voltage-switching (ZVS) operation for all the switches/diodes. Apart from increasing the overall efficiency, minimized dv/dt stress and improvement in power density are achieved by adding the link capacitor. The proposed converter employs four-quadrant switches, i.e., bidirectional-conducting bidirectional-blocking switches, and charges the link inductor in both positive and negative directions in each cycle. In view of this, better utilization of the link inductor and lower total harmonic distortion (THD) are offered. Furthermore, two distinct switching algorithms are developed for the proposed family of converters. In this paper, the detailed behavior of the proposed family is investigated analytically, and simulation and experimental results are presented to evaluate the performance and effectiveness of the proposed converter. A low-power proof-of-concept prototype with input voltage of 59 V/161 V, load voltage of 178 V/73.5 V, maximum switching frequency of 4.9 kHz/3.65 kHz at 215 W/450 W in a step-up/step-down operation is considered for the experimental verification. [ABSTRACT FROM AUTHOR]

In this paper, two (series and parallel versions) quasi Z source inverter (qZSI)-based multioutput series-parallel topologies capable of supplying multiple three-phase AC and single boost DC outputs simultaneously are presented. The proposed parallel version topology can supply n number of AC outputs along with one boost DC with constant voltage and variable current. Similarly, the series version topology can give n number of AC including one boost DC output with constant current and variable voltage. The outputs of the proposed topologies can feed directly to DC/AC microgrids and multiple residential loads simultaneously without using any extra adapter/regulator and thereby avoiding local power conversion to meet the load demand. A hybrid pulse width modulation technique with constant frequency is used to operate the proposed topologies. The performance of the proposed topologies is verified by developing the prototypes of 2.18 kW (for parallel version) and 2.02 kW (for series version) for two three-phase AC outputs and one boost DC output. The developed prototypes show measured efficiency of 90.01% for the parallel and 89.95% for the series version topology. [ABSTRACT FROM AUTHOR]

A new transformer-less three-level grid-tied inverter is proposed in this article. By employing the switched-capacitor (SC) modules, a new topology is derived. The proposed topology has some features which are high efficiency, the capability of voltage boosting without utilization of any additional boost stage, and suppressing the leakage current by using common grounded strategy. In this article, a peak current control is employed to generate the gate pulses of power semiconductor switches and adjustment of both active and reactive powers. By doing so, the grid injected current is controlled and adjusted to have a proper quality. The operation modes, design consideration, and a comparison with some recently proposed grid-connected topologies are done through this paper. Finally, the performance and feasibility of the proposed inverter are confirmed with a 500 W experimental prototype. [ABSTRACT FROM AUTHOR]

In high power applications, 3-phase ac/dc Voltage Source Converters (VSCs) are paralleled to increase the overall aggregated converter power rating, effective switching frequency and control bandwidth. For this, interleaved Pulse Width Modulation (PWM) and current limiting paralleling inductors are required. Interphase Transformers (ITRs) are often used for the converter paralleling because they provide large magnetizing inductances for the currents flowing between the converters while introducing negligible leakage inductances for the currents flowing from the converters to the ac grid. This large asymmetry in the inductance values makes it difficult to independently control active power flows in the individual converters. Thus, if the converters dc buses are not mutually interconnected, instabilities in active control of balance of converter dc bus voltages can occur in certain operational conditions. This paper presents a theoretical analysis of the active power flows produced by the currents flowing among the converters and explains origins of potential instability in the active control of balance of dc bus voltages in multi-converter systems with floating dc buses, paralleled using the ITRs. [ABSTRACT FROM AUTHOR]

This paper proposes a single-phase ac–dc–ac converter composed of a transformer and two three-leg converters connected in series. The proposed converter allows to supply the load with a voltage with constant amplitude and frequency, and to operate with the grid current with low harmonic distortion and high power factor. In addition, the converter can be used to mitigate fundamental overvoltage and voltage harmonics at the grid. The system model, regions of operation, a power flow analysis, and a method to regulate the dc-link voltages using the voltage vector redundancies are given. In the first version of this paper, two pulsewidth modulation (PWM) techniques (including space vector PWM) and a control system were provided. The proposed topology is compared with two conventional systems in terms of operation range, harmonic distortions, and semiconductor losses. Simulation and experimental results are provided to validate the feasibility of the system. [ABSTRACT FROM AUTHOR]

A trinary multilevel converter uses a few heterogeneous H-bridge submodules (SMs) to synthesize an output voltage with multiple levels. Two major limitations of this converter are that it needs multiple dc sources and it cannot operate under pulsewidth modulation (PWM). This paper addresses these limitations by adding a low-voltage H-bridge SM to this converter and proposing a new switching algorithm. The resulting PWM-based asymmetric cascaded H-bridge converter uses only one dc source and synthesizes a high-quality output voltage. This improved converter can be a potential choice for real and reactive power support in power system applications. This paper also proposes methods for stability analysis and design of this converter. Experimental case studies evaluate the performance of the proposed converter for both standalone and grid-connected modes of operation. [ABSTRACT FROM AUTHOR]

A modular multilevel converter (MMC) is regarded as a promising topology in high-voltage direct current systems. However, the MMC consists of numerous submodules (SMs) and switching devices, which lead to a considerable switching loss, and increased cost and size of the heat sink. To mitigate these issues, this paper presents a novel modulation method composed of fundamental frequency modulation (FFM) and multicarrier-based sinusoidal pulsewidth modulation schemes. The main purpose of this modulation method is the reduction of switching loss while maintaining good harmonic performance. However, the FFM scheme leads to the unbalanced capacitor voltage of each SM in the MMC. Accordingly, this paper additionally proposes the rotation method and selective voltage balancing control for SMs to ensure effective performance of the method. Simulation and experimental results verify the effectiveness and performance of the proposed modulation scheme through switching loss and spectral analyses. [ABSTRACT FROM AUTHOR]

This paper presents two capacitor voltage balancing (CVB) strategies for modular multilevel converter (MMC) applications. Both balancing schemes are based on model predictive control and are designed to efficiently solve a constrained optimal control problem, where the predicted capacitor voltage errors are included in the cost function with the demanded output voltage of a cluster being forced through an equality constraint. The first method proposed in this paper computes specific modulation indexes for each module using the explicit solution of a relaxed version of the original optimization problem. The second approach proposed in this paper reduces the complexity of the original problem by linearizing the objective function and using an optimal sorting network based on a greedy algorithm to solve this approximation. Considering the structures of both solution approaches, they are integrated into modulation schemes based on phase-shifted and level-shifted pulsewidth modulation algorithms, respectively. Experimental results obtained from a nine-cell single-phase MMC prototype demonstrate the good performance achieved with the proposed methodologies, as well as the implementation simplicity offered by the proposed CVB algorithms. [ABSTRACT FROM AUTHOR]

A nonisolated dc–dc converter with chain links of submodules (SMs) is proposed in this paper. The converter can perform as a dc transformer with a low step-up ratio. To demonstrate the step-up dc–dc conversion, the converter is operated in a resonant conversion mode, achieving soft switching and inherent balancing of the SM capacitor voltages. The circuit configuration is presented and the operation principle is analyzed in this paper. Experimental results based on a downscaled prototype validate the performance of the proposed converter as a low step-up ratio dc transformer. The converter also exhibits a good linearity covering a broad range. [ABSTRACT FROM AUTHOR]

This paper presents a new six-level flying capacitor based (FC-based) multilevel converter with one dc source and the capability of operating in all power factors and modulation indexes. Multilevel converters with one dc voltage source are attractive in many applications as they do not need rather expensive and bulky multiwinding input transformer connection at the dc side. On the other hand, not all classic multilevel converters with one dc source can produce any desirable number of output voltage levels at all power factors and/or modulation indexes. In this paper, a hybrid structure is proposed in which six voltage levels can be realized at the ac terminals. The modulation technique and the control strategy for the FC voltage balancing are presented. To show the advantages of the proposed converter, different performance criteria, such as switch count and rating, the size of capacitors, switching frequency, and power losses, are compared with other existing six-level topologies. The results indicate that the proposed structure is superior to other six-level converters from different standpoints. Simulation results are used to further evaluate the performance of the proposed converter. A laboratory-type experimental setup is used to validate the theoretical results. [ABSTRACT FROM AUTHOR]

In this paper, a new structure for a nonisolated boost dc–dc converter is proposed. The proposed converter generates higher voltage gain than some conventional nonisolated boost dc–dc converters. In this paper, the voltage and current equations of the elements and voltage gain in continuous conduction mode and discontinuous conduction mode are extracted. Then, the critical inductance converter is extracted and the current stresses in the switches are calculated. To achieve high voltage gain, a generalized structure based on the proposed structure generates for dc–dc converters. Meanwhile, the root mean square current relations of devices are obtained for an extended structure. Finally, the results of PSCAD/EMTDC software and laboratory prototype are used to reconfirm theoretical concept. [ABSTRACT FROM AUTHOR]

Impedance source inverters have experienced a fast evolution since the first release of the Z-source inverter in 2003. This evolution is not limited to improving the structure of the different topologies but also includes their modulation and control schemes in order to reinforce their performance from many perspectives. Accordingly, many modulation schemes have been proposed in different research activities, but the full differences among these modulation schemes, including their effect on the switching losses, are not clear yet to the researchers. Hence, this research activity is aimed at introducing a comprehensive review of these different modulation schemes employed for the three-phase impedance source inverters, which is enhanced with a comparative assessment. In this paper, different modulation schemes are classified and reviewed, introducing an important benchmark in order to identify the basic differences between these modulation schemes. In other words, from this paper, the concept of classifying the different modulation schemes and the mandatory equations to implement each scheme can easily be drawn. Moreover, this review is essential for the next part, i.e., Part II, in which a comparative assessment is introduced. [ABSTRACT FROM PUBLISHER]

Summary: This paper presents two nine‐level inverter topologies for open‐end winding induction motor drive with fault‐tolerance for all possible switch faults. The proposed topologies are designed with three voltage‐source inverters each with eight switches, an isolated DC source and a capacitor. The number of components and the scheme of connection employed for phase windings in both the topologies are identical. The voltage across the capacitors is controlled using the phase currents and hence does not require any additional pre‐charging circuit. The direction of phase currents flowing through the capacitors determines their charging and discharging states. Hence the proposed topologies are categorized as flying‐capacitor leg based topology (FCLBT) and switched‐capacitor based topology (SCBT) considering the technique employed for generating intermittent voltages. Although these topologies require three sources, the output voltage peak across each phase winding would be twice the source voltage, hence lower rating renewable energy sources can be employed as input sources. Conventional level‐shifted carrier sinusoidal pulse width modulation technique (SPWM) is employed for generating switching pulses. The proposed topologies employ reduced number of devices compared to existing similar nine‐level topologies and also exhibit fault‐tolerance for switch faults. The post‐fault operation of the proposed topologies does not require any additional hardware but necessitates the modifications of switching pulses. Simulations are performed in the MATLAB/Simulink environment and results are presented. A prototype is constructed to validate the performance of the proposed topologies and experimental results are presented. [ABSTRACT FROM AUTHOR]

Multilevel converters with floating capacitors (FCs) are widely applied in recent years in a wide range of industrial applications from high-voltage direct current systems to high power drives. However, some FC topologies lack complete FC voltage balancing capability due to the inherent topology limitation or the insufficient switching state for capacitor balancing. This will result in large ripples on capacitors at low frequency (such as fundamental frequency), limiting their performance and application, particularly, when the fundamental frequency is very low in low-speed drive operations. Typical examples of those multilevel converters are modular multilevel converters (MMC), nested neutral-point-clamped (NNPC) converter, etc. In order to improve the FC balancing for this kind of multilevel converters, this paper proposes a carrier-based pulse-width modulation (PWM) method, named stair edge PWM method. This method can obtain sufficient redundant switching states for FC voltage balancing by producing multiple levels in one PWM period. The FC voltage balancing is thus achieved at switching frequency, which can greatly reduce the capacitor voltage ripple and therefore enable the use of much smaller FCs. Meanwhile, the voltage stress on each device and low $dv/dt$ feature are still the same as the normal multilevel operation, reserving two of the most salient features of multilevel converters. The proposed method also features much simpler and easier implementation compared with space-vector-based approaches, particularly when high-level converters are considered. An application example using a four-level NNPC converter is provided in this paper. The effectiveness and performance of the proposed method are verified by both simulation and experiment. [ABSTRACT FROM AUTHOR]

In this paper, two structures are proposed for the switched-inductor quasi-Z-source inverter. In the proposed structures to extend the voltage gain of inverter, two new switched-inductor structures are used. In the proposed structures, voltage across the capacitors in the Z-source network and in the switched-inductor is symmetric and small. The other advantage of proposed inverters is known as achieving higher voltage gain per smaller duty cycle ratio (of shoot-through). Compared with a conventional continuous input current switched-inductor quasi-Z-source inverter at the same gain voltage, there is less of a ripple of input current in the proposed inverters. In this paper, at first the both the conventional and the proposed switched-inductor Z-source inventers are thoroughly investigated to find out their governing relations. Then, the proposed Z-source inverters are compared with the conventional ones by simulating them to assess their performance efficiency. Next, applying the simple boost pulse width modulation the simulation is carried out with PSCAD/EMTDC software. After that, to evaluate the obtained results, the prototypes of the proposed inverters with 48 Vdc input voltage are used. [ABSTRACT FROM PUBLISHER]

Due to the development of integrated electronic appliances, independently controlled multiple-output dc–dc converter prototypes have started to emerge in various forms, offering advantages of more compact size and cheaper cost. However, the existing converter topologies are capable of regulating outputs only with the help of auxiliary converter circuits and additional switches. The converter also fails to control all of the outputs independently when the converter has a greater number of output stages than that of the peripheral switching/linear regulators. Therefore, in this paper, a novel dc–dc converter prototype is proposed that can be utilized to construct independently controlled multiple-output converter topology with a single PWM signal driving the primary inverter switches. Feasibility, design challenges, and practical considerations are discussed in this paper with a design example of an independently controlled four-output, 356-W resonant converter system. [ABSTRACT FROM AUTHOR]