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This paper presents a generalized pulse width modulation (PWM)-based control algorithm for multiphase neutral-point-clamped (NPC) converters. The proposed algorithm provides a zero sequence to be added to the reference voltages that contributes to improve the performance of the converter by: 1) Regulating the neutral-point (NP) current to eliminate/attenuate the low-frequency NP voltage ripples; 2) reducing the switching losses of the power semiconductors; and 3) maximizing the range of modulation indices for linear operation mode. The control method is formulated following a carrier-based PWM approach. Hence, dealing with complex space-vector diagrams to solve the modulation problem for multiphase converters is avoided. The recursive approach means that it can be easily extended to n-phase converters without increasing the complexity and computational burden, making it especially attractive for digital implementation. The proposed method allows regulating the NP voltage without the need for external controllers; therefore, no parameter tuning is required. The algorithm has been tested in a four-leg NPC converter prototype performing as a three- and four-phase system and operating with balanced and unbalanced loads. [ABSTRACT FROM AUTHOR]

In this paper, a single-switch coupled-inductor-based two-channel light-emitting diode (LED) driver with a passive regenerative snubber is presented. In the proposed LED driver, the energy-transferring capacitor is not only used to step up the voltage gain but also to achieve the current balance among LED strings. Moreover, a passive regenerative snubber is added not only to recycle the leakage inductance energy but also to improve the voltage gain. As compared with the prior work, only one switch is required. Thus, the configuration of the proposed LED driver is simpler. Since the proposed LED driver has a higher voltage gain than the prior work, the turns ratio of the proposed LED driver can be lower. Thus, the magnetic core size can be reduced. In addition, both LED drivers have the same component count. Finally, the operating principle, analysis, and experimental results are provided to verify the effectiveness of the proposed LED driver. [ABSTRACT FROM AUTHOR]

To regulate an output ac voltage in inverter systems having wide input dc voltage variation, a buck–boost power conditioning system is preferred. This paper proposes a novel high-efficiency quasi single-stage single-phase buck–boost inverter. The proposed inverter can solve current shoot-through problem and eliminate PWM dead time, which leads to greatly enhanced system reliability. It allows bidirectional power flow and can use MOSFET as switching device without body diode conducting. The reverse recovery issues and related loss of the MOSFET body diode can be eliminated. The use of MOSFET contributes to the reduction of switching and conduction losses. Also, the proposed inverter can be operated with simple pulse width modulation (PWM) control and can be designed at higher switching frequency to reduce the volume of passive components. The detailed experimental results are provided to show the advantages of the proposed inverter. Efficiency measurement shows that using simple PWM control the proposed inverter can obtain peak efficiency of 97.8% for 1.1-kW output power at 30-kHz switching frequency. [ABSTRACT FROM AUTHOR]

A resonant single-stage single-switch four-output LED driver with high power factor and passive current balancing is proposed. By controlling one output current, the other output currents of four-output LED driver can be controlled via passive current balancing, which makes its control simple. When magnetizing inductor current operates in critical conduction mode, unity power factor is achieved. The proposed LED driver uses only one active switch and one magnetic component, thus it benefits from low cost, small volume, and light weight. Moreover, high-efficiency performance is achieved due to single-stage power conversion and soft-switching characteristics. The characteristics of the proposed LED driver are studied in this paper and experimental results of two 110-W four-output isolated LED drivers are provided to verify the studied results. [ABSTRACT FROM AUTHOR]

This paper presents a new advanced bus-clamped space vector pulsewidth modulation (SVPWM) technique to reduce line current harmonic distortion as well as switching loss. The proposed sequence introduces multiple division of active vector time (MDAVT) in a subcycle. An analysis of optimal subdivision of active vector dwell time is presented. Existing bus-clamping pulsewidth modulation techniques use double-switching clamping sequences, which use only one zero state and apply an active vector twice in a subcycle. The proposed MDAVT-based SVPWM technique presents a hybrid SVPWM technique. The additional switching is added when the fundamental voltage crosses zero. The switching patterns for the other two phases are not changed. The harmonic performance and switching loss characteristics of the proposed hybrid SVPWM techniques over the existing SVPWM is verified with experimental results on a 415-V, 2.2-kW induction motor drive. [ABSTRACT FROM AUTHOR]

A series of switched-capacitor (SC) cell balancing circuits is proposed for rechargeable energy storage devices like battery and supercapacitor strings in this paper. Taking a basic SC-based cell balancing unit as an equivalent resistor, the behavioral models of the proposed cell balancing circuits are developed to evaluate their balancing performance. Comparing with existing SC-based cell balancing circuits, the main advantage of the proposed circuits is that their balancing speed is independent of both of the number of battery cells and initial mismatch distribution of cell voltages. In order to improve the operation performance of SC-based cell balancing circuits in the respect of minimizing the equivalent resistance, optimizing methodologies of circuit parameters are introduced by referring the concepts of slow switching limit and fast switching limit as well as inductive switching limit of SC power converters. Simulation and experimental results are provided to verify the feasibility of the proposed cell balancing circuits. [ABSTRACT FROM AUTHOR]

The performance of a novel three-phase four-leg fault-tolerant T-type inverter topology is introduced in this paper. This inverter topology provides a fault-tolerant solution to any open-circuit and certain short-circuit switching faults in the power devices. During any of the fault-tolerant operation modes for these device faults, there is no derating required in the inverter output voltage or output power. In addition, overload capability is increased in this new T-type inverter compared to that in the conventional three-level T-type inverter. Such increase in inverter overload capability is due to the utilization of the redundant leg for overload current sharing with other main phase legs under healthy condition. Moreover, if the redundant phase leg is composed of silicon carbide metal-oxide-semiconductor field-effect transistors, quasi-zero-voltage switching, and zero-current switching of the silicon insulated-gate bipolar transistors (IGBTs) in the conventional main phase legs can be achieved at certain switching states, which can significantly relieve the thermal stress on the outer IGBTs and improve the whole inverter efficiency. Simulation and experimental results are given to verify the efficacy and merits of this high-performance fault-tolerant T-type inverter topology. [ABSTRACT FROM PUBLISHER]

On-line condition monitoring is of paramount importance for multilevel power converters used in safety-critical applications. A novel on-line nonintrusive diagnostic method for detecting open-circuit switch faults in silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs)-based T-type multilevel converters is introduced in this paper. The principle of this method is based on monitoring the abnormal variations of the dc-bus neutral-point current in combination with the existing information on instantaneous switching states and phase currents. Advantages of this method include faster detection speed and simpler implementation compared to other existing diagnostic methods in the literature. Moreover, this diagnostic method is immune to the disturbances of inverter's dc-bus voltage unbalance and load unbalance. In this method, only one additional current sensor is required for measuring the dc-bus neutral-point current; therefore, the implementation cost is low. Simulation and experimental results based on a lab-scale 20 kVA adjustable speed drive with a three-level SiC T-type inverter validate the effectiveness and robustness of this novel diagnostic method. [ABSTRACT FROM PUBLISHER]

In the integrated reconfigurable converter (IRC) topology for high-voltage series-connected battery module systems, the converter can be reconfigured into a range of operating modes: “feeding a load” mode, “battery modules balancing” mode, “regenerative” mode, “charging” mode, and “backup” mode. In most battery applications, a battery-balancing system operates while another converter is used as a controllable power interface between the battery system and a load. However, during the conventional IRC operation, the “battery modules balancing” and “feeding a load” modes cannot be operated simultaneously. In this paper, a new balancing scheme is proposed that allows balancing the battery modules while they are powering the load. The proposed balancing strategy is able to distribute different amount of load between the battery modules based on their state of charge (SOC). When the load is disconnected, the battery modules can be still balanced using the conventional “battery modules balancing” mode. A scaled down prototype of the IRC is implemented with three series-connected battery modules. Experimental results are provided to verify the viability of the proposed balancing method. [ABSTRACT FROM AUTHOR]

A self-biased CMOS analog mixer for ultra-wideband (UWB) applications is presented in this paper. The proposed mixer is complementary and self-biased, and has lower power consumption, superior isolation, and larger bandwidth. The proposed low-power, down conversion mixer is designed and fabricated in UMC 0.18\mu \textm CMOS technology. The measurement results show that it can operate at UWB frequencies that range from 1 to 6 GHz. The proposed mixer provides a maximum conversion gain of 13 dB, −4.5 dBm of third-order input intercept point, and a minimum double sideband noise figure of 12 dB. The maximum values of the measured local oscillator LO-to-RF, RF-to-IF, and LO-to-IF isolations are 50, 45, and 52 dB, respectively. [ABSTRACT FROM PUBLISHER]

Power-factor-correction (PFC) preregulator commonly suffers from slow dynamic response due to the need to operate with small closed-loop bandwidth for realizing low total harmonic distortion of input current. Ripple cancellation is one of the widely adopted strategies to achieve high power factor and fast dynamic response simultaneously. The main idea is to eliminate the double-line frequency component in the sampled output voltage by means of subtracting a replica of the output voltage ripple from the sampled output voltage. In this paper, a systematic derivation and analysis of the main figures of merit of PFC preregulator incorporating ripple cancellation is presented. Based on the equations obtained, three variants of a family of ripple cancellation methods based on switched-resistor circuits are proposed. The performances of these methods are experimentally investigated and compared by implementing them in a 200-W average-current-mode-controlled boost PFC preregulator. By comparing the measured figures of merit, it is shown that near-perfect ripple cancellation is achievable when the amplitude and phase angle of the sampled output voltage ripple are estimated independently, whereas a more cost-effective solution is provided by another approach that tracks the ripple amplitude only at the expense of decreased power factor and increased total harmonic distortion. [ABSTRACT FROM AUTHOR]

Cycling induced by automatic control of functional electrical stimulation provides a means of therapeutic exercise and functional restoration for people affected by paralysis. During cycling induced by functional electrical stimulation, various muscle groups are stimulated according to the cycle crank angle; however, because of kinematic constraints on the cycle-rider system, stimulation is typically only applied in a subsection of the crank cycle. Therefore, these systems can be considered as switched control systems with autonomous, state-dependent switching with potentially unstable modes. Previous studies have included an electric motor in the system to provide additional control authority, but no studies have considered the effects of switched control in the stability analysis of the motorized functional electrical stimulation cycling system. In this paper, a model of the motorized cycle-rider system with functional electrical stimulation is developed that includes the effects of a switched control input. A novel switching strategy for the electric motor is designed to only provide assistance in the regions of the crank cycle where the kinematic effectiveness of the rider's muscles is low. A switched sliding-mode controller is designed, and global, exponentially stable tracking of a desired crank trajectory is guaranteed via Lyapunov methods for switched systems, despite parametric uncertainty in the nonlinear model and unknown, time-varying disturbances. Experimental results from five able-bodied, passive riders are presented to validate the control design, and the developed control system achieves an average cadence tracking error of 0.00\pm 2.91 revolutions per minute for a desired trajectory of 50 revolutions per minute. [ABSTRACT FROM AUTHOR]

In this paper, measurement results of the arc erosion limitation in low voltage (LV) switches are presented. The reduction of the arc erosion in the analyzed electromechanical switches was achieved through an application of the hybrid switching in the tested alternative current circuit during interruption of the inductive current. The presented method is based on a commutation of the current during its interruption into a semiconductor branch that is connected in parallel to the operated switch. Thus, this approach is able to limit the electric arc energy efficiently, and as a consequence the arc erosion of the electrical contacts is also significantly reduced. For this reason, the application of the hybrid switching has a positive influence on a lifespan and a reliability of the operated switch. In order to evaluate the influence of the hybrid switching application on an effectiveness of the limitation of the arc erosion in the analyzed LV switches, 50 000 current interruptions were conducted in the tested circuit by each of four analyzed switches. Researches were performed for two standalone switches during a standard current interruption, as well as, for two switches with applied the hybrid switching system. In order to compare the arc erosion of the contact surfaces in both considered cases, scanning electron microscope method coupled with energy dispersion spectroscopy was applied. Moreover, photos of the electric contact surfaces are presented. Additionally, frames registered by high-speed camera during current interruption are presented for both considered approaches. [ABSTRACT FROM PUBLISHER]

In this paper, a novel space-vector pulse-width modulation (PWM) scheme for reducing the common-mode voltage (CMV) in the three-phase five-level active neutral-point clamped (5L-ANPC) inverter is proposed, where only the 55 selected voltage vectors among the entire 125 that produce low values of the CMV are utilized. This PWM scheme can significantly reduce the CMV without the increase of switching losses and total harmonic distortion of the output voltages. With the 55 selected voltage vectors, the inverter can still operate up to the maximum modulation index. In addition, the capacitor voltages are controlled by redundant switches of the 5L-ANPC inverters. It has been shown that the peak value of the CMV is decreased to one-twelfth of the dc-link voltage from the simulation and experimental results. [ABSTRACT FROM PUBLISHER]

Vertical alignment liquid crystal (LC) cell driven by in-plane field with 3-D polymer network exhibited no pooling mura under an external mechanical pressure; however, the operating voltage of the device was increased, because the polymer network hinders field-induced reorientation of LC. In this paper, we adopted a modified cell structure in which a counter electrode on top substrate of the conventional mode is existed, to improve upon this drawback. The proposed device in which the polymer network is formed in bulk of vertically aligned LC layer shows a very fast response time of 2 ms (rise + decay), 57% reduction in operating voltage, and also keeps image quality although the cell is curved. [ABSTRACT FROM AUTHOR]

By the logical statements and linear inequalities, a new modeling method named bi-switching status modeling (BSM) method is presented to model the dc–dc converters in this paper. Compared with other modeling methods, such as the state-space averaging method and the mixed logical dynamical (MLD) method, first, the BSM method can describe continuous conduction mode and discontinuous conduction mode operations of the dc–dc converters as a unified bi-switching status model. Second, the BSM method is more precise than the state-space averaging method because there is no approximate assumption. Third, the constrains of the operating modes in the BSM method can be simplified as a consolidated inequality, which means that the model obtained by the BSM method is more concise than that obtained by the MLD method. Simulation and available experiments of a buck converter verify the effectiveness of the proposed BSM method. [ABSTRACT FROM PUBLISHER]

Model predictive control (MPC) schemes have become popular in the field of power electronics due to their intuitive formulation, flexibility, and ease of implementation. Typically, these schemes have been implemented with the prediction horizon limited to one time-step, and extension of the prediction horizon over multiple time-steps remains an ongoing area of research. In this paper, a variant of the MPC strategy is proposed wherein the slope of the output trajectories is used to emulate long prediction horizons. Each of the outputs, e.g., current, voltage, torque, or flux, is regulated within a set of symmetrical bounds. When switching is necessitated due to collision with a bound, the switching state that yields the set of output trajectories with the minimum slope, relative to the reference trajectory, is applied to the converter. The key benefit of this approach is its ability to achieve low switching frequencies with a minimal level of computational burden. The feasibility of the scheme, which can be adapted easily to different case studies, is demonstrated through simulations of both a medium-voltage induction machine drive and a grid-connected converter. Experimental results, which are presented for a 1.68 kVA prototype grid-connected neutral-point-clamped converter, further demonstrate the practical viability of the proposed strategy. [ABSTRACT FROM PUBLISHER]

Direct power control (DPC) has attracted wide attention due to its advantages of simple structure, quick response, strong robustness, and elimination of current regulation/pulse width modulation blocks. However, conventional table-based DPC cannot work well when the grid voltages are unbalanced. Some work has been done on DPC to mitigate the influence of grid unbalance by adding power compensations to the original power references. However, they are usually complicated due to the positive/negative-sequence extraction of grid voltage and/or currents. Furthermore, applying only one voltage vector during one control period leads to high steady-state power ripples. This paper proposes an improved DPC by using a new definition of instantaneous reactive power. As a result, the distortion in grid current is eliminated, and constant active power and new reactive power are obtained. Neither complicated calculation of power compensation nor positive/negative-sequence extraction of grid voltage/current is required. The corresponding switching table suitable to regulate both active power and the new reactive power is established. Furthermore, the concept of duty cycle control is introduced to further improve the steady-state performance. Both simulation and experimental results are presented to confirm the theoretical study and the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

Efficient current, voltage, and power sensing are critical blocks for power management, switching regulators, maximum power point tracking (MPPT) circuit, and motor control. This paper presents a standard CMOS and low-power current-to-digital converter (IDC) that senses the current flowing at high-voltage nodes. The proposed sensor uses a CMOS-switched capacitor circuit to sense a dc–dc converter output current and gives digital output without an analog-to-digital converter (ADC), or the need for high-voltage technologies. Compared to the resistor-based current-sensing methods that require current-to-voltage circuit, gain block, and an ADC converter, the proposed sensor is a low-power integrated circuit that achieves high resolution, lower complexity, and lower power consumption. The IDC circuit is fabricated on a 5 V, 0.7 μm, and three metal CMOS technology and occupied less than 10% area (1 mm2 area) compared to other sensors. It consumes 18 mW that is less than 40% power consumed by other sensors, and its current measurement error is below 0.4%. The proposed IDC circuit has been characterized as standalone and with a boost dc–dc regulator and MPPT for photovoltaic systems. [ABSTRACT FROM AUTHOR]

Recently, a growing number of dc systems exist based on the development of electrical energy consumption. For low-voltage dc grids, switching devices are needed that have to meet technically sophisticated requirements. These devices have to handle fault currents of several hundred amperes and system voltages up to 1000 V. A typical dc circuit breaker has to provide low on-state losses, light weight, and small volume. On the way toward fulfilling these requirements, hybrid circuit breakers can represent the optimal solution. A hybrid dc circuit breaker combines the advantages of mechanical contacts and semiconductors. In this paper, such a device has been designed and constructed using a commercial switch and electronic components in the laboratory. The breaking performance of this experimental prototype has been investigated, and thus the interruption of the nominal and failure currents in the case of different time constants can be identified. The investigated hybrid switching device has been optimized in order to maximize the switching capacity and the protection of the semiconductors. [ABSTRACT FROM PUBLISHER]

This paper is concerned with sampled-data control of switched linear systems with average dwell time switching under variable sampling. Since the subsystem switching could occur during the sampling intervals while the associated controller does not switch, the asynchronous switching phenomenon arises. A new class of functionals consisting of multiple Lyapunov functions and looped functionals is developed to present sufficient conditions on the exponential stabilization for such systems with sampled-data state feedback. The obtained results are verified by an F-18 aircraft. [ABSTRACT FROM AUTHOR]

This paper presents a new multicell topology based on flying capacitor (FC) structure suitable for multilevel converters. The proposed topology employs the concept of phase-shifted carrier pulse width modulation (PWM) with modified modulating signals to generate appropriate PWM signals. The modulation strategy along with all possible switching states are explained. The implementation of the proposed PWM technique is shown by the help of illustrating waveforms. To show the advantages of the proposed structure, different performance criteria are compared with other FC multicell (FCM) structures. Simulation results are used to further evaluate the potential merits of the proposed topology. It is shown that the proposed structure is superior to other FCM-based structures from different standpoints. Specifically, it reduces the number of high-frequency switches, the number of FCs, and at the same time improves the quality of output voltage. A laboratory-type experimental setup is used to validate the modulation strategy and other theoretical findings. [ABSTRACT FROM AUTHOR]

This paper proposes a current control method for discontinuous current mode (DCM) in order to achieve the same control performance as continuous current mode (CCM) in a boost converter. By utilizing the duty ratio at the previous calculation period to compensate for a DCM nonlinearity, the controller, which is designed for CCM, can also be used in DCM. In the frequency analysis, the cutoff frequency of the proposed DCM current control agrees exactly to the design value, which is 2 kHz, whereas the cutoff frequency of the conventional DCM current control results in high error of 47.5%. In the current step response experiment with a 360-W prototype and the switching frequency of 20 kHz, the experimental DCM current response almost agrees with the conventional CCM current response, which are 380-μs rise time for both CCM and DCM, 9% and 8% overshoot for CCM and DCM, respectively. Furthermore, the computation time of the proposed DCM current control is shorter 35% than the conventional DCM current control. [ABSTRACT FROM AUTHOR]

This paper studies a distributed consensus algorithm for economic dispatch in a smart grid, which aims at minimizing the total generation cost. The proposed algorithm only needs each generator in the network be aware of its local cost parameters and its neighbors’ virtual incremental cost variables. The proposed algorithm is “anytime.” It does not break the supply–demand balance even in the transient process. It overcomes the defect that the trajectories of traditional consensus based algorithms are not feasible solutions before convergence. The proposed algorithm is also “anywhere.” It is applicable for the jointly connected switching undirected topology. It can gradually drive any connected region of a power system to approach its own optimal state. Simulation studies on several cases demonstrate its effectiveness. [ABSTRACT FROM AUTHOR]

This paper presents a nine-level inverter topology for an open-end induction motor drive requiring only eight switches per phase, using two three-level inverters with two isolated dc links in a 3:1 ratio. A space-vector-based formulation is used to determine pole voltages such that both inverters supply power to the load over the full modulation range, eliminating the possibility of dc bus overcharging. Proper selection of switching states ensures that all floating capacitor voltages are kept tightly balanced. A digital state machine is used to select sequences of switching states in order to eliminate deadtime-induced pole voltage transients, further improving the output-voltage quality. A level-shifted carrier-based pulse width modulation scheme is used. The steady-state and transient performance of this topology were verified and the experimental results are included. [ABSTRACT FROM AUTHOR]

A recently reported modeling methods for a switched capacitor converter either assume output as “firm” voltage or a resistor to facilitate calculation. When the size of output filter capacitor is moderate, accompanied by noticeable output ripple, previous modeling results may not provide accurate prediction and design guidelines. In this paper, a new modeling technique taking into account the output capacitor effect is proposed for simple dual-phase switched capacitor converters without complex coupling loops. The proposed model employs transient calculation, takes charge redistribution phase into account, and includes the duty cycle, switching frequency as well as output capacitor simultaneously in the final output impedance formula, which enhances accuracy of the model. It is suitable for interleaved and noninterleaved switched capacitor converters. The simulation and experimental results for the unity gain SC converter are provided to verify the proposed theory. [ABSTRACT FROM PUBLISHER]

Fixing the switching frequency is a key issue in sliding mode control implementations. This paper presents a hysteresis band controller capable of setting a constant value for the steady-state switching frequency of a sliding mode controller in regulation and tracking tasks. The proposed architecture relies on a piecewise linear modeling of the switching function behavior within the hysteresis band, and consists of a discrete-time integral-type controller that modifies the amplitude of the hysteresis band of the comparator in accordance with the error between the desired and the actually measured switching period. For tracking purposes, an additional feedforward action is introduced to compensate the time variation of the switching function derivatives at either sides of the switching hyperplane in the steady state. Stability proofs are provided, and a design criterion for the control parameters to guarantee closed-loop stability is subsequently derived. Numerical simulations and experimental results validate the proposal. [ABSTRACT FROM PUBLISHER]

Diode-assisted buck–boost voltage-source inverter achieves high voltage gain by introducing a switch-capacitor based high step-up dc–dc circuit between the dc source and inverter bridge. As for the unique structure, various pulse width modulation (PWM) strategies are developed with regard to the chopped intermediate dc-link voltage. In order to maximize voltage gain and increase efficiency, this paper proposes a novel PWM strategy. It regulates the average value of intermediate dc-link voltage in one switching time period ( Ts) the same as the instantaneous maximum value of three-phase line voltage by controlling the front boost circuit. Then, the equivalent switching frequency of power devices in the inverter bridge can be reduced to 1/3fs (fs = 1/Ts). The operating principle and closed-loop controller design are analyzed and verified by simulations and experiments. Compared with existing PWM strategies, the new control strategy demonstrates less power device requirement and higher efficiency in high voltage gain applications. It is a more competitive topology for wide range dc/ac voltage regulation in renewable energy applications. Furthermore, with new control strategy, the dc-side inductor current and capacitor voltage contains six-time line-frequency ripples. To overcome the undesired influence of low frequency ripples, it is also suitable for 400–800 Hz medium frequency aircraft and vessel power supply system. [ABSTRACT FROM PUBLISHER]

For the efficiency and simplicity of electric systems, the dc power electronic systems are widely used in a variety of applications such as electric vehicles, ships, and aircraft and in homes. In these systems, there could be a number of dynamic interactions and frequency coupling between network and loads and other converters. Hence, time-domain simulations are usually required to consider such a complex system behavior. However, simulations in the time domain may increase the calculation time and the utilization of computer memory. Furthermore, frequency coupling driven by multiple converters with different switching frequencies or harmonics from ac–dc converters makes that harmonics and frequency coupling are both problems of ac system and challenges of dc system. This paper presents the modeling and simulation methods of a large dc system by using the harmonic state space (HSS) modeling. Through this method, the required computation time and CPU memory can be reduced, where this faster simulation can be an advantage of a large network simulation. Besides, the achieved results show the same results as that of the nonlinear time-domain simulation. Furthermore, the HSS modeling can describe how the frequency components are coupled with each other through the different switching frequency of each converter. [ABSTRACT FROM PUBLISHER]

Many analytical methods of establishing accurate models of the switched-capacitor (SC) converters have been developed. These methods are applicable to simple low-order SC converters and can permit only a general efficiency calculation of SC converters. They do not provide analytical solutions that describe how individual electrical component in the circuit practically affects the SC converter at different frequencies. Such an analysis is important for the optimal design and realization of a complex (high-order) SC converter. This is particularly true for those SC converters which have more than two operating states. For complex SC converters, a constituent capacitor may have a profound effect on the converter's efficiency and is dependent on the configuration of the switches and the arrangement of the energy flow paths. In this paper, the relationship of the value of capacitors and the efficiency of complex SC converters is derived and investigated using an energy-flow-path analysis. Optimal design of SC converters can be achieved through a systematic component value selection by: 1) increasing the proportion of energy flow through the most efficient paths; and 2) increasing the efficiency of the paths that have a higher energy flow. The design of complex SC converters in terms of optimizing their power efficiency is discussed using an exponential SC converter as an illustration. The results of both calculation and experimental measurement show that the approach is effective. [ABSTRACT FROM AUTHOR]

This paper analyzes write errors in spin-torque switching due to thermal fluctuations in a system with perpendicular magnetic anisotropy. Prior analytical and numerical methods are summarized; a physics-based general 2-D Fokker–Planck equation (FPE) is solved numerically. Due to its computational efficiency and broad applicability to all switching regimes and system symmetries, the 2-D FPE has been used to study the relation between write error slope and material parameters as well as some emerging switching schemes. [ABSTRACT FROM PUBLISHER]

Input-series output-series (ISOS) modular dc–dc converters are suitable for applications involving high input and output voltages. Input voltage sharing (IVS) and output voltage sharing (OVS) of the constituent modules must be guaranteed for an ISOS system. A duty cycle-based model predictive control (DC-MPC) scheme is proposed in this paper to achieve IVS and OVS for an ISOS system. The employed switching frequency in the DC-MPC scheme is fixed; duty cycles are optimized and then determined by minimizing a cost function, which is derived from an ISOS system aimed at achieving IVS and OVS. IVS and OVS can, therefore, be obtained by employing the optimized duty cycle within each sampling period. In addition, challenges and disadvantages of directly using traditional MPC to achieve IVS and OVS is briefly discussed, while the proposed DC-MPC can effectively avoid them. Compared with the existing proportional integral-based schemes in the literature, the proposed DC-MPC is better for IVS and OVS because it is a very simple and intuitive approach with lower cost and higher overall dynamic performance. Simulation and experiments are conducted to verify that the proposed DC-MPC scheme works well during both steady and transient states. [ABSTRACT FROM AUTHOR]

This paper introduces a MultiTrack power conversion architecture that represents a new way of combining switched-capacitor circuits and magnetics. The MultiTrack architecture takes advantages of the distributed power processing concept and a hybrid switched-capacitor/magnetics circuit structure. It reduces the voltage ratings on devices, reduces the voltage regulation stress of the system, improves the component utilization, and reduces the sizes of passive components. This architecture is suitable to dc–dc and grid-interface applications that require both isolation and wide voltage conversion range. An 18–80 V input, 5 V, 15 A output, 800 kHz, 0.93 in $^2$ (1/16 brick equivalent) isolated dc–dc converter has been built and tested to verify the effectiveness of this architecture. By employing the MultiTrack architecture, utilizing GaN switches, and operating at higher frequencies, the prototype converter achieves a power density of 457.3 W/in$^3$ and a peak efficiency of 91.3%. Its power density is 3$\times$ higher than the state-of-the-art commercial converters with comparable efficiency across the wide operation range. [ABSTRACT FROM AUTHOR]

This paper proposes a new method of generating higher number of levels in the voltage waveform by stacking multilevel converters with lower voltage space vector structures. An important feature of this stacked structure is the use of low voltage devices while attaining higher number of levels. This will find extensive applications in electric vehicles since direct battery drive is possible. The voltages of all the capacitors in the structure can be controlled within a switching cycle using the switching state redundancies (pole voltage redundancies). This helps in reducing the capacitor size. Also, the capacitor voltages can be balanced irrespective of modulation index and load power factor. To verify the concept experimentally, a nine-level inverter is developed by stacking two five-level inverters and an induction motor is run using V/f control scheme. Both steady state and transient results are presented. [ABSTRACT FROM AUTHOR]

DC distribution power systems are vulnerable to instability because of the destabilizing effect of converter-controlled constant power loads (CPLs) and input filters. Standard stability analysis tools based on averaging linearization techniques can be used only when the switching frequency of the converter is significantly higher than the cutoff frequency of the filter. However, dc distribution systems with a reduced size filter, and consequently a high cutoff frequency, are common in transportation applications. Conventional methods fail to detect instabilities in the system because they do not take into account the switching effect. To overcome this drawback, this paper proposes a discrete-time method to analyze the stability of dc distribution systems. This model is applied here to a dc power system with a CPL. The switching effects and the nonlinearities of the system model are taken into account with a simple discretization approach. The proposed method is able to predict the dynamic properties of the system, such as slow-scale and fast-scale instabilities. An active stabilizer is also included in the system model in order to extend the stability margin of the system. Finally, these observations are validated experimentally on a laboratory test bench. [ABSTRACT FROM AUTHOR]

This paper studies the implementation of Boolean functions by lattices of four-terminal switches. Each switch is controlled by a Boolean literal. If the literal takes the value 1, the corresponding switch is connected to its four neighbors; else it is not connected. A Boolean function is implemented in terms of connectivity across the lattice: it evaluates to 1 iff there exists a connected path between two opposing edges of the lattice. The paper addresses the following synthesis problem: how should one assign literals to switches in a lattice in order to implement a given target Boolean function? The goal is to minimize the lattice size, measured in terms of the number of switches. An efficient algorithm for this task is presented—one that does not exhaustively enumerate paths but rather exploits the concept of Boolean function duality. The algorithm produces lattices with a size that grows linearly with the number of products of the target Boolean function in ISOP form. It runs in time that grows polynomially. Synthesis trials are performed on standard benchmark circuits. The synthesis results are compared to a lower-bound calculation on the lattice size. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel high step-up nonisolated single switch dc–dc converter suitable for regulating dc bus in various microsources especially for photovoltaic (PV) sources. Quadratic boost and switched-capacitor technique are used as primary and secondary circuits, respectively. A coupled inductor is applied to make a connection between them, so a high dc voltage gain is achieved. High efficiency is yield where voltage stress on active switch is alleviated by clamped capacitor; consequently, smaller \rmR\rm{DS(ON)} for power switch is required. On the other hand, input current of the proposed converter is continued, hence stress on the input source is reduced. The operating principles and steady-state analyses are discussed in detail for both continuous and discontinuous conduction modes. Also, the boundary condition is computed. To verify the performance of the proposed converter and theoretical calculations, a 250-W prototype converter is implemented with an input voltage of 24 V and an output voltage of 400 V designed especially for PV sources in continuous conduction mode operation. Finally, simulation results are confirmed by experimental results; maximum efficiency is occurred at 150 W and full-load efficiency is 92.96%. [ABSTRACT FROM AUTHOR]

This paper presents the design and implementation of a Class EF$_2$ inverter and Class EF$_2$ rectifier for two -W wireless power transfer (WPT) systems, one operating at 6.78 MHz and the other at 27.12 MHz. It will be shown that the Class EF$_2$ circuits can be designed to have beneficial features for WPT applications such as reduced second-harmonic component and lower total harmonic distortion, higher power-output capability, reduction in magnetic core requirements and operation at higher frequencies in rectification compared to other circuit topologies. A model will first be presented to analyze the circuits and to derive values of its components to achieve optimum switching operation. Additional analysis regarding harmonic content, magnetic core requirements and open-circuit protection will also be performed. The design and implementation process of the two Class-EF $_2$-based WPT systems will be discussed and compared to an equivalent Class-E-based WPT system. Experimental results will be provided to confirm validity of the analysis. A dc–dc efficiency of 75% was achieved with Class-EF$_2$-based systems. [ABSTRACT FROM AUTHOR]

This paper presents simplified techniques for the space vector modulation (SVM) of any n-level multilevel inverter. Three techniques have been presented to simplify the identification of the nearest three vectors to the reference vector. The first two techniques are based on resolving the multilevel inverter space vector diagram into appropriate two-level hexagons. This results in simplification of the multilevel SVM problem into a two-level SVM problem. The third technique is an algorithm-based technique which makes use of a 60°-spaced gh coordinate system to perform the SVM of a multilevel inverter. Switching sequence design for all the three techniques is presented with the aim of minimization of the device switching frequency. Simulation and experimental results have been provided to verify the feasibility of the proposed techniques. Simulation results are provided for up to 21-level cascaded H-bridge (CHB) inverters, while the experimental verification is done on a five-level laboratory prototype. Although only the CHB inverter is considered in this study, the proposed techniques are perfectly general and can be applied to all types of multilevel inverters, and are extendable to any number of levels. [ABSTRACT FROM AUTHOR]

In this paper, indium-tin-oxide (ITO) was used to act as both insulator and top electrode in resistive random access memory (RRAM) on identical bottom substrates. This is achieved by cosputtering an ITO target with nitride (N2) or oxygen (O2) gas as the insulator; then capping by an ITO electrode, such that both the rectifier and RRAM characteristics can be achieved before and after a forming process, respectively. In contrast, using pure ITO as an insulator does not exhibit RRAM behavior. To verify the rectifier and RRAM characteristics, material analyses and electrical measurements at various temperatures were conducted. Reliability tests including retention and endurance were also applied to verify the resistance switching stability. Finally, the rectifier and RRAM conduction models were proposed to examine the resistance switching behaviors. By applying the ITO material as both electrode and insulator, the resistance switching characteristic with high reliability is thus obtained. [ABSTRACT FROM AUTHOR]

In this paper, an efficient free-positioning wireless power transfer (WPT) system for charging multiple devices is proposed. For the system, a planar transmitting (Tx) coil that consists of a spiral coil and concentric multiple parallel loops and switchable impedance matching networks (IMNs) at a transmitter are developed. Using the Tx coil, mutual inductance between the Tx coil and the receiving (Rx) spiral coils is made uniform in the effective charging area. The parallel loops are placed in the interior of the Tx coil, and the magnetic field is enhanced and controlled by adjusting the space in each parallel loop. For optimal design of the coil, an analysis method using an equivalent circuit is explained in detail. It is found that the current of one loop of a parallel loop is more than the input current and negative current flows on the other loop, while the total current of each parallel loop is constant. An array of parallel capacitors with a switch as the switchable IMN is used for the maximum power transfer efficiency corresponding to the number of devices. The reflection coefficients of the fabricated WPT system are under −10 dB at 6.78 MHz, regardless of the number of devices and positions. The WPT system has the maximum power transfer efficiencies of 93% for two devices and simultaneously transfers uniform power to up to four devices with high efficiency. [ABSTRACT FROM PUBLISHER]

This paper presents a distributed control strategy for state-of-charge balancing between the battery modules of a reconfigurable battery energy storage system. The autonomous modules share state-of-charge information with their neighbors over a sparse communication network and cooperate to reach a balanced state of charge. The proposed control strategy provides advantages in terms of reduced communication requirements and increased modularity, over a centralized battery management system. Steady-state analysis provides bounds on the mean error and mean-squared error of the distributed average state-of-charge estimates used for autonomous balancing control. The proposed control strategy enforces module topology constraints specific to the particular reconfigurable battery implementation. The state-of-charge balancing mode current controller prevents current spikes during module topology transitions. Experimental results demonstrate the performance of the proposed control strategy for a reconfigurable energy storage system made up of four 6-V, 7-Ah lead-acid battery modules. [ABSTRACT FROM PUBLISHER]

The series configuration of fast semiconductor switches seems to be the key component in the high-voltage and fast rising time pulse generation. In this approach, two important issues must be considered. The first is to provide a safe operating condition for the switches in transient intervals. The second is to design a gate drive system with the capability of driving a large number of discrete devices simultaneously. The aim of this paper is to obviate these two requirements. First, different factors affecting the unbalanced voltage sharing between the series switches are discussed. In this investigation, the switch-to-ground parasitic capacitance effect has been recognized as the major effect on the unbalanced voltage sharing in the transient interval. Two schemes for abating this effect are proposed. To solve the unbalanced voltage distribution, the structure with a snubber circuit in the clamp mode operation is suggested. This scheme can be used for any number of switches without destructively affecting their behavior. In addition, the output pulse with a fast rising time could be obtained by the proposed gate drive system. In order to evaluate the operation of the proposed structure, a stacked switch with the voltage capability of 36 kV is tested experimentally. The characteristics of the obtained pulse are the fast rising time (69.5 ns) with the dV/dt of 460 kv/ \mu \texts and the wide range of the pulsewidth adjusting to 0.5–15 \mu \texts . In addition, the voltage variance of the switches level in the series structure is about 10%. [ABSTRACT FROM AUTHOR]

An improved switching scheme for static VAr compensators (SVCs) that have fixed capacitor-thyristor-controlled reactors (FC-TCRs) for load balancing and power factor improvement has been addressed in this paper. The proposed control scheme can eliminate negative-sequence current caused by unbalanced load while improving the source power factor simultaneously. Thus total current supplied by the source can be minimized along with improvement of the load voltage profile. As the switching of TCR can introduce additional harmonics in the line, an optimized switching function is adopted in the proposed scheme for minimum injected harmonics without using an external filter. The gravitational search algorithm has been used for obtaining the optimized switching angle. The proposed scheme has been verified through proper simulations backed by suitable experimental results on a practical system. [ABSTRACT FROM PUBLISHER]

This paper presents a design methodology to drastically improve the hot-switching reliability of contact-type radio frequency microelectromechanical system (RF-MEMS) switches. In the proposed design, sacrificial contacts are placed in parallel with low-resistance contacts to significantly reduce the electric field across the latter. The lower field strength drastically reduces the contact degradation associated with field-induced material transfer. Theoretical and numerical modeling shows that the proposed protection scheme introduces minimal, if any, impact on the RF performance of the switch. To realize the protection scheme, we introduce a novel mechanical design that allows the correct protection actuation sequence to be realized using a single actuator and bias electrode. As a demonstration, several 0–40-GHz RF-MEMS switches are fabricated using a robust copper sacrificial layer technique. Compared with unprotected switches, the protected switch design exhibits over 100 times improvement in the hot-switching lifetime. In particular, we demonstrate a 100–150 million cycle lifetime at 1-W hot switching and 50 million cycles at 2-W hot switching before catastrophic failure, measured in an open-air lab environment. Further optimization of the structural design and contact materials is likely to further increase the hot-switching lifetime. [ABSTRACT FROM PUBLISHER]

This paper presents an analytical and experimental comparison of a two-phase buck converter and a two-phase, series capacitor buck converter. The limitations of a conventional buck converter in high-current (10 A or more), and high-frequency (HF, 3–30 MHz) point-of-load voltage regulators with large voltage conversion ratios (10-to-1) are highlighted. The series capacitor buck converter exhibits desirable characteristics at HF, including lower switching loss, less inductor current ripple, automatic phase current balancing, duty ratio extension, and soft charging of the energy transfer capacitor. Analysis of the topologies indicates that switching loss and inductor core loss can dominate at HF. Results from side-by-side 12 V input, 1.2 V output hardware prototypes demonstrate that the series capacitor buck converter has up to 12 percentage points higher efficiency at 3 MHz and reduces power loss by up to 33% at full load (10 A). Some guidelines for inductor selection are provided, and a switch stress comparison reveals that the maximum converter switch stress is reduced by 30%. [ABSTRACT FROM AUTHOR]

A bidirectional converter (BDC) is essential in applications where energy storage devices are involved. Such applications include transportation, battery less uninterruptible power system, flywheel energy storage systems, etc. Bidirectional power flow through buck and boost modes of operation along with high power density and efficiency is important requirement of such systems. This paper presents a new BDC topology using a combination of fast turn-off SCR and insulated-gate bipolar transistor with a novel control logic implementation to achieve zero switching losses through zero voltage transition and zero current transition techniques. The proposed scheme ensures zero switching power loss (ZSPL) for both buck and boost modes of operation of the BDC. The scheme is simple and achieves ZSPL during both turn-on and turn-off of the devices resulting in improved efficiency and reduced electromagnetic interference problems. The basic principle of operation, analysis, and design procedure are presented for both voltage buck and boost modes of operation of the proposed BDC topology. A design example is presented. Limitations of the system are highlighted. Experimental and simulation results obtained on a 4 kW, 340 V input prototype with a switching frequency of 15.4 kHz are presented to verify the design. [ABSTRACT FROM PUBLISHER]

This paper presents the analysis of a novel high-pass filter/low-pass filter (HPF/LPF) switching concept. Since an HPF/LPF switching concept has a periodic structure, its equivalent circuit is almost the same as an LPF for the ON-state and is the same as an HPF for the OFF-state. The broadband isolation characteristics with low insertion loss can be achieved by designing its cutoff frequency. A three-stage single pole single throw InGaAs pseudomorphic high electron mobility transistor monolithic microwave integrated circuit switch based on the HPF/LPF switching concept is successfully demonstrated with an insertion loss of less than 1.6 dB and isolation of more than 82 dB below 6 GHz, with a size of 1.1 mm $\times \,\, 1.0$ mm. The RF performances are in good agreement with the theoretical calculations. The measured input power of 1-dB insertion loss compression, P1dB, and the measured third-order intercept point, IIP3, are 19 and 27.7 dBm, respectively, at 1.95 GHz. The measured ON-time is 5.5 ns without cable delay. The measured rise time is as fast as 1.4 ns. [ABSTRACT FROM AUTHOR]

Linear controllers and small-signal modeling techniques have been used for over 40 years to control power electronic converters around the equilibrium operating point. Outside the quiescent area, the shortcomings of linear controllers are well known and include uncertain large-signal transient behavior and sluggish dynamic/recovery response. In particular, resonant converters have inherent large-signal behavior, making the transient performance of small-signal linear controllers poor. This paper develops a geometric controller based on large-signal modeling to achieve enhanced dynamic response of the series resonant converter (SRC). The proposed modeling strategy provides detailed insight into the behavior of the SRC and creates an analytical framework to successfully perform geometric control. A new geometric control law is mathematically derived using average circular trajectories producing accurate and fast dynamics during startup, sudden load or reference changes. In order to validate the theoretical analysis, experimental and simulation results of an SRC are presented and compared to those of a linear and a nonlinear controller. The dynamic response is, on average, over 100 times faster than that of the designed linear controller, while overshoot is virtually eliminated. [ABSTRACT FROM AUTHOR]

This paper presents a generalized algorithm to eliminate spikes of common-mode voltages (CMV) caused by dead-time effect for common-mode voltage reduction pulse width modulation (CMVRPWM). The characteristics of the CMV spikes for the popular CMVRPWM strategies (AZSPWM1, NSPWM, CRLO-CMVRPWM, and SLO-CMVRPWM) are studied and compared by analyzing the extreme switch pulse patterns. The proposed CMV spikes elimination method directly adjusts the injected zero-sequence voltages instead of the durations of the adopted voltage space vectors to avoid the overlaps of the adjacent dead time periods. The CMV spikes can be eliminated regardless of the output voltages in the dead time periods; thus, the signs of phase currents are not needed to detect and overcome the problem caused by the resolution of the current sensors when the phase currents approach to zero. In addition, an effective method by online selecting low or high active pulses for the three legs is proposed to ensure that at most one leg switches between adjacent carrier periods. The proposed method is generalized and effective for all the CMVRPWM with symmetrical switch pulse patterns and no simultaneous switching problem. The simulation and experimental results validate the effectiveness. [ABSTRACT FROM AUTHOR]