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In this work, AlN polarization-enhancement interlayer (AlN-PEL) is adopted to enhance two-dimensional hole gas (2DHG) density in a p-GaN/AlN-PEL(∼2 nm)/AlGaN(<6 nm)/GaN heterostructure, aiming at monolithic integration of p/n-channel field effect transistors (p-FETs) on GaN-on-Si substrate. Owing to the strong built-in polarization of the AlN-PEL, high density 2DHG over 2.3 × 1013 cm−2 with good immunity to thermal freeze out effect is realized. Assisted by a two-step gate trench etching process, enhancement-mode (E-mode) buried-channel GaN p-FETs with temperature independent ON-resistance RON, and ON/OFF current ratio ION/IOFF (>108), have been fabricated. The fabricated p-FETs also deliver thermally stable subthreshold swing as well as threshold voltage Vth, and smaller Vth shift than that of p-FETs without the AlN-PEL, which is primarily due to enhanced 2DHG confinement by the AlN-PEL. The proposed structure is an attractive platform for monolithic integration of GaN-based logic and power devices for cryogenic applications as low as 10 K. [ABSTRACT FROM AUTHOR]

A physical insight into the capture and emission behavior of interface/oxide states in a GaN-based metal-oxide-semiconductor (MOS) structure is of great importance to understanding the threshold voltage (VTH) instability in GaN power transistors. A time-dependent VTH shift in Ni/Al2O3/AlGaN/GaN MOS-HFETs (heterojunction field-effect transistors) and a distribution of Al2O3/III-nitride interface states (Dit) were successfully characterized by constant-capacitance deep level transient spectroscopy. It is found that in situ remote plasma pretreatments in plasma-enhanced atomic-layer-deposition could suppress Dit (EC-ET > 0.4 eV) down to below 1.3 × 1012 cm−2 eV−1. Under high applied gate bias (e.g., VG > 8 V), tunnel filling of oxide states in the Al2O3 dielectric comes into play, contributing to remarkable VTH instability in the MOS-HFETs. The tunnel distance between the 2D Electron Gas (2DEG) channel and oxide states ET,ox in the Al2O3 dielectric decreases from 3.75 to 0.82 nm as VG increases from 2 to 8 V. A further increase of VG to 11 V makes the Fermi level approach ET,ox (EC − ET ∼ 1.62 eV), which may enable direct filling. High electric field induced tunnel filling of gate oxide states could be an assignable cause for VTH instability in normally-OFF III-nitride MOS-HFETs. [ABSTRACT FROM AUTHOR]

A normally-off SiC-JFET/GaN-HEMT cascode device is recently proposed, featuring a cascode configuration that incorporates a high-voltage (HV, e.g., 1200 V) silicon-carbide (SiC) junction field effect transistor (JFET) delivering the HV blocking capability and a low-voltage (LV) enhanced-mode (E-mode) gallium-nitride (GaN) high electron mobility transistor (HEMT) providing the normally-off gate control. This all-wide-bandgap device exhibits superior thermal stability and high switching speed compared to its counterparts, e.g., the SiC/Si cascode device. In this article, we study short-circuit (SC) characteristics of a 1200-V/80-mΩ SiC/GaN cascode device by considering the interactions between the SiC and GaN devices. The single-event SC withstand time (SCWT) of the demonstrated SiC/GaN cascode device is tested to be ∼3 μs under a dc-bus voltage (Vdc) of 600 V when the turn-on gate voltage (VG-on) is set to 5 V. The SC failure occurs due to the formation of hot spots induced by thermal-runaway leakage currents inside the SiC JFET. The SCWT of the cascode device could be improved by applying a moderate VG-on (e.g., SCWT = ∼6.5 μs at VG-on = 3.5 V under v dc = 600 V) without affecting the on-state resistance (r on). However, it is identified that current oscillations tend to be triggered during the SC period when VG-on is too low (e.g., lower than 3 V). The oscillation behavior is attributed to the energy stored in the interconnection parts between the SiC and GaN devices. The harmful oscillations could be suppressed by applying higher VG-on, which drives the SiC JFET into low-transconductance mode by modulating the drain-to-source voltage (VDS-G) of the LV GaN HEMT. [ABSTRACT FROM AUTHOR]

${p}$ -channel GaN field-effect transistors (FETs) with a SiNx/GaON gate stack have been demonstrated with enhanced stability within a wide range of voltage bias and temperature. In this letter, the gate leakage characteristics and reliability of this unconventional staggered gate stack are investigated. At relatively low gate voltages, the gate current is suppressed owing to the buried-channel structure and the presence of GaON that presents an effective hole barrier. With more negative gate biases, the gate leakage was found to be dominated by the transport of holes that spillover from the ${p}$ -channel through the SiNx via Poole-Frenkel emission. Based on this gate leakage mechanism at large gate bias, $\sqrt {{\mathrm {E}}} $ model was used for gate lifetime prediction. The maximum applicable ON-state gate voltage of −7.3 V is obtained for a 10-year lifetime with a 1% gate failure rate. [ABSTRACT FROM AUTHOR]

Although the gallium nitride (GaN) high-electron-mobility transistor/silicon carbide (SiC) junction field-effect transistor (JFET) cascode device exhibits certain performance advantages over the SiC metal–oxide–semiconductor field-effect transistor (MOSFET), its robustness in harsh operating conditions is unknown. In this work, the short-circuit (SC) robustness of 650-V GaN/SiC cascode devices is characterized, analyzed, and compared with that of several mainstream SiC MOSFETs. GaN/SiC cascode devices exhibit competitive SC capability. Different failure modes are observed: thermal runaway in the SiC JFET of the cascode device and gate-to-source breakdown in the SiC MOSFET. The difference is associated with the configuration of the dielectric above SiC in the JFET and the source pad layout. According to the waveforms in SC events, failure spots, and thermal simulation results, a thermal runaway in the SiC JFET is attributed to the positive feedback between the drain leakage current and the junction temperature in the local area (hotspot) without the source pad on the top. The SC withstand time of the cascode device can be extended by reduction of the active area without the source pad. [ABSTRACT FROM AUTHOR]

Enhancement-mode (E-mode) p-channel gallium nitride (GaN) field-effect transistors (p-FETs) are essential components for GaN-based complementary logic circuits. For the ease of integration with n-FETs, they could be fabricated on the commercial p-GaN gate high-electron-mobility-transistor (HEMT) platform, on which the two-dimensional electron gas at the AlGaN/GaN hetero-interface is completely depleted in as-grown epi-structures. However, under the gated region where p-GaN is recessed and depleted at thermal equilibrium, a parasitic electron channel (PEC) could appear at the AlGaN/GaN interface. This Letter reports experimental investigations on the PEC with specifically designed structures, confirming that the PEC does exist but imposes limited impacts on electrical characteristics of p-FETs. When connected with an external contact, the PEC could act as a back gate to modulate the overlaying p-channel. If isolated from external contacts, which is the case of p-FETs under normal operations, electrons in the PEC would redistribute under the active region of p-FETs in the horizontal direction (i.e., parallel to the surface) under different biases but are mostly confined near the AlGaN/GaN interface in the vertical direction (i.e., perpendicular to the surface). [ABSTRACT FROM AUTHOR]

This article was originally published online on 27 December 2023 with an error in the affiliation. The affiliation appears correct above. All online versions of this article were corrected on 4 April 2024.By Yingjie Wang; Sen Huang; Qimeng Jiang; Xinhua Wang; Zhongchen Ji; Jie Fan; Haibo Yin; Ke Wei; Xinyu Liu; Qian Sun and Kevin J. ChenReported by Author; Author; Author; Author; Author; Author; Author; Author; Author; Author; Author [Extracted from the article]

GaN ${p}$ -channel field-effect transistors (${p}$ -FETs) are essential components for implementing the energy-efficient complementary logic circuitry for monolithic GaN power integration. This letter reports the threshold voltage (${V}_{\mathrm {TH}}$) instability of ${p}$ -channel GaN MOSFETs with Al2O3 as the gate dielectric. When the gate-to-source bias sweeps toward the negative direction, the ${V}_{\mathrm {TH}}$ exhibits a shift toward more negative values. The impacts of such ${V}_{\mathrm {TH}}$ instability on GaN complementary logic circuits are characterized using logic inverters and ring oscillators. It is shown that impacts on circuit functions are limited with an operating voltage swing below 5 V. However, the propagation delay could be gradually prolonged, as a result of the drifting ${V}_{\mathrm {TH}}$. [ABSTRACT FROM AUTHOR]

An AlGaN-recess-free, ultrathin-barrier (UTB) AlGaN (<6 nm)/GaN heterostructure is presented for the fabrication and integration of AlGaN/GaN enhancement/depletion-mode (E/D-mode) heterojunction field-effect transistors (HFETs), and metal–insulator-semiconductor HFETs (MIS-HFETs). The 2D electron gas in the access region of the UTB-AlGaN/GaN (MIS)HFETs can effectively be recovered by a low-pressure chemical-vapor-deposited SiNx passivation layer (LPCVD-SiNx), which is capable of introducing about 2.75 × 1013 cm−2 positive fixed charges at the LPCVD-SiNx/(Al)GaN interface. LPCVD-SiNx can also serve as a good gate insulator for D-mode MIS-HFETs. Using the self-terminating etching of LPCVD-SiNx on III-nitride as well as a low-damage remote plasma pretreatment, high uniformity E-mode HFETs and low-hysteresis E-mode MIS-HFETs have been fabricated using the GaN-on-Si platform. E/D-mode MIS-HFET inverters with a large logic swing have also been demonstrated on this platform. The UTB-AlGaN/GaN heterostructure is an attractive technology platform for the on-chip integration of power and RF devices with power-driven circuits for GaN-based smart power integrated circuits. [ABSTRACT FROM AUTHOR]

A normally-off SiC-JFET/GaN-HEMT cascode device is recently proposed, featuring a cascode configuration that incorporates a high-voltage (i.e., 1200 V) SiC junction field effect transistor (JFET) and a low-voltage GaN high electron mobility transistor (HEMT). This cascode device exhibits superior thermal stability and switching performance compared to the SiC MOSFETs, but also inevitably presents challenge in dv/dt-control as the input gate does not directly control the high-voltage JFET. Since dv/dt-control is of great importance to the management and suppression of electromagnetic interference in power electronics systems, methods of controlling the dv/dt rates of SiC/GaN cascode devices need to be developed. In this article, we conduct systematic investigation on different dv/dt control schemes with theoretical analysis and experimental evaluation. A dv/dt-control method based on diode-clamped external JFET gate resistor is proposed and evaluated by comparing it with other more conventional methods. The proposed dv/dt-control method is verified to provide a balanced dv/dt-control on the device turn-on and turn-off. [ABSTRACT FROM AUTHOR]

GaN power transistors are attracting increasing attention for next-generation power switching applications. However, GaN power transistors should not be regarded as a direct replacement for silicon power metal–oxide–semiconductor field-effect transistors, since the unique properties of GaN power transistors require special treatment. In this work we review a unique and critical property of GaN power transistors, the dynamic threshold voltage (Vth). GaN power transistors feature a p-GaN gate structure, while the gate metal contacts the p-GaN layer through a Schottky junction. This unique p-GaN gate structure is distinctively different from the silicon metal–oxide–semiconductor gate structure in that the p-GaN layer is actually a floating region without direct electrical contact to the external electrodes of the device. The floating p-GaN layer enables a charge storage process during the switching operation of a p-GaN gate high-electron-mobility transistor. Through carefully designed experiments, the strong correlation between charge storage and the dynamic Vth shift has been revealed; this also serves as an approach to accurately predict the dynamic Vth during switching operation. The influence of the dynamic Vth on power switching applications is discussed. For example, with a positive dynamic Vth shift, the reverse conduction voltage of a GaN power transistor is significantly increased, adding to the power loss. This positive Vth shift also demands a sufficiently high gate drive voltage to ensure that the GaN power transistor can be fully turned on, which reduces the safety margin for the gate reliability of the device. To design a GaN based power switching circuit, accurate simulation of the device/circuit characteristics is necessary. Circuit simulations that do not consider the dynamic Vth lead to a large deviation from the measurement circuit characteristics. We demonstrate that by incorporating the dynamic Vth into the circuit model this deviation can be effectively eliminated. [ABSTRACT FROM AUTHOR]

A gallium nitride (GaN) ring oscillator based on high-performance one-chip complementary logic (CL) inverters is demonstrated on a conventional ${p}$ -GaN gate power HEMT (high-electron-mobility transistor) platform. It manifests the feasibility of the multiple-stage monolithic integration of GaN CL gates, the most energy-efficient digital circuit configuration, and consequently the potential of deploying CL circuits in the all-GaN power integration as peripheral circuits with higher energy efficiency. Thanks to the successful monolithic integration of enhancement-mode ${p}$ -channel and ${n}$ -channel field-effect transistors, the integrated CL inverters in this work present remarkable performances, including stringent rail-to-rail operations, substantially suppressed static power dissipation at both logic ‘low’ and ‘high’ states, suitable transition threshold voltages of ~2.0 V (40% of the common 5-V supply) and wide noise margins above 1.8 V (36% of 5 V). [ABSTRACT FROM AUTHOR]

Systematic characterizations of a cascode device with a low-voltage enhance-mode (E-mode) p-GaN gate high-electron mobility transistor as the control device and a high-voltage (HV) depletion-mode (D-mode) silicon carbide junction field effect transistor (JFET) as the voltage blocking device are presented in this article. The demonstrated device with a breakdown voltage rating of 1200 V and a static on-resistance (RON) of 100 mΩ features small device capacitances with fast switching speed, avalanche breakdown capability, thermally stable threshold voltage (VTH), and no dynamic RON degradation. To identify its safe operation in the off-state with a high drain bias, the off-state middle point voltage (VM) between the E-mode device drain and D-mode device source is investigated. A relatively low off-state VM is achieved under both static and dynamic modes. In addition to the device-level characterization, a custom-designed double-pulse test circuit is built to evaluate the transient switching performance of the cascode device. Optimal gate drive conditions are proposed to 1) overcome the drain bias induced positive dynamic VTH shift; and 2) suppress the increased dynamic off-state leakage current (IOFF) induced by on-state hole injection. Under 800 V/16 A testing conditions, high switching speed with the drain voltage peak slew rates of 72 V/ns during turn-on and 121 V/ns during turn-off is achieved. [ABSTRACT FROM AUTHOR]

The low-temperature gate reliability of Schottky-type p-GaN gate AlGaN/GaN heterojunction field-effect transistors under forward gate voltage stress is investigated. Both temperature-accelerated and voltage-accelerated time-dependent gate breakdown stress experiments are performed. The p-GaN gate exhibits a shorter time-to-failure at a lower temperature. It is found that the time-to-failure at "use conditions" predicted by acceleration tests at high gate bias stress could be overestimated at low temperatures. Such a discrepancy stems from the distinct dominant gate leakage mechanisms at high/low gate bias stress conditions. The dominant physical mechanism of the low-temperature gate leakage current is identified to be Poole–Frenkel emission at low gate bias and Fowler–Nordheim tunneling at high bias. From the physical model, a more accurate lifetime projection can be obtained for given use conditions. [ABSTRACT FROM AUTHOR]

In this paper, we carried out a systematic comparison between the enhancement-mode GaN-based fully recessed metal-insulator-semiconductor field-effect transistors (MIS-FETs) and partially recessed MIS-high-electron-mobility transistors (MIS-HEMTs) with the same gate dielectric stack (LPCVD-SiNx/PECVD-SiNx) that has delivered promising long-term reliability and stability. Despite a moderately larger on-resistance (${R}_{ \mathrm{ON}}$), the MIS-FETs deliver superior ${V}_{\text {TH}}$ uniformity and thermal stability. Under long-term gate bias stress, both the MIS-HEMT and MIS-FET deliver similar small positive-bias temperature instability, while the negative-bias temperature instability of the MIS-HEMT is much larger than that of MIS-FET. The MIS-FET also delivers a higher ${V}_{\text {TH}}$ stability than the MIS-HEMT under dynamic gate bias stress. It is suggested that the differences in ${V}_{\text {TH}}$ stability mainly originate from the different spatial separation between the trap states and the conducting channel, with it being larger in MIS-HEMT than in MIS-FET. [ABSTRACT FROM AUTHOR]

A SiC trench metal-oxide-semiconductor field-effect transistor (MOSFET) with a self-biased p-shield (SBS-MOS) is proposed and comprehensively studied. The p-shield region is used to reduce the high oxide field at the OFF-state, which would otherwise be detrimental to the device long-term reliability. A self-biasing network is designed to raise the potential of the pshield in the SBS-MOS, so that the parasitic junction field effect transistor (JFET) is driven synchronously with the MOS-gate. Mixed-mode numerical simulations are carried out to study the performance of the proposed device. The SBS-MOS boasts a reduced specific ON-resistance (RON-SP) compared with the trench MOSFET with a grounded p-shield (GS-MOS), by the reduction of the JFET resistance and/or further down-scaling of the cell size. To synchronously drive the JFET region, only a slightly larger gate charge is required for the SBS-MOS. Therefore, a low OFF-state oxide field, a low RON-SP and a low QGD are simultaneously achieved in the proposed SBS-MOS. [ABSTRACT FROM AUTHOR]

In addition to surface- and buffer-trapping, interface/border trapping and the consequent VTH shift in insulated-gate GaN power transistors could also cause RON increase, due to the reduced gate overdrive. This work reports on a systematic study of the trapping mechanisms in normally-on/off insulated-gate GaN transistors subjected to dynamic (AC) and static (DC) gate stress. The fast dynamic characterizations featuring an ultrashort measurement delay of 10−7 s minimize the recovery during measurement and enable a quantitative evaluation of VTH shift-induced RON increase. By analyzing the time-resolved instability in normally-on MIS-HEMT and normally-off MIS-FET with fully recessed barrier, we elucidate several key mechanisms including: (i) recessing the polarized III-nitride barrier layer can suppress VTH shift during ON/OFF switching; (ii) AC stress, which has more practical implication for lifetime projection for power switching applications, produces smaller VTH shift and RON increase comparing to DC stress; (iii) Sufficient gate overdrive at ON state and lower channel resistance in normally-on MIS-HEMT allow a better tolerance to VTH shift. Primary trapping effects in an insulated-gate GaN power transistor. [ABSTRACT FROM AUTHOR]

A GaN/SiC hybrid field-effect transistor (HyFET) is proposed as a high-voltage power device that provides a high-mobility lateral AlGaN/GaN channel to reduce the channel resistance and a vertical SiC drift region to sustain the high OFF-state voltage. The performance of the HyFET is evaluated by numerical device simulations. Compared with the conventional SiC MOSFET, the HyFET exhibits a greatly reduced R\mathrm{\scriptscriptstyle ON} together with a low C\mathrm{ GD} and low gate charges. The figures of merit Q\mathrm{ G}\times R\mathrm{\scriptscriptstyle ON} and Q\mathrm{ GD}\times R\mathrm{\scriptscriptstyle ON} of the HyFET are dramatically improved. [ABSTRACT FROM AUTHOR]

The temperature dependence of current collapse (CC) in AlGaN/GaN high-electron mobility transistors on silicon substrate is studied in this paper. Devices without and with Si3N4 passivation are used to investigate the behavior of surface- and buffer-induced CC, respectively. It is found that the degree of surface-induced CC in unpassivated devices has a weak temperature dependence, which is induced by the cancelling out between enhanced carrier injection based on surface hopping and enhanced emission when the temperature is increased. On the other hand, the degree of buffer-induced CC in the Si3N4 passivated devices is reduced at higher temperature since the energy of hot electrons is reduced due to the phonon scattering and the trapping of hot electrons in the buffer is mitigated. Temperature-dependent transient measurement is also carried out to investigate the recovery process for these two type of CC. Two types of trap levels are identified in the unpassivated and Si3N4 passivated devices, respectively. The trap level $E1$ with an activation energy of 0.08 eV is supposed to be related to the surface trapping, while $E2$ with an activation energy of 0.22 eV is located in the buffer layer. [ABSTRACT FROM AUTHOR]

Various 2D/3D heterostructures can be created by harnessing the advantages of both the layered two-dimensional semiconductors and bulk materials. A semiconducting gate field-effect transistor (SG-FET) structure based on 2D/3D heterostructures is proposed here. The SG-FET is demonstrated on an AlGaN/GaN high-electron mobility transistor (HEMT) by adopting single-layer MoS2 as the gate electrode. The MoS2 semiconducting gate can effectively turn on and turn off the HEMT without sacrificing the subthreshold swing and breakdown voltage. Most importantly, the proposed semiconducting gate can deliver inherent over-voltage protection for field-effect transistors (FETs). Furthermore, the self-adjustable semiconducting gate potential with drain bias can even boost the ON-current while guaranteeing the safe operation of FET. In implementing the semiconducting gate, the layered two-dimensional materials such as the adopted MoS2 have several important benefits such as the feasibility of high-quality crystals on different gate dielectrics and the good controllability of semiconducting gate depletion threshold voltage by the layer thickness. The demonstrated semiconducting gate as over-voltage protection for HEMT can be extended to other FETs, which can become another advantageous arena for the possible applications of the layered two-dimensional materials. [ABSTRACT FROM AUTHOR]